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418ec858 | 1 | /* |
d789b5f5 | 2 | * Copyright 2008-2011 Freescale Semiconductor, Inc. |
418ec858 KG |
3 | * |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * Version 2 as published by the Free Software Foundation. | |
7 | */ | |
8 | ||
83d40dfd KG |
9 | #ifndef _FSL_LAW_H_ |
10 | #define _FSL_LAW_H_ | |
11 | ||
12 | #include <asm/io.h> | |
13 | ||
418ec858 KG |
14 | #define LAW_EN 0x80000000 |
15 | ||
83d40dfd KG |
16 | #define SET_LAW_ENTRY(idx, a, sz, trgt) \ |
17 | { .index = idx, .addr = a, .size = sz, .trgt_id = trgt } | |
18 | ||
f060054d KG |
19 | #define SET_LAW(a, sz, trgt) \ |
20 | { .index = -1, .addr = a, .size = sz, .trgt_id = trgt } | |
21 | ||
83d40dfd KG |
22 | enum law_size { |
23 | LAW_SIZE_4K = 0xb, | |
24 | LAW_SIZE_8K, | |
25 | LAW_SIZE_16K, | |
26 | LAW_SIZE_32K, | |
27 | LAW_SIZE_64K, | |
28 | LAW_SIZE_128K, | |
29 | LAW_SIZE_256K, | |
30 | LAW_SIZE_512K, | |
31 | LAW_SIZE_1M, | |
32 | LAW_SIZE_2M, | |
33 | LAW_SIZE_4M, | |
34 | LAW_SIZE_8M, | |
35 | LAW_SIZE_16M, | |
36 | LAW_SIZE_32M, | |
37 | LAW_SIZE_64M, | |
38 | LAW_SIZE_128M, | |
39 | LAW_SIZE_256M, | |
40 | LAW_SIZE_512M, | |
41 | LAW_SIZE_1G, | |
42 | LAW_SIZE_2G, | |
43 | LAW_SIZE_4G, | |
44 | LAW_SIZE_8G, | |
45 | LAW_SIZE_16G, | |
46 | LAW_SIZE_32G, | |
47 | }; | |
48 | ||
de3cbd78 | 49 | #define law_size_bits(sz) (__ilog2_u64(sz) - 1) |
e71755f8 | 50 | #define lawar_size(x) (1ULL << ((x & 0x3f) + 1)) |
de3cbd78 | 51 | |
418ec858 KG |
52 | #ifdef CONFIG_FSL_CORENET |
53 | enum law_trgt_if { | |
54 | LAW_TRGT_IF_PCIE_1 = 0x00, | |
55 | LAW_TRGT_IF_PCIE_2 = 0x01, | |
56 | LAW_TRGT_IF_PCIE_3 = 0x02, | |
9ab87d04 | 57 | LAW_TRGT_IF_PCIE_4 = 0x03, |
418ec858 KG |
58 | LAW_TRGT_IF_RIO_1 = 0x08, |
59 | LAW_TRGT_IF_RIO_2 = 0x09, | |
60 | ||
61 | LAW_TRGT_IF_DDR_1 = 0x10, | |
62 | LAW_TRGT_IF_DDR_2 = 0x11, /* 2nd controller */ | |
a4c66509 YS |
63 | LAW_TRGT_IF_DDR_3 = 0x12, |
64 | LAW_TRGT_IF_DDR_4 = 0x13, | |
418ec858 | 65 | LAW_TRGT_IF_DDR_INTRLV = 0x14, |
a4c66509 YS |
66 | LAW_TRGT_IF_DDR_INTLV_34 = 0x15, |
67 | LAW_TRGT_IF_DDR_INTLV_123 = 0x17, | |
68 | LAW_TRGT_IF_DDR_INTLV_1234 = 0x16, | |
418ec858 KG |
69 | LAW_TRGT_IF_BMAN = 0x18, |
70 | LAW_TRGT_IF_DCSR = 0x1d, | |
377ffcfa | 71 | LAW_TRGT_IF_CCSR = 0x1e, |
418ec858 KG |
72 | LAW_TRGT_IF_LBC = 0x1f, |
73 | LAW_TRGT_IF_QMAN = 0x3c, | |
6eaeba23 SL |
74 | |
75 | LAW_TRGT_IF_MAPLE = 0x50, | |
418ec858 KG |
76 | }; |
77 | #define LAW_TRGT_IF_DDR LAW_TRGT_IF_DDR_1 | |
3854173a | 78 | #define LAW_TRGT_IF_IFC LAW_TRGT_IF_LBC |
418ec858 | 79 | #else |
83d40dfd KG |
80 | enum law_trgt_if { |
81 | LAW_TRGT_IF_PCI = 0x00, | |
82 | LAW_TRGT_IF_PCI_2 = 0x01, | |
83 | #ifndef CONFIG_MPC8641 | |
84 | LAW_TRGT_IF_PCIE_1 = 0x02, | |
85 | #endif | |
64501c66 | 86 | #if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132) |
765b0bdb PJ |
87 | LAW_TRGT_IF_OCN_DSP = 0x03, |
88 | #else | |
8d949aff | 89 | #if !defined(CONFIG_MPC8572) && !defined(CONFIG_P2020) |
83d40dfd | 90 | LAW_TRGT_IF_PCIE_3 = 0x03, |
765b0bdb | 91 | #endif |
83d40dfd KG |
92 | #endif |
93 | LAW_TRGT_IF_LBC = 0x04, | |
94 | LAW_TRGT_IF_CCSR = 0x08, | |
765b0bdb | 95 | LAW_TRGT_IF_DSP_CCSR = 0x09, |
3b75e982 | 96 | LAW_TRGT_IF_PLATFORM_SRAM = 0x0a, |
83d40dfd KG |
97 | LAW_TRGT_IF_DDR_INTRLV = 0x0b, |
98 | LAW_TRGT_IF_RIO = 0x0c, | |
64501c66 PJ |
99 | #if defined(CONFIG_BSC9132) |
100 | LAW_TRGT_IF_CLASS_DSP = 0x0d, | |
101 | #else | |
de3cbd78 | 102 | LAW_TRGT_IF_RIO_2 = 0x0d, |
64501c66 | 103 | #endif |
67a719da | 104 | LAW_TRGT_IF_DPAA_SWP_SRAM = 0x0e, |
83d40dfd KG |
105 | LAW_TRGT_IF_DDR = 0x0f, |
106 | LAW_TRGT_IF_DDR_2 = 0x16, /* 2nd controller */ | |
a4c66509 YS |
107 | /* place holder for 3-way and 4-way interleaving */ |
108 | LAW_TRGT_IF_DDR_3, | |
109 | LAW_TRGT_IF_DDR_4, | |
110 | LAW_TRGT_IF_DDR_INTLV_34, | |
111 | LAW_TRGT_IF_DDR_INTLV_123, | |
112 | LAW_TRGT_IF_DDR_INTLV_1234, | |
83d40dfd KG |
113 | }; |
114 | #define LAW_TRGT_IF_DDR_1 LAW_TRGT_IF_DDR | |
115 | #define LAW_TRGT_IF_PCI_1 LAW_TRGT_IF_PCI | |
116 | #define LAW_TRGT_IF_PCIX LAW_TRGT_IF_PCI | |
117 | #define LAW_TRGT_IF_PCIE_2 LAW_TRGT_IF_PCI_2 | |
a09b9b68 | 118 | #define LAW_TRGT_IF_RIO_1 LAW_TRGT_IF_RIO |
d789b5f5 | 119 | #define LAW_TRGT_IF_IFC LAW_TRGT_IF_LBC |
83d40dfd KG |
120 | |
121 | #ifdef CONFIG_MPC8641 | |
122 | #define LAW_TRGT_IF_PCIE_1 LAW_TRGT_IF_PCI | |
123 | #endif | |
124 | ||
8d949aff | 125 | #if defined(CONFIG_MPC8572) || defined(CONFIG_P2020) |
83d40dfd KG |
126 | #define LAW_TRGT_IF_PCIE_3 LAW_TRGT_IF_PCI |
127 | #endif | |
418ec858 | 128 | #endif /* CONFIG_FSL_CORENET */ |
83d40dfd KG |
129 | |
130 | struct law_entry { | |
131 | int index; | |
132 | phys_addr_t addr; | |
133 | enum law_size size; | |
134 | enum law_trgt_if trgt_id; | |
135 | }; | |
136 | ||
137 | extern void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id); | |
f060054d | 138 | extern int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id); |
ba04f701 | 139 | extern int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id); |
f784e32b | 140 | extern int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id); |
418ec858 | 141 | extern struct law_entry find_law(phys_addr_t addr); |
83d40dfd KG |
142 | extern void disable_law(u8 idx); |
143 | extern void init_laws(void); | |
ddcebcb6 | 144 | extern void print_laws(void); |
83d40dfd KG |
145 | |
146 | /* define in board code */ | |
147 | extern struct law_entry law_table[]; | |
148 | extern int num_law_entries; | |
149 | #endif |