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42dbd667 | 1 | /* |
3f0202ed | 2 | * Copyright (C) 2004-2008,2010 Freescale Semiconductor, Inc. |
42dbd667 AV |
3 | * |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | */ | |
12 | ||
13 | #ifndef __ASM_PPC_FSL_LBC_H | |
14 | #define __ASM_PPC_FSL_LBC_H | |
15 | ||
16 | #include <config.h> | |
17 | ||
18 | /* BR - Base Registers | |
19 | */ | |
20 | #define BR0 0x5000 /* Register offset to immr */ | |
21 | #define BR1 0x5008 | |
22 | #define BR2 0x5010 | |
23 | #define BR3 0x5018 | |
24 | #define BR4 0x5020 | |
25 | #define BR5 0x5028 | |
26 | #define BR6 0x5030 | |
27 | #define BR7 0x5038 | |
28 | ||
29 | #define BR_BA 0xFFFF8000 | |
30 | #define BR_BA_SHIFT 15 | |
c51fc5d5 KG |
31 | #define BR_XBA 0x00006000 |
32 | #define BR_XBA_SHIFT 13 | |
42dbd667 AV |
33 | #define BR_PS 0x00001800 |
34 | #define BR_PS_SHIFT 11 | |
35 | #define BR_PS_8 0x00000800 /* Port Size 8 bit */ | |
36 | #define BR_PS_16 0x00001000 /* Port Size 16 bit */ | |
37 | #define BR_PS_32 0x00001800 /* Port Size 32 bit */ | |
38 | #define BR_DECC 0x00000600 | |
39 | #define BR_DECC_SHIFT 9 | |
40 | #define BR_DECC_OFF 0x00000000 | |
41 | #define BR_DECC_CHK 0x00000200 | |
42 | #define BR_DECC_CHK_GEN 0x00000400 | |
43 | #define BR_WP 0x00000100 | |
44 | #define BR_WP_SHIFT 8 | |
45 | #define BR_MSEL 0x000000E0 | |
46 | #define BR_MSEL_SHIFT 5 | |
47 | #define BR_MS_GPCM 0x00000000 /* GPCM */ | |
48 | #define BR_MS_FCM 0x00000020 /* FCM */ | |
c8c5fc26 | 49 | #ifdef CONFIG_MPC83xx |
42dbd667 | 50 | #define BR_MS_SDRAM 0x00000060 /* SDRAM */ |
c8c5fc26 AV |
51 | #elif defined(CONFIG_MPC85xx) |
52 | #define BR_MS_SDRAM 0x00000000 /* SDRAM */ | |
53 | #endif | |
42dbd667 AV |
54 | #define BR_MS_UPMA 0x00000080 /* UPMA */ |
55 | #define BR_MS_UPMB 0x000000A0 /* UPMB */ | |
56 | #define BR_MS_UPMC 0x000000C0 /* UPMC */ | |
2c7920af | 57 | #if !defined(CONFIG_MPC834x) |
42dbd667 AV |
58 | #define BR_ATOM 0x0000000C |
59 | #define BR_ATOM_SHIFT 2 | |
60 | #endif | |
61 | #define BR_V 0x00000001 | |
62 | #define BR_V_SHIFT 0 | |
63 | ||
740280e6 SP |
64 | #define UPMA 0 |
65 | #define UPMB 1 | |
66 | #define UPMC 2 | |
67 | ||
2c7920af | 68 | #if defined(CONFIG_MPC834x) |
42dbd667 AV |
69 | #define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V) |
70 | #else | |
71 | #define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V) | |
72 | #endif | |
73 | ||
ea154a17 | 74 | /* Convert an address into the right format for the BR registers */ |
c51fc5d5 | 75 | #if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_FSL_ELBC) |
ea154a17 KG |
76 | #define BR_PHYS_ADDR(x) ((unsigned long)((x & 0x0ffff8000ULL) | \ |
77 | ((x & 0x300000000ULL) >> 19))) | |
78 | #else | |
79 | #define BR_PHYS_ADDR(x) (x & 0xffff8000) | |
80 | #endif | |
81 | ||
42dbd667 AV |
82 | /* OR - Option Registers |
83 | */ | |
84 | #define OR0 0x5004 /* Register offset to immr */ | |
85 | #define OR1 0x500C | |
86 | #define OR2 0x5014 | |
87 | #define OR3 0x501C | |
88 | #define OR4 0x5024 | |
89 | #define OR5 0x502C | |
90 | #define OR6 0x5034 | |
91 | #define OR7 0x503C | |
92 | ||
93 | #define OR_GPCM_AM 0xFFFF8000 | |
94 | #define OR_GPCM_AM_SHIFT 15 | |
c51fc5d5 KG |
95 | #define OR_GPCM_XAM 0x00006000 |
96 | #define OR_GPCM_XAM_SHIFT 13 | |
42dbd667 AV |
97 | #define OR_GPCM_BCTLD 0x00001000 |
98 | #define OR_GPCM_BCTLD_SHIFT 12 | |
99 | #define OR_GPCM_CSNT 0x00000800 | |
100 | #define OR_GPCM_CSNT_SHIFT 11 | |
101 | #define OR_GPCM_ACS 0x00000600 | |
102 | #define OR_GPCM_ACS_SHIFT 9 | |
c8c5fc26 AV |
103 | #define OR_GPCM_ACS_DIV2 0x00000600 |
104 | #define OR_GPCM_ACS_DIV4 0x00000400 | |
42dbd667 AV |
105 | #define OR_GPCM_XACS 0x00000100 |
106 | #define OR_GPCM_XACS_SHIFT 8 | |
107 | #define OR_GPCM_SCY 0x000000F0 | |
108 | #define OR_GPCM_SCY_SHIFT 4 | |
109 | #define OR_GPCM_SCY_1 0x00000010 | |
110 | #define OR_GPCM_SCY_2 0x00000020 | |
111 | #define OR_GPCM_SCY_3 0x00000030 | |
112 | #define OR_GPCM_SCY_4 0x00000040 | |
113 | #define OR_GPCM_SCY_5 0x00000050 | |
114 | #define OR_GPCM_SCY_6 0x00000060 | |
115 | #define OR_GPCM_SCY_7 0x00000070 | |
116 | #define OR_GPCM_SCY_8 0x00000080 | |
117 | #define OR_GPCM_SCY_9 0x00000090 | |
118 | #define OR_GPCM_SCY_10 0x000000a0 | |
119 | #define OR_GPCM_SCY_11 0x000000b0 | |
120 | #define OR_GPCM_SCY_12 0x000000c0 | |
121 | #define OR_GPCM_SCY_13 0x000000d0 | |
122 | #define OR_GPCM_SCY_14 0x000000e0 | |
123 | #define OR_GPCM_SCY_15 0x000000f0 | |
124 | #define OR_GPCM_SETA 0x00000008 | |
125 | #define OR_GPCM_SETA_SHIFT 3 | |
126 | #define OR_GPCM_TRLX 0x00000004 | |
127 | #define OR_GPCM_TRLX_SHIFT 2 | |
3f0202ed LC |
128 | #define OR_GPCM_TRLX_CLEAR 0x00000000 |
129 | #define OR_GPCM_TRLX_SET 0x00000004 | |
42dbd667 AV |
130 | #define OR_GPCM_EHTR 0x00000002 |
131 | #define OR_GPCM_EHTR_SHIFT 1 | |
3f0202ed LC |
132 | #define OR_GPCM_EHTR_CLEAR 0x00000000 |
133 | #define OR_GPCM_EHTR_SET 0x00000002 | |
42dbd667 AV |
134 | #define OR_GPCM_EAD 0x00000001 |
135 | #define OR_GPCM_EAD_SHIFT 0 | |
136 | ||
c8c5fc26 AV |
137 | /* helpers to convert values into an OR address mask (GPCM mode) */ |
138 | #define P2SZ_TO_AM(s) ((~((s) - 1)) & 0xffff8000) /* must be pow of 2 */ | |
139 | #define MEG_TO_AM(m) P2SZ_TO_AM((m) << 20) | |
140 | ||
42dbd667 AV |
141 | #define OR_FCM_AM 0xFFFF8000 |
142 | #define OR_FCM_AM_SHIFT 15 | |
c51fc5d5 KG |
143 | #define OR_FCM_XAM 0x00006000 |
144 | #define OR_FCM_XAM_SHIFT 13 | |
42dbd667 AV |
145 | #define OR_FCM_BCTLD 0x00001000 |
146 | #define OR_FCM_BCTLD_SHIFT 12 | |
147 | #define OR_FCM_PGS 0x00000400 | |
148 | #define OR_FCM_PGS_SHIFT 10 | |
149 | #define OR_FCM_CSCT 0x00000200 | |
150 | #define OR_FCM_CSCT_SHIFT 9 | |
151 | #define OR_FCM_CST 0x00000100 | |
152 | #define OR_FCM_CST_SHIFT 8 | |
153 | #define OR_FCM_CHT 0x00000080 | |
154 | #define OR_FCM_CHT_SHIFT 7 | |
155 | #define OR_FCM_SCY 0x00000070 | |
156 | #define OR_FCM_SCY_SHIFT 4 | |
157 | #define OR_FCM_SCY_1 0x00000010 | |
158 | #define OR_FCM_SCY_2 0x00000020 | |
159 | #define OR_FCM_SCY_3 0x00000030 | |
160 | #define OR_FCM_SCY_4 0x00000040 | |
161 | #define OR_FCM_SCY_5 0x00000050 | |
162 | #define OR_FCM_SCY_6 0x00000060 | |
163 | #define OR_FCM_SCY_7 0x00000070 | |
164 | #define OR_FCM_RST 0x00000008 | |
165 | #define OR_FCM_RST_SHIFT 3 | |
166 | #define OR_FCM_TRLX 0x00000004 | |
167 | #define OR_FCM_TRLX_SHIFT 2 | |
168 | #define OR_FCM_EHTR 0x00000002 | |
169 | #define OR_FCM_EHTR_SHIFT 1 | |
170 | ||
171 | #define OR_UPM_AM 0xFFFF8000 | |
172 | #define OR_UPM_AM_SHIFT 15 | |
173 | #define OR_UPM_XAM 0x00006000 | |
174 | #define OR_UPM_XAM_SHIFT 13 | |
175 | #define OR_UPM_BCTLD 0x00001000 | |
176 | #define OR_UPM_BCTLD_SHIFT 12 | |
177 | #define OR_UPM_BI 0x00000100 | |
178 | #define OR_UPM_BI_SHIFT 8 | |
179 | #define OR_UPM_TRLX 0x00000004 | |
180 | #define OR_UPM_TRLX_SHIFT 2 | |
181 | #define OR_UPM_EHTR 0x00000002 | |
182 | #define OR_UPM_EHTR_SHIFT 1 | |
183 | #define OR_UPM_EAD 0x00000001 | |
184 | #define OR_UPM_EAD_SHIFT 0 | |
185 | ||
186 | #define OR_SDRAM_AM 0xFFFF8000 | |
187 | #define OR_SDRAM_AM_SHIFT 15 | |
188 | #define OR_SDRAM_XAM 0x00006000 | |
189 | #define OR_SDRAM_XAM_SHIFT 13 | |
190 | #define OR_SDRAM_COLS 0x00001C00 | |
191 | #define OR_SDRAM_COLS_SHIFT 10 | |
192 | #define OR_SDRAM_ROWS 0x000001C0 | |
193 | #define OR_SDRAM_ROWS_SHIFT 6 | |
194 | #define OR_SDRAM_PMSEL 0x00000020 | |
195 | #define OR_SDRAM_PMSEL_SHIFT 5 | |
196 | #define OR_SDRAM_EAD 0x00000001 | |
197 | #define OR_SDRAM_EAD_SHIFT 0 | |
198 | ||
199 | #define OR_AM_32KB 0xFFFF8000 | |
200 | #define OR_AM_64KB 0xFFFF0000 | |
201 | #define OR_AM_128KB 0xFFFE0000 | |
202 | #define OR_AM_256KB 0xFFFC0000 | |
203 | #define OR_AM_512KB 0xFFF80000 | |
204 | #define OR_AM_1MB 0xFFF00000 | |
205 | #define OR_AM_2MB 0xFFE00000 | |
206 | #define OR_AM_4MB 0xFFC00000 | |
207 | #define OR_AM_8MB 0xFF800000 | |
208 | #define OR_AM_16MB 0xFF000000 | |
209 | #define OR_AM_32MB 0xFE000000 | |
210 | #define OR_AM_64MB 0xFC000000 | |
211 | #define OR_AM_128MB 0xF8000000 | |
212 | #define OR_AM_256MB 0xF0000000 | |
213 | #define OR_AM_512MB 0xE0000000 | |
214 | #define OR_AM_1GB 0xC0000000 | |
215 | #define OR_AM_2GB 0x80000000 | |
216 | #define OR_AM_4GB 0x00000000 | |
217 | ||
6fab2fe7 WG |
218 | /* MxMR - UPM Machine A/B/C Mode Registers |
219 | */ | |
220 | #define MxMR_MAD_MSK 0x0000003f /* Machine Address Mask */ | |
221 | #define MxMR_TLFx_MSK 0x000003c0 /* Refresh Loop Field Mask */ | |
222 | #define MxMR_WLFx_MSK 0x00003c00 /* Write Loop Field Mask */ | |
223 | #define MxMR_WLFx_1X 0x00000400 /* executed 1 time */ | |
224 | #define MxMR_WLFx_2X 0x00000800 /* executed 2 times */ | |
225 | #define MxMR_WLFx_3X 0x00000c00 /* executed 3 times */ | |
226 | #define MxMR_WLFx_4X 0x00001000 /* executed 4 times */ | |
227 | #define MxMR_WLFx_5X 0x00001400 /* executed 5 times */ | |
228 | #define MxMR_WLFx_6X 0x00001800 /* executed 6 times */ | |
229 | #define MxMR_WLFx_7X 0x00001c00 /* executed 7 times */ | |
230 | #define MxMR_WLFx_8X 0x00002000 /* executed 8 times */ | |
231 | #define MxMR_WLFx_9X 0x00002400 /* executed 9 times */ | |
232 | #define MxMR_WLFx_10X 0x00002800 /* executed 10 times */ | |
233 | #define MxMR_WLFx_11X 0x00002c00 /* executed 11 times */ | |
234 | #define MxMR_WLFx_12X 0x00003000 /* executed 12 times */ | |
235 | #define MxMR_WLFx_13X 0x00003400 /* executed 13 times */ | |
236 | #define MxMR_WLFx_14X 0x00003800 /* executed 14 times */ | |
237 | #define MxMR_WLFx_15X 0x00003c00 /* executed 15 times */ | |
238 | #define MxMR_WLFx_16X 0x00000000 /* executed 16 times */ | |
239 | #define MxMR_RLFx_MSK 0x0003c000 /* Read Loop Field Mask */ | |
240 | #define MxMR_GPL_x4DIS 0x00040000 /* GPL_A4 Ouput Line Disable */ | |
241 | #define MxMR_G0CLx_MSK 0x00380000 /* General Line 0 Control Mask */ | |
242 | #define MxMR_DSx_1_CYCL 0x00000000 /* 1 cycle Disable Period */ | |
243 | #define MxMR_DSx_2_CYCL 0x00400000 /* 2 cycle Disable Period */ | |
244 | #define MxMR_DSx_3_CYCL 0x00800000 /* 3 cycle Disable Period */ | |
245 | #define MxMR_DSx_4_CYCL 0x00c00000 /* 4 cycle Disable Period */ | |
246 | #define MxMR_DSx_MSK 0x00c00000 /* Disable Timer Period Mask */ | |
247 | #define MxMR_AMx_MSK 0x07000000 /* Addess Multiplex Size Mask */ | |
3b439792 | 248 | #define MxMR_UWPL 0x08000000 /* LUPWAIT Polarity Mask */ |
6fab2fe7 WG |
249 | #define MxMR_OP_NORM 0x00000000 /* Normal Operation */ |
250 | #define MxMR_OP_WARR 0x10000000 /* Write to Array */ | |
251 | #define MxMR_OP_RARR 0x20000000 /* Read from Array */ | |
252 | #define MxMR_OP_RUNP 0x30000000 /* Run Pattern */ | |
253 | #define MxMR_OP_MSK 0x30000000 /* Command Opcode Mask */ | |
254 | #define MxMR_RFEN 0x40000000 /* Refresh Enable */ | |
255 | #define MxMR_BSEL 0x80000000 /* Bus Select */ | |
256 | ||
42dbd667 AV |
257 | #define LBLAWAR_EN 0x80000000 |
258 | #define LBLAWAR_4KB 0x0000000B | |
259 | #define LBLAWAR_8KB 0x0000000C | |
260 | #define LBLAWAR_16KB 0x0000000D | |
261 | #define LBLAWAR_32KB 0x0000000E | |
262 | #define LBLAWAR_64KB 0x0000000F | |
263 | #define LBLAWAR_128KB 0x00000010 | |
264 | #define LBLAWAR_256KB 0x00000011 | |
265 | #define LBLAWAR_512KB 0x00000012 | |
266 | #define LBLAWAR_1MB 0x00000013 | |
267 | #define LBLAWAR_2MB 0x00000014 | |
268 | #define LBLAWAR_4MB 0x00000015 | |
269 | #define LBLAWAR_8MB 0x00000016 | |
270 | #define LBLAWAR_16MB 0x00000017 | |
271 | #define LBLAWAR_32MB 0x00000018 | |
272 | #define LBLAWAR_64MB 0x00000019 | |
273 | #define LBLAWAR_128MB 0x0000001A | |
274 | #define LBLAWAR_256MB 0x0000001B | |
275 | #define LBLAWAR_512MB 0x0000001C | |
276 | #define LBLAWAR_1GB 0x0000001D | |
277 | #define LBLAWAR_2GB 0x0000001E | |
278 | ||
279 | /* LBCR - Local Bus Configuration Register | |
280 | */ | |
281 | #define LBCR_LDIS 0x80000000 | |
282 | #define LBCR_LDIS_SHIFT 31 | |
283 | #define LBCR_BCTLC 0x00C00000 | |
284 | #define LBCR_BCTLC_SHIFT 22 | |
285 | #define LBCR_LPBSE 0x00020000 | |
286 | #define LBCR_LPBSE_SHIFT 17 | |
287 | #define LBCR_EPAR 0x00010000 | |
288 | #define LBCR_EPAR_SHIFT 16 | |
289 | #define LBCR_BMT 0x0000FF00 | |
290 | #define LBCR_BMT_SHIFT 8 | |
291 | ||
292 | /* LCRR - Clock Ratio Register | |
293 | */ | |
294 | #define LCRR_DBYP 0x80000000 | |
295 | #define LCRR_DBYP_SHIFT 31 | |
296 | #define LCRR_BUFCMDC 0x30000000 | |
297 | #define LCRR_BUFCMDC_SHIFT 28 | |
298 | #define LCRR_BUFCMDC_1 0x10000000 | |
299 | #define LCRR_BUFCMDC_2 0x20000000 | |
300 | #define LCRR_BUFCMDC_3 0x30000000 | |
301 | #define LCRR_BUFCMDC_4 0x00000000 | |
302 | #define LCRR_ECL 0x03000000 | |
303 | #define LCRR_ECL_SHIFT 24 | |
304 | #define LCRR_ECL_4 0x00000000 | |
305 | #define LCRR_ECL_5 0x01000000 | |
306 | #define LCRR_ECL_6 0x02000000 | |
307 | #define LCRR_ECL_7 0x03000000 | |
308 | #define LCRR_EADC 0x00030000 | |
309 | #define LCRR_EADC_SHIFT 16 | |
310 | #define LCRR_EADC_1 0x00010000 | |
311 | #define LCRR_EADC_2 0x00020000 | |
312 | #define LCRR_EADC_3 0x00030000 | |
313 | #define LCRR_EADC_4 0x00000000 | |
a5d212a2 TP |
314 | /* CLKDIV is five bits only on 8536, 8572, and 8610, so far, but the fifth bit |
315 | * should always be zero on older parts that have a four bit CLKDIV. | |
316 | */ | |
317 | #define LCRR_CLKDIV 0x0000001F | |
42dbd667 | 318 | #define LCRR_CLKDIV_SHIFT 0 |
202d9487 KG |
319 | #if defined(CONFIG_MPC83xx) || defined (CONFIG_MPC8540) || \ |
320 | defined(CONFIG_MPC8541) || defined (CONFIG_MPC8555) || \ | |
321 | defined(CONFIG_MPC8560) | |
42dbd667 AV |
322 | #define LCRR_CLKDIV_2 0x00000002 |
323 | #define LCRR_CLKDIV_4 0x00000004 | |
324 | #define LCRR_CLKDIV_8 0x00000008 | |
01df5212 KG |
325 | #elif defined(CONFIG_FSL_CORENET) |
326 | #define LCRR_CLKDIV_8 0x00000002 | |
327 | #define LCRR_CLKDIV_16 0x00000004 | |
328 | #define LCRR_CLKDIV_32 0x00000008 | |
202d9487 KG |
329 | #else |
330 | #define LCRR_CLKDIV_4 0x00000002 | |
331 | #define LCRR_CLKDIV_8 0x00000004 | |
332 | #define LCRR_CLKDIV_16 0x00000008 | |
333 | #endif | |
42dbd667 | 334 | |
f2302d44 SR |
335 | /* LTEDR - Transfer Error Check Disable Register |
336 | */ | |
337 | #define LTEDR_BMD 0x80000000 /* Bus monitor disable */ | |
338 | #define LTEDR_PARD 0x20000000 /* Parity error checking disabled */ | |
339 | #define LTEDR_WPD 0x04000000 /* Write protect error checking diable */ | |
340 | #define LTEDR_WARA 0x00800000 /* Write-after-read-atomic error checking diable */ | |
341 | #define LTEDR_RAWA 0x00400000 /* Read-after-write-atomic error checking disable */ | |
342 | #define LTEDR_CSD 0x00080000 /* Chip select error checking disable */ | |
343 | ||
4e190b03 HW |
344 | /* FMR - Flash Mode Register |
345 | */ | |
346 | #define FMR_CWTO 0x0000F000 | |
347 | #define FMR_CWTO_SHIFT 12 | |
348 | #define FMR_BOOT 0x00000800 | |
349 | #define FMR_ECCM 0x00000100 | |
350 | #define FMR_AL 0x00000030 | |
351 | #define FMR_AL_SHIFT 4 | |
352 | #define FMR_OP 0x00000003 | |
353 | #define FMR_OP_SHIFT 0 | |
354 | ||
355 | /* FIR - Flash Instruction Register | |
356 | */ | |
357 | #define FIR_OP0 0xF0000000 | |
358 | #define FIR_OP0_SHIFT 28 | |
359 | #define FIR_OP1 0x0F000000 | |
360 | #define FIR_OP1_SHIFT 24 | |
361 | #define FIR_OP2 0x00F00000 | |
362 | #define FIR_OP2_SHIFT 20 | |
363 | #define FIR_OP3 0x000F0000 | |
364 | #define FIR_OP3_SHIFT 16 | |
365 | #define FIR_OP4 0x0000F000 | |
366 | #define FIR_OP4_SHIFT 12 | |
367 | #define FIR_OP5 0x00000F00 | |
368 | #define FIR_OP5_SHIFT 8 | |
369 | #define FIR_OP6 0x000000F0 | |
370 | #define FIR_OP6_SHIFT 4 | |
371 | #define FIR_OP7 0x0000000F | |
372 | #define FIR_OP7_SHIFT 0 | |
373 | #define FIR_OP_NOP 0x0 /* No operation and end of sequence */ | |
374 | #define FIR_OP_CA 0x1 /* Issue current column address */ | |
375 | #define FIR_OP_PA 0x2 /* Issue current block+page address */ | |
376 | #define FIR_OP_UA 0x3 /* Issue user defined address */ | |
377 | #define FIR_OP_CM0 0x4 /* Issue command from FCR[CMD0] */ | |
378 | #define FIR_OP_CM1 0x5 /* Issue command from FCR[CMD1] */ | |
379 | #define FIR_OP_CM2 0x6 /* Issue command from FCR[CMD2] */ | |
380 | #define FIR_OP_CM3 0x7 /* Issue command from FCR[CMD3] */ | |
381 | #define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */ | |
382 | #define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */ | |
383 | #define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */ | |
384 | #define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */ | |
385 | #define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */ | |
386 | #define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */ | |
387 | #define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */ | |
388 | #define FIR_OP_RSW 0xF /* Wait then read 1 or 2 bytes */ | |
389 | ||
390 | /* FCR - Flash Command Register | |
391 | */ | |
392 | #define FCR_CMD0 0xFF000000 | |
393 | #define FCR_CMD0_SHIFT 24 | |
394 | #define FCR_CMD1 0x00FF0000 | |
395 | #define FCR_CMD1_SHIFT 16 | |
396 | #define FCR_CMD2 0x0000FF00 | |
397 | #define FCR_CMD2_SHIFT 8 | |
398 | #define FCR_CMD3 0x000000FF | |
399 | #define FCR_CMD3_SHIFT 0 | |
400 | /* FBAR - Flash Block Address Register | |
401 | */ | |
402 | #define FBAR_BLK 0x00FFFFFF | |
403 | ||
404 | /* FPAR - Flash Page Address Register | |
405 | */ | |
406 | #define FPAR_SP_PI 0x00007C00 | |
407 | #define FPAR_SP_PI_SHIFT 10 | |
408 | #define FPAR_SP_MS 0x00000200 | |
409 | #define FPAR_SP_CI 0x000001FF | |
410 | #define FPAR_SP_CI_SHIFT 0 | |
411 | #define FPAR_LP_PI 0x0003F000 | |
412 | #define FPAR_LP_PI_SHIFT 12 | |
413 | #define FPAR_LP_MS 0x00000800 | |
414 | #define FPAR_LP_CI 0x000007FF | |
415 | #define FPAR_LP_CI_SHIFT 0 | |
416 | ||
0088c298 KG |
417 | /* LSDMR - SDRAM Machine Mode Register |
418 | */ | |
419 | #define LSDMR_RFEN (1 << (31 - 1)) | |
420 | #define LSDMR_BSMA1516 (3 << (31 - 10)) | |
421 | #define LSDMR_BSMA1617 (4 << (31 - 10)) | |
422 | #define LSDMR_RFCR5 (3 << (31 - 16)) | |
423 | #define LSDMR_RFCR16 (7 << (31 - 16)) | |
424 | #define LSDMR_PRETOACT3 (3 << (31 - 19)) | |
425 | #define LSDMR_PRETOACT7 (7 << (31 - 19)) | |
426 | #define LSDMR_ACTTORW3 (3 << (31 - 22)) | |
427 | #define LSDMR_ACTTORW7 (7 << (31 - 22)) | |
428 | #define LSDMR_ACTTORW6 (6 << (31 - 22)) | |
429 | #define LSDMR_BL8 (1 << (31 - 23)) | |
430 | #define LSDMR_WRC2 (2 << (31 - 27)) | |
431 | #define LSDMR_WRC4 (0 << (31 - 27)) | |
432 | #define LSDMR_BUFCMD (1 << (31 - 29)) | |
433 | #define LSDMR_CL3 (3 << (31 - 31)) | |
434 | ||
435 | #define LSDMR_OP_NORMAL (0 << (31 - 4)) | |
436 | #define LSDMR_OP_ARFRSH (1 << (31 - 4)) | |
437 | #define LSDMR_OP_SRFRSH (2 << (31 - 4)) | |
438 | #define LSDMR_OP_MRW (3 << (31 - 4)) | |
439 | #define LSDMR_OP_PRECH (4 << (31 - 4)) | |
440 | #define LSDMR_OP_PCHALL (5 << (31 - 4)) | |
441 | #define LSDMR_OP_ACTBNK (6 << (31 - 4)) | |
442 | #define LSDMR_OP_RWINV (7 << (31 - 4)) | |
443 | ||
4e190b03 HW |
444 | /* LTESR - Transfer Error Status Register |
445 | */ | |
446 | #define LTESR_BM 0x80000000 | |
447 | #define LTESR_FCT 0x40000000 | |
448 | #define LTESR_PAR 0x20000000 | |
449 | #define LTESR_WP 0x04000000 | |
450 | #define LTESR_ATMW 0x00800000 | |
451 | #define LTESR_ATMR 0x00400000 | |
452 | #define LTESR_CS 0x00080000 | |
453 | #define LTESR_CC 0x00000001 | |
454 | ||
455 | #ifndef __ASSEMBLY__ | |
456 | /* | |
457 | * Local Bus Controller Registers. | |
458 | */ | |
459 | typedef struct lbus_bank { | |
460 | u32 br; /* Base Register */ | |
461 | u32 or; /* Option Register */ | |
462 | } lbus_bank_t; | |
463 | ||
464 | typedef struct fsl_lbus { | |
465 | lbus_bank_t bank[8]; | |
466 | u8 res0[0x28]; | |
467 | u32 mar; /* UPM Address Register */ | |
468 | u8 res1[0x4]; | |
469 | u32 mamr; /* UPMA Mode Register */ | |
470 | u32 mbmr; /* UPMB Mode Register */ | |
471 | u32 mcmr; /* UPMC Mode Register */ | |
472 | u8 res2[0x8]; | |
473 | u32 mrtpr; /* Memory Refresh Timer Prescaler Register */ | |
474 | u32 mdr; /* UPM Data Register */ | |
475 | u8 res3[0x4]; | |
476 | u32 lsor; /* Special Operation Initiation Register */ | |
477 | u32 lsdmr; /* SDRAM Mode Register */ | |
478 | u8 res4[0x8]; | |
479 | u32 lurt; /* UPM Refresh Timer */ | |
480 | u32 lsrt; /* SDRAM Refresh Timer */ | |
481 | u8 res5[0x8]; | |
482 | u32 ltesr; /* Transfer Error Status Register */ | |
483 | u32 ltedr; /* Transfer Error Disable Register */ | |
484 | u32 lteir; /* Transfer Error Interrupt Register */ | |
485 | u32 lteatr; /* Transfer Error Attributes Register */ | |
486 | u32 ltear; /* Transfer Error Address Register */ | |
487 | u8 res6[0xC]; | |
488 | u32 lbcr; /* Configuration Register */ | |
489 | u32 lcrr; /* Clock Ratio Register */ | |
490 | u8 res7[0x8]; | |
491 | u32 fmr; /* Flash Mode Register */ | |
492 | u32 fir; /* Flash Instruction Register */ | |
493 | u32 fcr; /* Flash Command Register */ | |
494 | u32 fbar; /* Flash Block Addr Register */ | |
495 | u32 fpar; /* Flash Page Addr Register */ | |
496 | u32 fbcr; /* Flash Byte Count Register */ | |
497 | u8 res8[0xF08]; | |
498 | } fsl_lbus_t; | |
499 | #endif /* __ASSEMBLY__ */ | |
500 | ||
42dbd667 | 501 | #endif /* __ASM_PPC_FSL_LBC_H */ |