[people/ms/u-boot.git] / arch / powerpc / include / asm / fsl_pci.h

/*
 * Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 */

#ifndef __FSL_PCI_H_
#define __FSL_PCI_H_

#include <asm/fsl_law.h>

int fsl_setup_hose(struct pci_controller *hose, unsigned long addr);
int fsl_is_pci_agent(struct pci_controller *hose);
void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data);
void fsl_pci_config_unlock(struct pci_controller *hose);
void ft_fsl_pci_setup(void *blob, const char *pci_compat,
			struct pci_controller *hose, unsigned long ctrl_addr);

/*
 * Common PCI/PCIE Register structure for mpc85xx and mpc86xx
 */

/*
 * PCI Translation Registers
 */
typedef struct pci_outbound_window {
	u32	potar;		/* 0x00 - Address */
	u32	potear;		/* 0x04 - Address Extended */
	u32	powbar;		/* 0x08 - Window Base Address */
	u32	res1;
	u32	powar;		/* 0x10 - Window Attributes */
#define POWAR_EN	0x80000000
#define POWAR_IO_READ	0x00080000
#define POWAR_MEM_READ	0x00040000
#define POWAR_IO_WRITE	0x00008000
#define POWAR_MEM_WRITE	0x00004000
	u32	res2[3];
} pot_t;

typedef struct pci_inbound_window {
	u32	pitar;		/* 0x00 - Address */
	u32	res1;
	u32	piwbar;		/* 0x08 - Window Base Address */
	u32	piwbear;	/* 0x0c - Window Base Address Extended */
	u32	piwar;		/* 0x10 - Window Attributes */
#define PIWAR_EN		0x80000000
#define PIWAR_PF		0x20000000
#define PIWAR_LOCAL		0x00f00000
#define PIWAR_READ_SNOOP	0x00050000
#define PIWAR_WRITE_SNOOP	0x00005000
	u32	res2[3];
} pit_t;

/* PCI/PCI Express Registers */
typedef struct ccsr_pci {
	u32	cfg_addr;	/* 0x000 - PCI Configuration Address Register */
	u32	cfg_data;	/* 0x004 - PCI Configuration Data Register */
	u32	int_ack;	/* 0x008 - PCI Interrupt Acknowledge Register */
	u32	out_comp_to;	/* 0x00C - PCI Outbound Completion Timeout Register */
	u32	out_conf_to;	/* 0x010 - PCI Configuration Timeout Register */
	u32	config;		/* 0x014 - PCIE CONFIG Register */
	char	res2[8];
	u32	pme_msg_det;	/* 0x020 - PCIE PME & message detect register */
	u32	pme_msg_dis;	/* 0x024 - PCIE PME & message disable register */
	u32	pme_msg_int_en;	/* 0x028 - PCIE PME & message interrupt enable register */
	u32	pm_command;	/* 0x02c - PCIE PM Command register */
	char	res4[3016];	/*     (- #xbf8	 #x30)3016 */
	u32	block_rev1;	/* 0xbf8 - PCIE Block Revision register 1 */
	u32	block_rev2;	/* 0xbfc - PCIE Block Revision register 2 */

	pot_t	pot[5];		/* 0xc00 - 0xc9f Outbound ATMU's 0, 1, 2, 3, and 4 */
	u32	res5[64];
	pit_t	pit[3];		/* 0xda0 - 0xdff Inbound ATMU's 3, 2, and 1 */
#define PIT3 0
#define PIT2 1
#define PIT1 2

#if 0
	u32	potar0;		/* 0xc00 - PCI Outbound Transaction Address Register 0 */
	u32	potear0;	/* 0xc04 - PCI Outbound Translation Extended Address Register 0 */
	char	res5[8];
	u32	powar0;		/* 0xc10 - PCI Outbound Window Attributes Register 0 */
	char	res6[12];
	u32	potar1;		/* 0xc20 - PCI Outbound Transaction Address Register 1 */
	u32	potear1;	/* 0xc24 - PCI Outbound Translation Extended Address Register 1 */
	u32	powbar1;	/* 0xc28 - PCI Outbound Window Base Address Register 1 */
	char	res7[4];
	u32	powar1;		/* 0xc30 - PCI Outbound Window Attributes Register 1 */
	char	res8[12];
	u32	potar2;		/* 0xc40 - PCI Outbound Transaction Address Register 2 */
	u32	potear2;	/* 0xc44 - PCI Outbound Translation Extended Address Register 2 */
	u32	powbar2;	/* 0xc48 - PCI Outbound Window Base Address Register 2 */
	char	res9[4];
	u32	powar2;		/* 0xc50 - PCI Outbound Window Attributes Register 2 */
	char	res10[12];
	u32	potar3;		/* 0xc60 - PCI Outbound Transaction Address Register 3 */
	u32	potear3;	/* 0xc64 - PCI Outbound Translation Extended Address Register 3 */
	u32	powbar3;	/* 0xc68 - PCI Outbound Window Base Address Register 3 */
	char	res11[4];
	u32	powar3;		/* 0xc70 - PCI Outbound Window Attributes Register 3 */
	char	res12[12];
	u32	potar4;		/* 0xc80 - PCI Outbound Transaction Address Register 4 */
	u32	potear4;	/* 0xc84 - PCI Outbound Translation Extended Address Register 4 */
	u32	powbar4;	/* 0xc88 - PCI Outbound Window Base Address Register 4 */
	char	res13[4];
	u32	powar4;		/* 0xc90 - PCI Outbound Window Attributes Register 4 */
	char	res14[268];
	u32	pitar3;		/* 0xda0 - PCI Inbound Translation Address Register 3 */
	char	res15[4];
	u32	piwbar3;	/* 0xda8 - PCI Inbound Window Base Address Register 3 */
	u32	piwbear3;	/* 0xdac - PCI Inbound Window Base Extended Address Register 3 */
	u32	piwar3;		/* 0xdb0 - PCI Inbound Window Attributes Register 3 */
	char	res16[12];
	u32	pitar2;		/* 0xdc0 - PCI Inbound Translation Address Register 2 */
	char	res17[4];
	u32	piwbar2;	/* 0xdc8 - PCI Inbound Window Base Address Register 2 */
	u32	piwbear2;	/* 0xdcc - PCI Inbound Window Base Extended Address Register 2 */
	u32	piwar2;		/* 0xdd0 - PCI Inbound Window Attributes Register 2 */
	char	res18[12];
	u32	pitar1;		/* 0xde0 - PCI Inbound Translation Address Register 1 */
	char	res19[4];
	u32	piwbar1;	/* 0xde8 - PCI Inbound Window Base Address Register 1 */
	char	res20[4];
	u32	piwar1;		/* 0xdf0 - PCI Inbound Window Attributes Register 1 */
	char	res21[12];
#endif
	u32	pedr;		/* 0xe00 - PCI Error Detect Register */
	u32	pecdr;		/* 0xe04 - PCI Error Capture Disable Register */
	u32	peer;		/* 0xe08 - PCI Error Interrupt Enable Register */
	u32	peattrcr;	/* 0xe0c - PCI Error Attributes Capture Register */
	u32	peaddrcr;	/* 0xe10 - PCI Error Address Capture Register */
/*	u32	perr_disr	 * 0xe10 - PCIE Erorr Disable Register */
	u32	peextaddrcr;	/* 0xe14 - PCI	Error Extended Address Capture Register */
	u32	pedlcr;		/* 0xe18 - PCI Error Data Low Capture Register */
	u32	pedhcr;		/* 0xe1c - PCI Error Error Data High Capture Register */
	u32	gas_timr;	/* 0xe20 - PCI Gasket Timer Register */
/*	u32	perr_cap_stat;	 * 0xe20 - PCIE Error Capture Status Register */
	char	res22[4];
	u32	perr_cap0;	/* 0xe28 - PCIE Error Capture Register 0 */
	u32	perr_cap1;	/* 0xe2c - PCIE Error Capture Register 1 */
	u32	perr_cap2;	/* 0xe30 - PCIE Error Capture Register 2 */
	u32	perr_cap3;	/* 0xe34 - PCIE Error Capture Register 3 */
	char	res23[200];
	u32	pdb_stat;	/* 0xf00 - PCIE Debug Status */
	char	res24[252];
} ccsr_fsl_pci_t;

struct fsl_pci_info {
	unsigned long regs;
	pci_addr_t mem_bus;
	phys_size_t mem_phys;
	pci_size_t mem_size;
	pci_addr_t io_bus;
	phys_size_t io_phys;
	pci_size_t io_size;
	enum law_trgt_if law;
	int pci_num;
};

int fsl_pci_init_port(struct fsl_pci_info *pci_info,
				struct pci_controller *hose, int busno);

#define SET_STD_PCI_INFO(x, num) \
{			\
	x.regs = CONFIG_SYS_PCI##num##_ADDR;	\
	x.mem_bus = CONFIG_SYS_PCI##num##_MEM_BUS; \
	x.mem_phys = CONFIG_SYS_PCI##num##_MEM_PHYS; \
	x.mem_size = CONFIG_SYS_PCI##num##_MEM_SIZE; \
	x.io_bus = CONFIG_SYS_PCI##num##_IO_BUS; \
	x.io_phys = CONFIG_SYS_PCI##num##_IO_PHYS; \
	x.io_size = CONFIG_SYS_PCI##num##_IO_SIZE; \
	x.law = LAW_TRGT_IF_PCI_##num; \
	x.pci_num = num; \
}

#define SET_STD_PCIE_INFO(x, num) \
{			\
	x.regs = CONFIG_SYS_PCIE##num##_ADDR;	\
	x.mem_bus = CONFIG_SYS_PCIE##num##_MEM_BUS; \
	x.mem_phys = CONFIG_SYS_PCIE##num##_MEM_PHYS; \
	x.mem_size = CONFIG_SYS_PCIE##num##_MEM_SIZE; \
	x.io_bus = CONFIG_SYS_PCIE##num##_IO_BUS; \
	x.io_phys = CONFIG_SYS_PCIE##num##_IO_PHYS; \
	x.io_size = CONFIG_SYS_PCIE##num##_IO_SIZE; \
	x.law = LAW_TRGT_IF_PCIE_##num; \
	x.pci_num = num; \
}

#define __FT_FSL_PCI_SETUP(blob, compat, num) \
	ft_fsl_pci_setup(blob, compat, &pci##num##_hose, \
			 CONFIG_SYS_PCI##num##_ADDR)

#define __FT_FSL_PCI_DEL(blob, compat, num) \
	ft_fsl_pci_setup(blob, compat, NULL, CONFIG_SYS_PCI##num##_ADDR)

#define __FT_FSL_PCIE_SETUP(blob, compat, num) \
	ft_fsl_pci_setup(blob, compat, &pcie##num##_hose, \
			 CONFIG_SYS_PCIE##num##_ADDR)

#define __FT_FSL_PCIE_DEL(blob, compat, num) \
	ft_fsl_pci_setup(blob, compat, NULL, CONFIG_SYS_PCIE##num##_ADDR)

#ifdef CONFIG_PCI1
#define FT_FSL_PCI1_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 1)
#else
#define FT_FSL_PCI1_SETUP __FT_FSL_PCI_DEL(blob, FSL_PCI_COMPAT, 1)
#endif

#ifdef CONFIG_PCI2
#define FT_FSL_PCI2_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 2)
#else
#define FT_FSL_PCI2_SETUP __FT_FSL_PCI_DEL(blob, FSL_PCI_COMPAT, 2)
#endif

#ifdef CONFIG_PCIE1
#define FT_FSL_PCIE1_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 1)
#else
#define FT_FSL_PCIE1_SETUP __FT_FSL_PCIE_DEL(blob, FSL_PCIE_COMPAT, 1)
#endif

#ifdef CONFIG_PCIE2
#define FT_FSL_PCIE2_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 2)
#else
#define FT_FSL_PCIE2_SETUP __FT_FSL_PCIE_DEL(blob, FSL_PCIE_COMPAT, 2)
#endif

#ifdef CONFIG_PCIE3
#define FT_FSL_PCIE3_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 3)
#else
#define FT_FSL_PCIE3_SETUP __FT_FSL_PCIE_DEL(blob, FSL_PCIE_COMPAT, 3)
#endif

#ifdef CONFIG_PCIE4
#define FT_FSL_PCIE4_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 4)
#else
#define FT_FSL_PCIE4_SETUP __FT_FSL_PCIE_DEL(blob, FSL_PCIE_COMPAT, 4)
#endif

#if defined(CONFIG_FSL_CORENET)
#define FSL_PCIE_COMPAT	"fsl,p4080-pcie"
#define FT_FSL_PCI_SETUP \
	FT_FSL_PCIE1_SETUP; \
	FT_FSL_PCIE2_SETUP; \
	FT_FSL_PCIE3_SETUP; \
	FT_FSL_PCIE4_SETUP;
#elif defined(CONFIG_MPC85xx)
#define FSL_PCI_COMPAT	"fsl,mpc8540-pci"
#define FSL_PCIE_COMPAT	"fsl,mpc8548-pcie"
#define FT_FSL_PCI_SETUP \
	FT_FSL_PCI1_SETUP; \
	FT_FSL_PCI2_SETUP; \
	FT_FSL_PCIE1_SETUP; \
	FT_FSL_PCIE2_SETUP; \
	FT_FSL_PCIE3_SETUP;
#elif defined(CONFIG_MPC86xx)
#define FSL_PCI_COMPAT	"fsl,mpc8610-pci"
#define FSL_PCIE_COMPAT	"fsl,mpc8641-pcie"
#define FT_FSL_PCI_SETUP \
	FT_FSL_PCI1_SETUP; \
	FT_FSL_PCIE1_SETUP; \
	FT_FSL_PCIE2_SETUP;
#else
#error FT_FSL_PCI_SETUP not defined
#endif


#endif
Commit	Line	Data
ee53650d	1	/*
6525d51f	2	* Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
63cec581 ES	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License as
	6	* published by the Free Software Foundation; either version 2 of
	7	* the License, or (at your option) any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	17	* MA 02111-1307 USA
	18	*
	19	*/
	20
32049b40 KG	21	#ifndef __FSL_PCI_H_
	22	#define __FSL_PCI_H_
	23
3e7b6c1f KG	24	#include <asm/fsl_law.h>
3e7b6c1f KG	25
ee53650d	26	int fsl_setup_hose(struct pci_controller *hose, unsigned long addr);
715d8f76	27	int fsl_is_pci_agent(struct pci_controller *hose);
fb3143b3	28	void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data);
32049b40	29	void fsl_pci_config_unlock(struct pci_controller *hose);
6525d51f KG	30	void ft_fsl_pci_setup(void blob, const char pci_compat,
6525d51f KG	31	struct pci_controller *hose, unsigned long ctrl_addr);
63cec581 ES	32
	33	/*
	34	* Common PCI/PCIE Register structure for mpc85xx and mpc86xx
	35	*/
	36
	37	/*
	38	* PCI Translation Registers
	39	*/
	40	typedef struct pci_outbound_window {
	41	u32 potar; /* 0x00 - Address */
	42	u32 potear; /* 0x04 - Address Extended */
	43	u32 powbar; /* 0x08 - Window Base Address */
	44	u32 res1;
	45	u32 powar; /* 0x10 - Window Attributes */
	46	#define POWAR_EN 0x80000000
	47	#define POWAR_IO_READ 0x00080000
	48	#define POWAR_MEM_READ 0x00040000
	49	#define POWAR_IO_WRITE 0x00008000
	50	#define POWAR_MEM_WRITE 0x00004000
	51	u32 res2[3];
	52	} pot_t;
	53
	54	typedef struct pci_inbound_window {
	55	u32 pitar; /* 0x00 - Address */
	56	u32 res1;
	57	u32 piwbar; /* 0x08 - Window Base Address */
	58	u32 piwbear; /* 0x0c - Window Base Address Extended */
	59	u32 piwar; /* 0x10 - Window Attributes */
	60	#define PIWAR_EN 0x80000000
	61	#define PIWAR_PF 0x20000000
	62	#define PIWAR_LOCAL 0x00f00000
	63	#define PIWAR_READ_SNOOP 0x00050000
	64	#define PIWAR_WRITE_SNOOP 0x00005000
	65	u32 res2[3];
	66	} pit_t;
	67
	68	/* PCI/PCI Express Registers */
	69	typedef struct ccsr_pci {
	70	u32 cfg_addr; /* 0x000 - PCI Configuration Address Register */
	71	u32 cfg_data; /* 0x004 - PCI Configuration Data Register */
	72	u32 int_ack; /* 0x008 - PCI Interrupt Acknowledge Register */
	73	u32 out_comp_to; /* 0x00C - PCI Outbound Completion Timeout Register */
	74	u32 out_conf_to; /* 0x010 - PCI Configuration Timeout Register */
	75	u32 config; /* 0x014 - PCIE CONFIG Register */
	76	char res2[8];
	77	u32 pme_msg_det; /* 0x020 - PCIE PME & message detect register */
	78	u32 pme_msg_dis; /* 0x024 - PCIE PME & message disable register */
	79	u32 pme_msg_int_en; /* 0x028 - PCIE PME & message interrupt enable register */
	80	u32 pm_command; /* 0x02c - PCIE PM Command register */
	81	char res4[3016]; /* (- #xbf8 #x30)3016 */
	82	u32 block_rev1; /* 0xbf8 - PCIE Block Revision register 1 */
	83	u32 block_rev2; /* 0xbfc - PCIE Block Revision register 2 */
	84
	85	pot_t pot[5]; /* 0xc00 - 0xc9f Outbound ATMU's 0, 1, 2, 3, and 4 */
	86	u32 res5[64];
	87	pit_t pit[3]; /* 0xda0 - 0xdff Inbound ATMU's 3, 2, and 1 */
	88	#define PIT3 0
	89	#define PIT2 1
	90	#define PIT1 2
	91
	92	#if 0
	93	u32 potar0; /* 0xc00 - PCI Outbound Transaction Address Register 0 */
	94	u32 potear0; /* 0xc04 - PCI Outbound Translation Extended Address Register 0 */
	95	char res5[8];
96	u32 powar0; /* 0xc10 - PCI Outbound Window Attributes Register 0 */
97	char res6[12];
98	u32 potar1; /* 0xc20 - PCI Outbound Transaction Address Register 1 */
99	u32 potear1; /* 0xc24 - PCI Outbound Translation Extended Address Register 1 */
100	u32 powbar1; /* 0xc28 - PCI Outbound Window Base Address Register 1 */
101	char res7[4];
102	u32 powar1; /* 0xc30 - PCI Outbound Window Attributes Register 1 */
103	char res8[12];
104	u32 potar2; /* 0xc40 - PCI Outbound Transaction Address Register 2 */
105	u32 potear2; /* 0xc44 - PCI Outbound Translation Extended Address Register 2 */
106	u32 powbar2; /* 0xc48 - PCI Outbound Window Base Address Register 2 */
107	char res9[4];
108	u32 powar2; /* 0xc50 - PCI Outbound Window Attributes Register 2 */
109	char res10[12];
110	u32 potar3; /* 0xc60 - PCI Outbound Transaction Address Register 3 */
111	u32 potear3; /* 0xc64 - PCI Outbound Translation Extended Address Register 3 */
112	u32 powbar3; /* 0xc68 - PCI Outbound Window Base Address Register 3 */
113	char res11[4];
114	u32 powar3; /* 0xc70 - PCI Outbound Window Attributes Register 3 */
115	char res12[12];
116	u32 potar4; /* 0xc80 - PCI Outbound Transaction Address Register 4 */
117	u32 potear4; /* 0xc84 - PCI Outbound Translation Extended Address Register 4 */
118	u32 powbar4; /* 0xc88 - PCI Outbound Window Base Address Register 4 */
119	char res13[4];
120	u32 powar4; /* 0xc90 - PCI Outbound Window Attributes Register 4 */
121	char res14[268];
122	u32 pitar3; /* 0xda0 - PCI Inbound Translation Address Register 3 */
123	char res15[4];
124	u32 piwbar3; /* 0xda8 - PCI Inbound Window Base Address Register 3 */
125	u32 piwbear3; /* 0xdac - PCI Inbound Window Base Extended Address Register 3 */
126	u32 piwar3; /* 0xdb0 - PCI Inbound Window Attributes Register 3 */
127	char res16[12];
128	u32 pitar2; /* 0xdc0 - PCI Inbound Translation Address Register 2 */
129	char res17[4];
130	u32 piwbar2; /* 0xdc8 - PCI Inbound Window Base Address Register 2 */
131	u32 piwbear2; /* 0xdcc - PCI Inbound Window Base Extended Address Register 2 */
132	u32 piwar2; /* 0xdd0 - PCI Inbound Window Attributes Register 2 */
133	char res18[12];
134	u32 pitar1; /* 0xde0 - PCI Inbound Translation Address Register 1 */
135	char res19[4];
136	u32 piwbar1; /* 0xde8 - PCI Inbound Window Base Address Register 1 */
137	char res20[4];
138	u32 piwar1; /* 0xdf0 - PCI Inbound Window Attributes Register 1 */
139	char res21[12];
140	#endif
141	u32 pedr; /* 0xe00 - PCI Error Detect Register */
142	u32 pecdr; /* 0xe04 - PCI Error Capture Disable Register */
143	u32 peer; /* 0xe08 - PCI Error Interrupt Enable Register */
144	u32 peattrcr; /* 0xe0c - PCI Error Attributes Capture Register */
145	u32 peaddrcr; /* 0xe10 - PCI Error Address Capture Register */
146	/* u32 perr_disr * 0xe10 - PCIE Erorr Disable Register */
147	u32 peextaddrcr; /* 0xe14 - PCI Error Extended Address Capture Register */
148	u32 pedlcr; /* 0xe18 - PCI Error Data Low Capture Register */
149	u32 pedhcr; /* 0xe1c - PCI Error Error Data High Capture Register */
150	u32 gas_timr; /* 0xe20 - PCI Gasket Timer Register */
151	/* u32 perr_cap_stat; * 0xe20 - PCIE Error Capture Status Register */
152	char res22[4];
153	u32 perr_cap0; /* 0xe28 - PCIE Error Capture Register 0 */
154	u32 perr_cap1; /* 0xe2c - PCIE Error Capture Register 1 */
155	u32 perr_cap2; /* 0xe30 - PCIE Error Capture Register 2 */
156	u32 perr_cap3; /* 0xe34 - PCIE Error Capture Register 3 */
8ff3de61 KG	157	char res23[200];
	158	u32 pdb_stat; /* 0xf00 - PCIE Debug Status */
	159	char res24[252];
63cec581 ES	160	} ccsr_fsl_pci_t;
63cec581 ES	161
0d3d68b2	162	struct fsl_pci_info {
752bc335 TT	163	unsigned long regs;
	164	pci_addr_t mem_bus;
	165	phys_size_t mem_phys;
	166	pci_size_t mem_size;
	167	pci_addr_t io_bus;
	168	phys_size_t io_phys;
	169	pci_size_t io_size;
	170	enum law_trgt_if law;
	171	int pci_num;
0d3d68b2 PA	172	};
	173
	174	int fsl_pci_init_port(struct fsl_pci_info *pci_info,
01471d53	175	struct pci_controller *hose, int busno);
0d3d68b2	176
a8b3e90f PG	177	#define SET_STD_PCI_INFO(x, num) \
	178	{ \
	179	x.regs = CONFIG_SYS_PCI##num##_ADDR; \
	180	x.mem_bus = CONFIG_SYS_PCI##num##_MEM_BUS; \
	181	x.mem_phys = CONFIG_SYS_PCI##num##_MEM_PHYS; \
	182	x.mem_size = CONFIG_SYS_PCI##num##_MEM_SIZE; \
	183	x.io_bus = CONFIG_SYS_PCI##num##_IO_BUS; \
	184	x.io_phys = CONFIG_SYS_PCI##num##_IO_PHYS; \
	185	x.io_size = CONFIG_SYS_PCI##num##_IO_SIZE; \
752bc335	186	x.law = LAW_TRGT_IF_PCI_##num; \
a8b3e90f PG	187	x.pci_num = num; \
	188	}
	189
0d3d68b2 PA	190	#define SET_STD_PCIE_INFO(x, num) \
	191	{ \
	192	x.regs = CONFIG_SYS_PCIE##num##_ADDR; \
	193	x.mem_bus = CONFIG_SYS_PCIE##num##_MEM_BUS; \
	194	x.mem_phys = CONFIG_SYS_PCIE##num##_MEM_PHYS; \
	195	x.mem_size = CONFIG_SYS_PCIE##num##_MEM_SIZE; \
	196	x.io_bus = CONFIG_SYS_PCIE##num##_IO_BUS; \
	197	x.io_phys = CONFIG_SYS_PCIE##num##_IO_PHYS; \
	198	x.io_size = CONFIG_SYS_PCIE##num##_IO_SIZE; \
752bc335	199	x.law = LAW_TRGT_IF_PCIE_##num; \
0d3d68b2 PA	200	x.pci_num = num; \
	201	}
	202
6525d51f KG	203	#define __FT_FSL_PCI_SETUP(blob, compat, num) \
	204	ft_fsl_pci_setup(blob, compat, &pci##num##_hose, \
	205	CONFIG_SYS_PCI##num##_ADDR)
	206
	207	#define __FT_FSL_PCI_DEL(blob, compat, num) \
	208	ft_fsl_pci_setup(blob, compat, NULL, CONFIG_SYS_PCI##num##_ADDR)
	209
	210	#define __FT_FSL_PCIE_SETUP(blob, compat, num) \
	211	ft_fsl_pci_setup(blob, compat, &pcie##num##_hose, \
	212	CONFIG_SYS_PCIE##num##_ADDR)
	213
	214	#define __FT_FSL_PCIE_DEL(blob, compat, num) \
	215	ft_fsl_pci_setup(blob, compat, NULL, CONFIG_SYS_PCIE##num##_ADDR)
	216
	217	#ifdef CONFIG_PCI1
	218	#define FT_FSL_PCI1_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 1)
	219	#else
	220	#define FT_FSL_PCI1_SETUP __FT_FSL_PCI_DEL(blob, FSL_PCI_COMPAT, 1)
	221	#endif
	222
	223	#ifdef CONFIG_PCI2
	224	#define FT_FSL_PCI2_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 2)
	225	#else
	226	#define FT_FSL_PCI2_SETUP __FT_FSL_PCI_DEL(blob, FSL_PCI_COMPAT, 2)
	227	#endif
	228
	229	#ifdef CONFIG_PCIE1
	230	#define FT_FSL_PCIE1_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 1)
	231	#else
	232	#define FT_FSL_PCIE1_SETUP __FT_FSL_PCIE_DEL(blob, FSL_PCIE_COMPAT, 1)
	233	#endif
	234
	235	#ifdef CONFIG_PCIE2
	236	#define FT_FSL_PCIE2_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 2)
	237	#else
	238	#define FT_FSL_PCIE2_SETUP __FT_FSL_PCIE_DEL(blob, FSL_PCIE_COMPAT, 2)
	239	#endif
	240
	241	#ifdef CONFIG_PCIE3
	242	#define FT_FSL_PCIE3_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 3)
	243	#else
	244	#define FT_FSL_PCIE3_SETUP __FT_FSL_PCIE_DEL(blob, FSL_PCIE_COMPAT, 3)
	245	#endif
	246
	247	#ifdef CONFIG_PCIE4
	248	#define FT_FSL_PCIE4_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 4)
	249	#else
	250	#define FT_FSL_PCIE4_SETUP __FT_FSL_PCIE_DEL(blob, FSL_PCIE_COMPAT, 4)
	251	#endif
	252
	253	#if defined(CONFIG_FSL_CORENET)
	254	#define FSL_PCIE_COMPAT "fsl,p4080-pcie"
	255	#define FT_FSL_PCI_SETUP \
	256	FT_FSL_PCIE1_SETUP; \
	257	FT_FSL_PCIE2_SETUP; \
	258	FT_FSL_PCIE3_SETUP; \
	259	FT_FSL_PCIE4_SETUP;
	260	#elif defined(CONFIG_MPC85xx)
	261	#define FSL_PCI_COMPAT "fsl,mpc8540-pci"
	262	#define FSL_PCIE_COMPAT "fsl,mpc8548-pcie"
	263	#define FT_FSL_PCI_SETUP \
	264	FT_FSL_PCI1_SETUP; \
	265	FT_FSL_PCI2_SETUP; \
	266	FT_FSL_PCIE1_SETUP; \
267	FT_FSL_PCIE2_SETUP; \
268	FT_FSL_PCIE3_SETUP;
269	#elif defined(CONFIG_MPC86xx)
270	#define FSL_PCI_COMPAT "fsl,mpc8610-pci"
271	#define FSL_PCIE_COMPAT "fsl,mpc8641-pcie"
272	#define FT_FSL_PCI_SETUP \
273	FT_FSL_PCI1_SETUP; \
274	FT_FSL_PCIE1_SETUP; \
275	FT_FSL_PCIE2_SETUP;
276	#else
277	#error FT_FSL_PCI_SETUP not defined
278	#endif
279
280
32049b40	281	#endif