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ee53650d | 1 | /* |
6525d51f | 2 | * Copyright 2007,2009-2010 Freescale Semiconductor, Inc. |
63cec581 ES |
3 | * |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License as | |
6 | * published by the Free Software Foundation; either version 2 of | |
7 | * the License, or (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
17 | * MA 02111-1307 USA | |
18 | * | |
19 | */ | |
20 | ||
32049b40 KG |
21 | #ifndef __FSL_PCI_H_ |
22 | #define __FSL_PCI_H_ | |
23 | ||
3e7b6c1f | 24 | #include <asm/fsl_law.h> |
a4aafcc9 KG |
25 | #include <asm/fsl_serdes.h> |
26 | #include <pci.h> | |
3e7b6c1f | 27 | |
ee53650d | 28 | int fsl_setup_hose(struct pci_controller *hose, unsigned long addr); |
715d8f76 | 29 | int fsl_is_pci_agent(struct pci_controller *hose); |
fb3143b3 | 30 | void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data); |
32049b40 | 31 | void fsl_pci_config_unlock(struct pci_controller *hose); |
3a0e3c27 | 32 | void ft_fsl_pci_setup(void *blob, const char *compat, unsigned long ctrl_addr); |
63cec581 ES |
33 | |
34 | /* | |
35 | * Common PCI/PCIE Register structure for mpc85xx and mpc86xx | |
36 | */ | |
37 | ||
38 | /* | |
39 | * PCI Translation Registers | |
40 | */ | |
41 | typedef struct pci_outbound_window { | |
42 | u32 potar; /* 0x00 - Address */ | |
43 | u32 potear; /* 0x04 - Address Extended */ | |
44 | u32 powbar; /* 0x08 - Window Base Address */ | |
45 | u32 res1; | |
46 | u32 powar; /* 0x10 - Window Attributes */ | |
47 | #define POWAR_EN 0x80000000 | |
48 | #define POWAR_IO_READ 0x00080000 | |
49 | #define POWAR_MEM_READ 0x00040000 | |
50 | #define POWAR_IO_WRITE 0x00008000 | |
51 | #define POWAR_MEM_WRITE 0x00004000 | |
52 | u32 res2[3]; | |
53 | } pot_t; | |
54 | ||
55 | typedef struct pci_inbound_window { | |
56 | u32 pitar; /* 0x00 - Address */ | |
57 | u32 res1; | |
58 | u32 piwbar; /* 0x08 - Window Base Address */ | |
59 | u32 piwbear; /* 0x0c - Window Base Address Extended */ | |
60 | u32 piwar; /* 0x10 - Window Attributes */ | |
61 | #define PIWAR_EN 0x80000000 | |
62 | #define PIWAR_PF 0x20000000 | |
63 | #define PIWAR_LOCAL 0x00f00000 | |
64 | #define PIWAR_READ_SNOOP 0x00050000 | |
65 | #define PIWAR_WRITE_SNOOP 0x00005000 | |
66 | u32 res2[3]; | |
67 | } pit_t; | |
68 | ||
69 | /* PCI/PCI Express Registers */ | |
70 | typedef struct ccsr_pci { | |
71 | u32 cfg_addr; /* 0x000 - PCI Configuration Address Register */ | |
72 | u32 cfg_data; /* 0x004 - PCI Configuration Data Register */ | |
73 | u32 int_ack; /* 0x008 - PCI Interrupt Acknowledge Register */ | |
74 | u32 out_comp_to; /* 0x00C - PCI Outbound Completion Timeout Register */ | |
75 | u32 out_conf_to; /* 0x010 - PCI Configuration Timeout Register */ | |
76 | u32 config; /* 0x014 - PCIE CONFIG Register */ | |
77 | char res2[8]; | |
78 | u32 pme_msg_det; /* 0x020 - PCIE PME & message detect register */ | |
79 | u32 pme_msg_dis; /* 0x024 - PCIE PME & message disable register */ | |
80 | u32 pme_msg_int_en; /* 0x028 - PCIE PME & message interrupt enable register */ | |
81 | u32 pm_command; /* 0x02c - PCIE PM Command register */ | |
82 | char res4[3016]; /* (- #xbf8 #x30)3016 */ | |
83 | u32 block_rev1; /* 0xbf8 - PCIE Block Revision register 1 */ | |
84 | u32 block_rev2; /* 0xbfc - PCIE Block Revision register 2 */ | |
85 | ||
86 | pot_t pot[5]; /* 0xc00 - 0xc9f Outbound ATMU's 0, 1, 2, 3, and 4 */ | |
87 | u32 res5[64]; | |
88 | pit_t pit[3]; /* 0xda0 - 0xdff Inbound ATMU's 3, 2, and 1 */ | |
89 | #define PIT3 0 | |
90 | #define PIT2 1 | |
91 | #define PIT1 2 | |
92 | ||
93 | #if 0 | |
94 | u32 potar0; /* 0xc00 - PCI Outbound Transaction Address Register 0 */ | |
95 | u32 potear0; /* 0xc04 - PCI Outbound Translation Extended Address Register 0 */ | |
96 | char res5[8]; | |
97 | u32 powar0; /* 0xc10 - PCI Outbound Window Attributes Register 0 */ | |
98 | char res6[12]; | |
99 | u32 potar1; /* 0xc20 - PCI Outbound Transaction Address Register 1 */ | |
100 | u32 potear1; /* 0xc24 - PCI Outbound Translation Extended Address Register 1 */ | |
101 | u32 powbar1; /* 0xc28 - PCI Outbound Window Base Address Register 1 */ | |
102 | char res7[4]; | |
103 | u32 powar1; /* 0xc30 - PCI Outbound Window Attributes Register 1 */ | |
104 | char res8[12]; | |
105 | u32 potar2; /* 0xc40 - PCI Outbound Transaction Address Register 2 */ | |
106 | u32 potear2; /* 0xc44 - PCI Outbound Translation Extended Address Register 2 */ | |
107 | u32 powbar2; /* 0xc48 - PCI Outbound Window Base Address Register 2 */ | |
108 | char res9[4]; | |
109 | u32 powar2; /* 0xc50 - PCI Outbound Window Attributes Register 2 */ | |
110 | char res10[12]; | |
111 | u32 potar3; /* 0xc60 - PCI Outbound Transaction Address Register 3 */ | |
112 | u32 potear3; /* 0xc64 - PCI Outbound Translation Extended Address Register 3 */ | |
113 | u32 powbar3; /* 0xc68 - PCI Outbound Window Base Address Register 3 */ | |
114 | char res11[4]; | |
115 | u32 powar3; /* 0xc70 - PCI Outbound Window Attributes Register 3 */ | |
116 | char res12[12]; | |
117 | u32 potar4; /* 0xc80 - PCI Outbound Transaction Address Register 4 */ | |
118 | u32 potear4; /* 0xc84 - PCI Outbound Translation Extended Address Register 4 */ | |
119 | u32 powbar4; /* 0xc88 - PCI Outbound Window Base Address Register 4 */ | |
120 | char res13[4]; | |
121 | u32 powar4; /* 0xc90 - PCI Outbound Window Attributes Register 4 */ | |
122 | char res14[268]; | |
123 | u32 pitar3; /* 0xda0 - PCI Inbound Translation Address Register 3 */ | |
124 | char res15[4]; | |
125 | u32 piwbar3; /* 0xda8 - PCI Inbound Window Base Address Register 3 */ | |
126 | u32 piwbear3; /* 0xdac - PCI Inbound Window Base Extended Address Register 3 */ | |
127 | u32 piwar3; /* 0xdb0 - PCI Inbound Window Attributes Register 3 */ | |
128 | char res16[12]; | |
129 | u32 pitar2; /* 0xdc0 - PCI Inbound Translation Address Register 2 */ | |
130 | char res17[4]; | |
131 | u32 piwbar2; /* 0xdc8 - PCI Inbound Window Base Address Register 2 */ | |
132 | u32 piwbear2; /* 0xdcc - PCI Inbound Window Base Extended Address Register 2 */ | |
133 | u32 piwar2; /* 0xdd0 - PCI Inbound Window Attributes Register 2 */ | |
134 | char res18[12]; | |
135 | u32 pitar1; /* 0xde0 - PCI Inbound Translation Address Register 1 */ | |
136 | char res19[4]; | |
137 | u32 piwbar1; /* 0xde8 - PCI Inbound Window Base Address Register 1 */ | |
138 | char res20[4]; | |
139 | u32 piwar1; /* 0xdf0 - PCI Inbound Window Attributes Register 1 */ | |
140 | char res21[12]; | |
141 | #endif | |
142 | u32 pedr; /* 0xe00 - PCI Error Detect Register */ | |
143 | u32 pecdr; /* 0xe04 - PCI Error Capture Disable Register */ | |
144 | u32 peer; /* 0xe08 - PCI Error Interrupt Enable Register */ | |
145 | u32 peattrcr; /* 0xe0c - PCI Error Attributes Capture Register */ | |
146 | u32 peaddrcr; /* 0xe10 - PCI Error Address Capture Register */ | |
147 | /* u32 perr_disr * 0xe10 - PCIE Erorr Disable Register */ | |
148 | u32 peextaddrcr; /* 0xe14 - PCI Error Extended Address Capture Register */ | |
149 | u32 pedlcr; /* 0xe18 - PCI Error Data Low Capture Register */ | |
150 | u32 pedhcr; /* 0xe1c - PCI Error Error Data High Capture Register */ | |
151 | u32 gas_timr; /* 0xe20 - PCI Gasket Timer Register */ | |
152 | /* u32 perr_cap_stat; * 0xe20 - PCIE Error Capture Status Register */ | |
153 | char res22[4]; | |
154 | u32 perr_cap0; /* 0xe28 - PCIE Error Capture Register 0 */ | |
155 | u32 perr_cap1; /* 0xe2c - PCIE Error Capture Register 1 */ | |
156 | u32 perr_cap2; /* 0xe30 - PCIE Error Capture Register 2 */ | |
157 | u32 perr_cap3; /* 0xe34 - PCIE Error Capture Register 3 */ | |
8ff3de61 KG |
158 | char res23[200]; |
159 | u32 pdb_stat; /* 0xf00 - PCIE Debug Status */ | |
160 | char res24[252]; | |
63cec581 ES |
161 | } ccsr_fsl_pci_t; |
162 | ||
0d3d68b2 | 163 | struct fsl_pci_info { |
752bc335 TT |
164 | unsigned long regs; |
165 | pci_addr_t mem_bus; | |
166 | phys_size_t mem_phys; | |
167 | pci_size_t mem_size; | |
168 | pci_addr_t io_bus; | |
169 | phys_size_t io_phys; | |
170 | pci_size_t io_size; | |
171 | enum law_trgt_if law; | |
172 | int pci_num; | |
0d3d68b2 PA |
173 | }; |
174 | ||
175 | int fsl_pci_init_port(struct fsl_pci_info *pci_info, | |
01471d53 | 176 | struct pci_controller *hose, int busno); |
a4aafcc9 KG |
177 | int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev, |
178 | struct fsl_pci_info *pci_info); | |
179 | int fsl_pcie_init_board(int busno); | |
0d3d68b2 | 180 | |
a8b3e90f PG |
181 | #define SET_STD_PCI_INFO(x, num) \ |
182 | { \ | |
183 | x.regs = CONFIG_SYS_PCI##num##_ADDR; \ | |
184 | x.mem_bus = CONFIG_SYS_PCI##num##_MEM_BUS; \ | |
185 | x.mem_phys = CONFIG_SYS_PCI##num##_MEM_PHYS; \ | |
186 | x.mem_size = CONFIG_SYS_PCI##num##_MEM_SIZE; \ | |
187 | x.io_bus = CONFIG_SYS_PCI##num##_IO_BUS; \ | |
188 | x.io_phys = CONFIG_SYS_PCI##num##_IO_PHYS; \ | |
189 | x.io_size = CONFIG_SYS_PCI##num##_IO_SIZE; \ | |
752bc335 | 190 | x.law = LAW_TRGT_IF_PCI_##num; \ |
a8b3e90f PG |
191 | x.pci_num = num; \ |
192 | } | |
193 | ||
0d3d68b2 PA |
194 | #define SET_STD_PCIE_INFO(x, num) \ |
195 | { \ | |
196 | x.regs = CONFIG_SYS_PCIE##num##_ADDR; \ | |
197 | x.mem_bus = CONFIG_SYS_PCIE##num##_MEM_BUS; \ | |
198 | x.mem_phys = CONFIG_SYS_PCIE##num##_MEM_PHYS; \ | |
199 | x.mem_size = CONFIG_SYS_PCIE##num##_MEM_SIZE; \ | |
200 | x.io_bus = CONFIG_SYS_PCIE##num##_IO_BUS; \ | |
201 | x.io_phys = CONFIG_SYS_PCIE##num##_IO_PHYS; \ | |
202 | x.io_size = CONFIG_SYS_PCIE##num##_IO_SIZE; \ | |
752bc335 | 203 | x.law = LAW_TRGT_IF_PCIE_##num; \ |
0d3d68b2 PA |
204 | x.pci_num = num; \ |
205 | } | |
206 | ||
6525d51f | 207 | #define __FT_FSL_PCI_SETUP(blob, compat, num) \ |
3a0e3c27 | 208 | ft_fsl_pci_setup(blob, compat, CONFIG_SYS_PCI##num##_ADDR) |
6525d51f KG |
209 | |
210 | #define __FT_FSL_PCIE_SETUP(blob, compat, num) \ | |
3a0e3c27 | 211 | ft_fsl_pci_setup(blob, compat, CONFIG_SYS_PCIE##num##_ADDR) |
6525d51f | 212 | |
6525d51f | 213 | #define FT_FSL_PCI1_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 1) |
6525d51f | 214 | #define FT_FSL_PCI2_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 2) |
6525d51f | 215 | |
6525d51f | 216 | #define FT_FSL_PCIE1_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 1) |
6525d51f | 217 | #define FT_FSL_PCIE2_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 2) |
6525d51f | 218 | #define FT_FSL_PCIE3_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 3) |
6525d51f | 219 | #define FT_FSL_PCIE4_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 4) |
6525d51f KG |
220 | |
221 | #if defined(CONFIG_FSL_CORENET) | |
222 | #define FSL_PCIE_COMPAT "fsl,p4080-pcie" | |
223 | #define FT_FSL_PCI_SETUP \ | |
224 | FT_FSL_PCIE1_SETUP; \ | |
225 | FT_FSL_PCIE2_SETUP; \ | |
226 | FT_FSL_PCIE3_SETUP; \ | |
227 | FT_FSL_PCIE4_SETUP; | |
a4aafcc9 | 228 | #define FT_FSL_PCIE_SETUP FT_FSL_PCI_SETUP |
6525d51f KG |
229 | #elif defined(CONFIG_MPC85xx) |
230 | #define FSL_PCI_COMPAT "fsl,mpc8540-pci" | |
231 | #define FSL_PCIE_COMPAT "fsl,mpc8548-pcie" | |
232 | #define FT_FSL_PCI_SETUP \ | |
233 | FT_FSL_PCI1_SETUP; \ | |
234 | FT_FSL_PCI2_SETUP; \ | |
235 | FT_FSL_PCIE1_SETUP; \ | |
236 | FT_FSL_PCIE2_SETUP; \ | |
237 | FT_FSL_PCIE3_SETUP; | |
a4aafcc9 KG |
238 | #define FT_FSL_PCIE_SETUP \ |
239 | FT_FSL_PCIE1_SETUP; \ | |
240 | FT_FSL_PCIE2_SETUP; \ | |
241 | FT_FSL_PCIE3_SETUP; | |
6525d51f KG |
242 | #elif defined(CONFIG_MPC86xx) |
243 | #define FSL_PCI_COMPAT "fsl,mpc8610-pci" | |
244 | #define FSL_PCIE_COMPAT "fsl,mpc8641-pcie" | |
245 | #define FT_FSL_PCI_SETUP \ | |
246 | FT_FSL_PCI1_SETUP; \ | |
247 | FT_FSL_PCIE1_SETUP; \ | |
248 | FT_FSL_PCIE2_SETUP; | |
249 | #else | |
250 | #error FT_FSL_PCI_SETUP not defined | |
251 | #endif | |
252 | ||
253 | ||
32049b40 | 254 | #endif |