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42d1f039 WD |
1 | /* |
2 | * MPC85xx Internal Memory Map | |
3 | * | |
a07bf180 | 4 | * Copyright 2007-2009 Freescale Semiconductor, Inc. |
837f1ba0 | 5 | * |
42d1f039 WD |
6 | * Copyright(c) 2002,2003 Motorola Inc. |
7 | * Xianghua Xiao (x.xiao@motorola.com) | |
8 | * | |
11588b5d KG |
9 | * See file CREDITS for list of people who contributed to this |
10 | * project. | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License as | |
14 | * published by the Free Software Foundation; either version 2 of | |
15 | * the License, or (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
25 | * MA 02111-1307 USA | |
42d1f039 WD |
26 | */ |
27 | ||
28 | #ifndef __IMMAP_85xx__ | |
29 | #define __IMMAP_85xx__ | |
30 | ||
3dfa9cfd | 31 | #include <asm/types.h> |
b1f12650 | 32 | #include <asm/fsl_dma.h> |
3dfa9cfd | 33 | #include <asm/fsl_i2c.h> |
4e190b03 | 34 | #include <asm/fsl_lbc.h> |
3dfa9cfd | 35 | |
01df5212 | 36 | typedef struct ccsr_local { |
8280912e KG |
37 | u32 ccsrbarh; /* CCSR Base Addr High */ |
38 | u32 ccsrbarl; /* CCSR Base Addr Low */ | |
39 | u32 ccsrar; /* CCSR Attr */ | |
01df5212 KG |
40 | #define CCSRAR_C 0x80000000 /* Commit */ |
41 | u8 res1[4]; | |
8280912e KG |
42 | u32 altcbarh; /* Alternate Configuration Base Addr High */ |
43 | u32 altcbarl; /* Alternate Configuration Base Addr Low */ | |
44 | u32 altcar; /* Alternate Configuration Attr */ | |
01df5212 | 45 | u8 res2[4]; |
8280912e KG |
46 | u32 bstrh; /* Boot space translation high */ |
47 | u32 bstrl; /* Boot space translation Low */ | |
48 | u32 bstrar; /* Boot space translation attributes */ | |
01df5212 KG |
49 | u8 res3[0xbd4]; |
50 | struct { | |
8280912e KG |
51 | u32 lawbarh; /* LAWn base addr high */ |
52 | u32 lawbarl; /* LAWn base addr low */ | |
53 | u32 lawar; /* LAWn attributes */ | |
01df5212 KG |
54 | u8 res4[4]; |
55 | } law[32]; | |
56 | u8 res35[0x204]; | |
57 | } ccsr_local_t; | |
58 | ||
8280912e | 59 | /* Local-Access Registers & ECM Registers */ |
42d1f039 | 60 | typedef struct ccsr_local_ecm { |
8280912e KG |
61 | u32 ccsrbar; /* CCSR Base Addr */ |
62 | u8 res1[4]; | |
63 | u32 altcbar; /* Alternate Configuration Base Addr */ | |
64 | u8 res2[4]; | |
65 | u32 altcar; /* Alternate Configuration Attr */ | |
66 | u8 res3[12]; | |
67 | u32 bptr; /* Boot Page Translation */ | |
68 | u8 res4[3044]; | |
69 | u32 lawbar0; /* Local Access Window 0 Base Addr */ | |
70 | u8 res5[4]; | |
71 | u32 lawar0; /* Local Access Window 0 Attrs */ | |
72 | u8 res6[20]; | |
73 | u32 lawbar1; /* Local Access Window 1 Base Addr */ | |
74 | u8 res7[4]; | |
75 | u32 lawar1; /* Local Access Window 1 Attrs */ | |
76 | u8 res8[20]; | |
77 | u32 lawbar2; /* Local Access Window 2 Base Addr */ | |
78 | u8 res9[4]; | |
79 | u32 lawar2; /* Local Access Window 2 Attrs */ | |
80 | u8 res10[20]; | |
81 | u32 lawbar3; /* Local Access Window 3 Base Addr */ | |
82 | u8 res11[4]; | |
83 | u32 lawar3; /* Local Access Window 3 Attrs */ | |
84 | u8 res12[20]; | |
85 | u32 lawbar4; /* Local Access Window 4 Base Addr */ | |
86 | u8 res13[4]; | |
87 | u32 lawar4; /* Local Access Window 4 Attrs */ | |
88 | u8 res14[20]; | |
89 | u32 lawbar5; /* Local Access Window 5 Base Addr */ | |
90 | u8 res15[4]; | |
91 | u32 lawar5; /* Local Access Window 5 Attrs */ | |
92 | u8 res16[20]; | |
93 | u32 lawbar6; /* Local Access Window 6 Base Addr */ | |
94 | u8 res17[4]; | |
95 | u32 lawar6; /* Local Access Window 6 Attrs */ | |
96 | u8 res18[20]; | |
97 | u32 lawbar7; /* Local Access Window 7 Base Addr */ | |
98 | u8 res19[4]; | |
99 | u32 lawar7; /* Local Access Window 7 Attrs */ | |
100 | u8 res19_8a[20]; | |
101 | u32 lawbar8; /* Local Access Window 8 Base Addr */ | |
102 | u8 res19_8b[4]; | |
103 | u32 lawar8; /* Local Access Window 8 Attrs */ | |
104 | u8 res19_9a[20]; | |
105 | u32 lawbar9; /* Local Access Window 9 Base Addr */ | |
106 | u8 res19_9b[4]; | |
107 | u32 lawar9; /* Local Access Window 9 Attrs */ | |
108 | u8 res19_10a[20]; | |
109 | u32 lawbar10; /* Local Access Window 10 Base Addr */ | |
110 | u8 res19_10b[4]; | |
111 | u32 lawar10; /* Local Access Window 10 Attrs */ | |
112 | u8 res19_11a[20]; | |
113 | u32 lawbar11; /* Local Access Window 11 Base Addr */ | |
114 | u8 res19_11b[4]; | |
115 | u32 lawar11; /* Local Access Window 11 Attrs */ | |
116 | u8 res20[652]; | |
117 | u32 eebacr; /* ECM CCB Addr Configuration */ | |
118 | u8 res21[12]; | |
119 | u32 eebpcr; /* ECM CCB Port Configuration */ | |
120 | u8 res22[3564]; | |
121 | u32 eedr; /* ECM Error Detect */ | |
122 | u8 res23[4]; | |
123 | u32 eeer; /* ECM Error Enable */ | |
124 | u32 eeatr; /* ECM Error Attrs Capture */ | |
125 | u32 eeadr; /* ECM Error Addr Capture */ | |
126 | u8 res24[492]; | |
42d1f039 WD |
127 | } ccsr_local_ecm_t; |
128 | ||
8280912e | 129 | /* DDR memory controller registers */ |
42d1f039 | 130 | typedef struct ccsr_ddr { |
8280912e KG |
131 | u32 cs0_bnds; /* Chip Select 0 Memory Bounds */ |
132 | u8 res1[4]; | |
133 | u32 cs1_bnds; /* Chip Select 1 Memory Bounds */ | |
134 | u8 res2[4]; | |
135 | u32 cs2_bnds; /* Chip Select 2 Memory Bounds */ | |
136 | u8 res3[4]; | |
137 | u32 cs3_bnds; /* Chip Select 3 Memory Bounds */ | |
138 | u8 res4[100]; | |
139 | u32 cs0_config; /* Chip Select Configuration */ | |
140 | u32 cs1_config; /* Chip Select Configuration */ | |
141 | u32 cs2_config; /* Chip Select Configuration */ | |
142 | u32 cs3_config; /* Chip Select Configuration */ | |
143 | u8 res4a[48]; | |
144 | u32 cs0_config_2; /* Chip Select Configuration 2 */ | |
145 | u32 cs1_config_2; /* Chip Select Configuration 2 */ | |
146 | u32 cs2_config_2; /* Chip Select Configuration 2 */ | |
147 | u32 cs3_config_2; /* Chip Select Configuration 2 */ | |
148 | u8 res5[48]; | |
149 | u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */ | |
150 | u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */ | |
151 | u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */ | |
152 | u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */ | |
153 | u32 sdram_cfg; /* SDRAM Control Configuration */ | |
154 | u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */ | |
155 | u32 sdram_mode; /* SDRAM Mode Configuration */ | |
156 | u32 sdram_mode_2; /* SDRAM Mode Configuration 2 */ | |
157 | u32 sdram_md_cntl; /* SDRAM Mode Control */ | |
158 | u32 sdram_interval; /* SDRAM Interval Configuration */ | |
159 | u32 sdram_data_init; /* SDRAM Data initialization */ | |
160 | u8 res6[4]; | |
161 | u32 sdram_clk_cntl; /* SDRAM Clock Control */ | |
162 | u8 res7[20]; | |
163 | u32 init_addr; /* training init addr */ | |
164 | u32 init_ext_addr; /* training init extended addr */ | |
165 | u8 res8_1[16]; | |
166 | u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */ | |
167 | u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */ | |
168 | u8 reg8_1a[8]; | |
169 | u32 ddr_zq_cntl; /* ZQ calibration control*/ | |
170 | u32 ddr_wrlvl_cntl; /* write leveling control*/ | |
171 | u8 reg8_1aa[4]; | |
172 | u32 ddr_sr_cntr; /* self refresh counter */ | |
173 | u32 ddr_sdram_rcw_1; /* Control Words 1 */ | |
174 | u32 ddr_sdram_rcw_2; /* Control Words 2 */ | |
175 | u8 res8_1b[2456]; | |
176 | u32 ddr_dsr1; /* Debug Status 1 */ | |
177 | u32 ddr_dsr2; /* Debug Status 2 */ | |
178 | u32 ddr_cdr1; /* Control Driver 1 */ | |
179 | u32 ddr_cdr2; /* Control Driver 2 */ | |
180 | u8 res8_1c[200]; | |
181 | u32 ip_rev1; /* IP Block Revision 1 */ | |
182 | u32 ip_rev2; /* IP Block Revision 2 */ | |
183 | u8 res8_2[512]; | |
184 | u32 data_err_inject_hi; /* Data Path Err Injection Mask High */ | |
185 | u32 data_err_inject_lo; /* Data Path Err Injection Mask Low */ | |
186 | u32 ecc_err_inject; /* Data Path Err Injection Mask ECC */ | |
187 | u8 res9[20]; | |
188 | u32 capture_data_hi; /* Data Path Read Capture High */ | |
189 | u32 capture_data_lo; /* Data Path Read Capture Low */ | |
190 | u32 capture_ecc; /* Data Path Read Capture ECC */ | |
191 | u8 res10[20]; | |
192 | u32 err_detect; /* Error Detect */ | |
193 | u32 err_disable; /* Error Disable */ | |
194 | u32 err_int_en; | |
195 | u32 capture_attributes; /* Error Attrs Capture */ | |
196 | u32 capture_address; /* Error Addr Capture */ | |
197 | u32 capture_ext_address; /* Error Extended Addr Capture */ | |
198 | u32 err_sbe; /* Single-Bit ECC Error Management */ | |
199 | u8 res11[164]; | |
200 | u32 debug_1; | |
201 | u32 debug_2; | |
202 | u32 debug_3; | |
203 | u32 debug_4; | |
204 | u32 debug_5; | |
205 | u32 debug_6; | |
206 | u32 debug_7; | |
207 | u32 debug_8; | |
208 | u32 debug_9; | |
209 | u32 debug_10; | |
210 | u32 debug_11; | |
211 | u32 debug_12; | |
212 | u32 debug_13; | |
213 | u32 debug_14; | |
214 | u32 debug_15; | |
215 | u32 debug_16; | |
216 | u32 debug_17; | |
217 | u32 debug_18; | |
218 | u8 res12[184]; | |
42d1f039 WD |
219 | } ccsr_ddr_t; |
220 | ||
8280912e | 221 | /* I2C Registers */ |
42d1f039 | 222 | typedef struct ccsr_i2c { |
3dfa9cfd JL |
223 | struct fsl_i2c i2c[1]; |
224 | u8 res[4096 - 1 * sizeof(struct fsl_i2c)]; | |
42d1f039 WD |
225 | } ccsr_i2c_t; |
226 | ||
03f5c550 WD |
227 | #if defined(CONFIG_MPC8540) \ |
228 | || defined(CONFIG_MPC8541) \ | |
d9b94f28 | 229 | || defined(CONFIG_MPC8548) \ |
03f5c550 | 230 | || defined(CONFIG_MPC8555) |
8280912e | 231 | /* DUART Registers */ |
42d1f039 | 232 | typedef struct ccsr_duart { |
8280912e KG |
233 | u8 res1[1280]; |
234 | /* URBR1, UTHR1, UDLB1 with the same addr */ | |
235 | u8 urbr1_uthr1_udlb1; | |
236 | /* UIER1, UDMB1 with the same addr01 */ | |
237 | u8 uier1_udmb1; | |
238 | /* UIIR1, UFCR1, UAFR1 with the same addr */ | |
239 | u8 uiir1_ufcr1_uafr1; | |
240 | u8 ulcr1; /* UART1 Line Control */ | |
241 | u8 umcr1; /* UART1 Modem Control */ | |
242 | u8 ulsr1; /* UART1 Line Status */ | |
243 | u8 umsr1; /* UART1 Modem Status */ | |
244 | u8 uscr1; /* UART1 Scratch */ | |
245 | u8 res2[8]; | |
246 | u8 udsr1; /* UART1 DMA Status */ | |
247 | u8 res3[239]; | |
248 | /* URBR2, UTHR2, UDLB2 with the same addr */ | |
249 | u8 urbr2_uthr2_udlb2; | |
250 | /* UIER2, UDMB2 with the same addr */ | |
251 | u8 uier2_udmb2; | |
252 | /* UIIR2, UFCR2, UAFR2 with the same addr */ | |
253 | u8 uiir2_ufcr2_uafr2; | |
254 | u8 ulcr2; /* UART2 Line Control */ | |
255 | u8 umcr2; /* UART2 Modem Control */ | |
256 | u8 ulsr2; /* UART2 Line Status */ | |
257 | u8 umsr2; /* UART2 Modem Status */ | |
258 | u8 uscr2; /* UART2 Scratch */ | |
259 | u8 res4[8]; | |
260 | u8 udsr2; /* UART2 DMA Status */ | |
261 | u8 res5[2543]; | |
42d1f039 WD |
262 | } ccsr_duart_t; |
263 | #else /* MPC8560 uses UART on its CPM */ | |
264 | typedef struct ccsr_duart { | |
8280912e | 265 | u8 res[4096]; |
42d1f039 WD |
266 | } ccsr_duart_t; |
267 | #endif | |
268 | ||
8280912e | 269 | /* Local Bus Controller Registers */ |
42d1f039 | 270 | typedef struct ccsr_lbc { |
8280912e KG |
271 | u32 br0; /* LBC Base 0 */ |
272 | u32 or0; /* LBC Options 0 */ | |
273 | u32 br1; /* LBC Base 1 */ | |
274 | u32 or1; /* LBC Options 1 */ | |
275 | u32 br2; /* LBC Base 2 */ | |
276 | u32 or2; /* LBC Options 2 */ | |
277 | u32 br3; /* LBC Base 3 */ | |
278 | u32 or3; /* LBC Options 3 */ | |
279 | u32 br4; /* LBC Base 4 */ | |
280 | u32 or4; /* LBC Options 4 */ | |
281 | u32 br5; /* LBC Base 5 */ | |
282 | u32 or5; /* LBC Options 5 */ | |
283 | u32 br6; /* LBC Base 6 */ | |
284 | u32 or6; /* LBC Options 6 */ | |
285 | u32 br7; /* LBC Base 7 */ | |
286 | u32 or7; /* LBC Options 7 */ | |
287 | u8 res1[40]; | |
288 | u32 mar; /* LBC UPM Addr */ | |
289 | u8 res2[4]; | |
290 | u32 mamr; /* LBC UPMA Mode */ | |
291 | u32 mbmr; /* LBC UPMB Mode */ | |
292 | u32 mcmr; /* LBC UPMC Mode */ | |
293 | u8 res3[8]; | |
294 | u32 mrtpr; /* LBC Memory Refresh Timer Prescaler */ | |
295 | u32 mdr; /* LBC UPM Data */ | |
296 | u8 res4[8]; | |
297 | u32 lsdmr; /* LBC SDRAM Mode */ | |
298 | u8 res5[8]; | |
299 | u32 lurt; /* LBC UPM Refresh Timer */ | |
300 | u32 lsrt; /* LBC SDRAM Refresh Timer */ | |
301 | u8 res6[8]; | |
302 | u32 ltesr; /* LBC Transfer Error Status */ | |
303 | u32 ltedr; /* LBC Transfer Error Disable */ | |
304 | u32 lteir; /* LBC Transfer Error IRQ */ | |
305 | u32 lteatr; /* LBC Transfer Error Attrs */ | |
306 | u32 ltear; /* LBC Transfer Error Addr */ | |
307 | u8 res7[12]; | |
308 | u32 lbcr; /* LBC Configuration */ | |
309 | u32 lcrr; /* LBC Clock Ratio */ | |
310 | u8 res8[3880]; | |
42d1f039 WD |
311 | } ccsr_lbc_t; |
312 | ||
8280912e | 313 | /* eSPI Registers */ |
7fa96a9a | 314 | typedef struct ccsr_espi { |
8280912e KG |
315 | u32 mode; /* eSPI mode */ |
316 | u32 event; /* eSPI event */ | |
317 | u32 mask; /* eSPI mask */ | |
318 | u32 com; /* eSPI command */ | |
319 | u32 tx; /* eSPI transmit FIFO access */ | |
320 | u32 rx; /* eSPI receive FIFO access */ | |
321 | u8 res1[8]; /* reserved */ | |
322 | u32 csmode[4]; /* 0x2c: sSPI CS0/1/2/3 mode */ | |
323 | u8 res2[4048]; /* fill up to 0x1000 */ | |
7fa96a9a MH |
324 | } ccsr_espi_t; |
325 | ||
8280912e | 326 | /* PCI Registers */ |
42d1f039 | 327 | typedef struct ccsr_pcix { |
8280912e KG |
328 | u32 cfg_addr; /* PCIX Configuration Addr */ |
329 | u32 cfg_data; /* PCIX Configuration Data */ | |
330 | u32 int_ack; /* PCIX IRQ Acknowledge */ | |
331 | u8 res1[3060]; | |
332 | u32 potar0; /* PCIX Outbound Transaction Addr 0 */ | |
333 | u32 potear0; /* PCIX Outbound Translation Extended Addr 0 */ | |
334 | u32 powbar0; /* PCIX Outbound Window Base Addr 0 */ | |
335 | u32 powbear0; /* PCIX Outbound Window Base Extended Addr 0 */ | |
336 | u32 powar0; /* PCIX Outbound Window Attrs 0 */ | |
337 | u8 res2[12]; | |
338 | u32 potar1; /* PCIX Outbound Transaction Addr 1 */ | |
339 | u32 potear1; /* PCIX Outbound Translation Extended Addr 1 */ | |
340 | u32 powbar1; /* PCIX Outbound Window Base Addr 1 */ | |
341 | u32 powbear1; /* PCIX Outbound Window Base Extended Addr 1 */ | |
342 | u32 powar1; /* PCIX Outbound Window Attrs 1 */ | |
343 | u8 res3[12]; | |
344 | u32 potar2; /* PCIX Outbound Transaction Addr 2 */ | |
345 | u32 potear2; /* PCIX Outbound Translation Extended Addr 2 */ | |
346 | u32 powbar2; /* PCIX Outbound Window Base Addr 2 */ | |
347 | u32 powbear2; /* PCIX Outbound Window Base Extended Addr 2 */ | |
348 | u32 powar2; /* PCIX Outbound Window Attrs 2 */ | |
349 | u8 res4[12]; | |
350 | u32 potar3; /* PCIX Outbound Transaction Addr 3 */ | |
351 | u32 potear3; /* PCIX Outbound Translation Extended Addr 3 */ | |
352 | u32 powbar3; /* PCIX Outbound Window Base Addr 3 */ | |
353 | u32 powbear3; /* PCIX Outbound Window Base Extended Addr 3 */ | |
354 | u32 powar3; /* PCIX Outbound Window Attrs 3 */ | |
355 | u8 res5[12]; | |
356 | u32 potar4; /* PCIX Outbound Transaction Addr 4 */ | |
357 | u32 potear4; /* PCIX Outbound Translation Extended Addr 4 */ | |
358 | u32 powbar4; /* PCIX Outbound Window Base Addr 4 */ | |
359 | u32 powbear4; /* PCIX Outbound Window Base Extended Addr 4 */ | |
360 | u32 powar4; /* PCIX Outbound Window Attrs 4 */ | |
361 | u8 res6[268]; | |
362 | u32 pitar3; /* PCIX Inbound Translation Addr 3 */ | |
363 | u32 pitear3; /* PCIX Inbound Translation Extended Addr 3 */ | |
364 | u32 piwbar3; /* PCIX Inbound Window Base Addr 3 */ | |
365 | u32 piwbear3; /* PCIX Inbound Window Base Extended Addr 3 */ | |
366 | u32 piwar3; /* PCIX Inbound Window Attrs 3 */ | |
367 | u8 res7[12]; | |
368 | u32 pitar2; /* PCIX Inbound Translation Addr 2 */ | |
369 | u32 pitear2; /* PCIX Inbound Translation Extended Addr 2 */ | |
370 | u32 piwbar2; /* PCIX Inbound Window Base Addr 2 */ | |
371 | u32 piwbear2; /* PCIX Inbound Window Base Extended Addr 2 */ | |
372 | u32 piwar2; /* PCIX Inbound Window Attrs 2 */ | |
373 | u8 res8[12]; | |
374 | u32 pitar1; /* PCIX Inbound Translation Addr 1 */ | |
375 | u32 pitear1; /* PCIX Inbound Translation Extended Addr 1 */ | |
376 | u32 piwbar1; /* PCIX Inbound Window Base Addr 1 */ | |
377 | u8 res9[4]; | |
378 | u32 piwar1; /* PCIX Inbound Window Attrs 1 */ | |
379 | u8 res10[12]; | |
380 | u32 pedr; /* PCIX Error Detect */ | |
381 | u32 pecdr; /* PCIX Error Capture Disable */ | |
382 | u32 peer; /* PCIX Error Enable */ | |
383 | u32 peattrcr; /* PCIX Error Attrs Capture */ | |
384 | u32 peaddrcr; /* PCIX Error Addr Capture */ | |
385 | u32 peextaddrcr; /* PCIX Error Extended Addr Capture */ | |
386 | u32 pedlcr; /* PCIX Error Data Low Capture */ | |
387 | u32 pedhcr; /* PCIX Error Error Data High Capture */ | |
388 | u32 gas_timr; /* PCIX Gasket Timer */ | |
389 | u8 res11[476]; | |
42d1f039 WD |
390 | } ccsr_pcix_t; |
391 | ||
97074ed9 MM |
392 | #define PCIX_COMMAND 0x62 |
393 | #define POWAR_EN 0x80000000 | |
394 | #define POWAR_IO_READ 0x00080000 | |
395 | #define POWAR_MEM_READ 0x00040000 | |
396 | #define POWAR_IO_WRITE 0x00008000 | |
397 | #define POWAR_MEM_WRITE 0x00004000 | |
398 | #define POWAR_MEM_512M 0x0000001c | |
399 | #define POWAR_IO_1M 0x00000013 | |
400 | ||
401 | #define PIWAR_EN 0x80000000 | |
402 | #define PIWAR_PF 0x20000000 | |
403 | #define PIWAR_LOCAL 0x00f00000 | |
404 | #define PIWAR_READ_SNOOP 0x00050000 | |
405 | #define PIWAR_WRITE_SNOOP 0x00005000 | |
406 | #define PIWAR_MEM_2G 0x0000001e | |
407 | ||
8280912e KG |
408 | typedef struct ccsr_gpio { |
409 | u32 gpdir; | |
410 | u32 gpodr; | |
411 | u32 gpdat; | |
412 | u32 gpier; | |
413 | u32 gpimr; | |
414 | u32 gpicr; | |
415 | } ccsr_gpio_t; | |
97074ed9 | 416 | |
8280912e | 417 | /* L2 Cache Registers */ |
42d1f039 | 418 | typedef struct ccsr_l2cache { |
8280912e KG |
419 | u32 l2ctl; /* L2 configuration 0 */ |
420 | u8 res1[12]; | |
421 | u32 l2cewar0; /* L2 cache external write addr 0 */ | |
422 | u8 res2[4]; | |
423 | u32 l2cewcr0; /* L2 cache external write control 0 */ | |
424 | u8 res3[4]; | |
425 | u32 l2cewar1; /* L2 cache external write addr 1 */ | |
426 | u8 res4[4]; | |
427 | u32 l2cewcr1; /* L2 cache external write control 1 */ | |
428 | u8 res5[4]; | |
429 | u32 l2cewar2; /* L2 cache external write addr 2 */ | |
430 | u8 res6[4]; | |
431 | u32 l2cewcr2; /* L2 cache external write control 2 */ | |
432 | u8 res7[4]; | |
433 | u32 l2cewar3; /* L2 cache external write addr 3 */ | |
434 | u8 res8[4]; | |
435 | u32 l2cewcr3; /* L2 cache external write control 3 */ | |
436 | u8 res9[180]; | |
437 | u32 l2srbar0; /* L2 memory-mapped SRAM base addr 0 */ | |
438 | u8 res10[4]; | |
439 | u32 l2srbar1; /* L2 memory-mapped SRAM base addr 1 */ | |
440 | u8 res11[3316]; | |
441 | u32 l2errinjhi; /* L2 error injection mask high */ | |
442 | u32 l2errinjlo; /* L2 error injection mask low */ | |
443 | u32 l2errinjctl; /* L2 error injection tag/ECC control */ | |
444 | u8 res12[20]; | |
445 | u32 l2captdatahi; /* L2 error data high capture */ | |
446 | u32 l2captdatalo; /* L2 error data low capture */ | |
447 | u32 l2captecc; /* L2 error ECC capture */ | |
448 | u8 res13[20]; | |
449 | u32 l2errdet; /* L2 error detect */ | |
450 | u32 l2errdis; /* L2 error disable */ | |
451 | u32 l2errinten; /* L2 error interrupt enable */ | |
452 | u32 l2errattr; /* L2 error attributes capture */ | |
453 | u32 l2erraddr; /* L2 error addr capture */ | |
454 | u8 res14[4]; | |
455 | u32 l2errctl; /* L2 error control */ | |
456 | u8 res15[420]; | |
42d1f039 WD |
457 | } ccsr_l2cache_t; |
458 | ||
76b474e2 MH |
459 | #define MPC85xx_L2CTL_L2E 0x80000000 |
460 | #define MPC85xx_L2CTL_L2SRAM_ENTIRE 0x00010000 | |
461 | #define MPC85xx_L2ERRDIS_MBECC 0x00000008 | |
462 | #define MPC85xx_L2ERRDIS_SBECC 0x00000004 | |
463 | ||
8280912e | 464 | /* DMA Registers */ |
42d1f039 | 465 | typedef struct ccsr_dma { |
8280912e | 466 | u8 res1[256]; |
b1f12650 | 467 | struct fsl_dma dma[4]; |
8280912e KG |
468 | u32 dgsr; /* DMA General Status */ |
469 | u8 res2[11516]; | |
42d1f039 WD |
470 | } ccsr_dma_t; |
471 | ||
8280912e | 472 | /* tsec */ |
42d1f039 | 473 | typedef struct ccsr_tsec { |
8280912e KG |
474 | u8 res1[16]; |
475 | u32 ievent; /* IRQ Event */ | |
476 | u32 imask; /* IRQ Mask */ | |
477 | u32 edis; /* Error Disabled */ | |
478 | u8 res2[4]; | |
479 | u32 ecntrl; /* Ethernet Control */ | |
480 | u32 minflr; /* Minimum Frame Len */ | |
481 | u32 ptv; /* Pause Time Value */ | |
482 | u32 dmactrl; /* DMA Control */ | |
483 | u32 tbipa; /* TBI PHY Addr */ | |
484 | u8 res3[88]; | |
485 | u32 fifo_tx_thr; /* FIFO transmit threshold */ | |
486 | u8 res4[8]; | |
487 | u32 fifo_tx_starve; /* FIFO transmit starve */ | |
488 | u32 fifo_tx_starve_shutoff; /* FIFO transmit starve shutoff */ | |
489 | u8 res5[96]; | |
490 | u32 tctrl; /* TX Control */ | |
491 | u32 tstat; /* TX Status */ | |
492 | u8 res6[4]; | |
493 | u32 tbdlen; /* TX Buffer Desc Data Len */ | |
494 | u8 res7[16]; | |
495 | u32 ctbptrh; /* Current TX Buffer Desc Ptr High */ | |
496 | u32 ctbptr; /* Current TX Buffer Desc Ptr */ | |
497 | u8 res8[88]; | |
498 | u32 tbptrh; /* TX Buffer Desc Ptr High */ | |
499 | u32 tbptr; /* TX Buffer Desc Ptr Low */ | |
500 | u8 res9[120]; | |
501 | u32 tbaseh; /* TX Desc Base Addr High */ | |
502 | u32 tbase; /* TX Desc Base Addr */ | |
503 | u8 res10[168]; | |
504 | u32 ostbd; /* Out-of-Sequence(OOS) TX Buffer Desc */ | |
505 | u32 ostbdp; /* OOS TX Data Buffer Ptr */ | |
506 | u32 os32tbdp; /* OOS 32 Bytes TX Data Buffer Ptr Low */ | |
507 | u32 os32iptrh; /* OOS 32 Bytes TX Insert Ptr High */ | |
508 | u32 os32iptrl; /* OOS 32 Bytes TX Insert Ptr Low */ | |
509 | u32 os32tbdr; /* OOS 32 Bytes TX Reserved */ | |
510 | u32 os32iil; /* OOS 32 Bytes TX Insert Idx/Len */ | |
511 | u8 res11[52]; | |
512 | u32 rctrl; /* RX Control */ | |
513 | u32 rstat; /* RX Status */ | |
514 | u8 res12[4]; | |
515 | u32 rbdlen; /* RxBD Data Len */ | |
516 | u8 res13[16]; | |
517 | u32 crbptrh; /* Current RX Buffer Desc Ptr High */ | |
518 | u32 crbptr; /* Current RX Buffer Desc Ptr */ | |
519 | u8 res14[24]; | |
520 | u32 mrblr; /* Maximum RX Buffer Len */ | |
521 | u32 mrblr2r3; /* Maximum RX Buffer Len R2R3 */ | |
522 | u8 res15[56]; | |
523 | u32 rbptrh; /* RX Buffer Desc Ptr High 0 */ | |
524 | u32 rbptr; /* RX Buffer Desc Ptr */ | |
525 | u32 rbptrh1; /* RX Buffer Desc Ptr High 1 */ | |
526 | u32 rbptrl1; /* RX Buffer Desc Ptr Low 1 */ | |
527 | u32 rbptrh2; /* RX Buffer Desc Ptr High 2 */ | |
528 | u32 rbptrl2; /* RX Buffer Desc Ptr Low 2 */ | |
529 | u32 rbptrh3; /* RX Buffer Desc Ptr High 3 */ | |
530 | u32 rbptrl3; /* RX Buffer Desc Ptr Low 3 */ | |
531 | u8 res16[96]; | |
532 | u32 rbaseh; /* RX Desc Base Addr High 0 */ | |
533 | u32 rbase; /* RX Desc Base Addr */ | |
534 | u32 rbaseh1; /* RX Desc Base Addr High 1 */ | |
535 | u32 rbasel1; /* RX Desc Base Addr Low 1 */ | |
536 | u32 rbaseh2; /* RX Desc Base Addr High 2 */ | |
537 | u32 rbasel2; /* RX Desc Base Addr Low 2 */ | |
538 | u32 rbaseh3; /* RX Desc Base Addr High 3 */ | |
539 | u32 rbasel3; /* RX Desc Base Addr Low 3 */ | |
540 | u8 res17[224]; | |
541 | u32 maccfg1; /* MAC Configuration 1 */ | |
542 | u32 maccfg2; /* MAC Configuration 2 */ | |
543 | u32 ipgifg; /* Inter Packet Gap/Inter Frame Gap */ | |
544 | u32 hafdup; /* Half Duplex */ | |
545 | u32 maxfrm; /* Maximum Frame Len */ | |
546 | u8 res18[12]; | |
547 | u32 miimcfg; /* MII Management Configuration */ | |
548 | u32 miimcom; /* MII Management Cmd */ | |
549 | u32 miimadd; /* MII Management Addr */ | |
550 | u32 miimcon; /* MII Management Control */ | |
551 | u32 miimstat; /* MII Management Status */ | |
552 | u32 miimind; /* MII Management Indicator */ | |
553 | u8 res19[4]; | |
554 | u32 ifstat; /* Interface Status */ | |
555 | u32 macstnaddr1; /* Station Addr Part 1 */ | |
556 | u32 macstnaddr2; /* Station Addr Part 2 */ | |
557 | u8 res20[312]; | |
558 | u32 tr64; /* TX & RX 64-byte Frame Counter */ | |
559 | u32 tr127; /* TX & RX 65-127 byte Frame Counter */ | |
560 | u32 tr255; /* TX & RX 128-255 byte Frame Counter */ | |
561 | u32 tr511; /* TX & RX 256-511 byte Frame Counter */ | |
562 | u32 tr1k; /* TX & RX 512-1023 byte Frame Counter */ | |
563 | u32 trmax; /* TX & RX 1024-1518 byte Frame Counter */ | |
564 | u32 trmgv; /* TX & RX 1519-1522 byte Good VLAN Frame */ | |
565 | u32 rbyt; /* RX Byte Counter */ | |
566 | u32 rpkt; /* RX Packet Counter */ | |
567 | u32 rfcs; /* RX FCS Error Counter */ | |
568 | u32 rmca; /* RX Multicast Packet Counter */ | |
569 | u32 rbca; /* RX Broadcast Packet Counter */ | |
570 | u32 rxcf; /* RX Control Frame Packet Counter */ | |
571 | u32 rxpf; /* RX Pause Frame Packet Counter */ | |
572 | u32 rxuo; /* RX Unknown OP Code Counter */ | |
573 | u32 raln; /* RX Alignment Error Counter */ | |
574 | u32 rflr; /* RX Frame Len Error Counter */ | |
575 | u32 rcde; /* RX Code Error Counter */ | |
576 | u32 rcse; /* RX Carrier Sense Error Counter */ | |
577 | u32 rund; /* RX Undersize Packet Counter */ | |
578 | u32 rovr; /* RX Oversize Packet Counter */ | |
579 | u32 rfrg; /* RX Fragments Counter */ | |
580 | u32 rjbr; /* RX Jabber Counter */ | |
581 | u32 rdrp; /* RX Drop Counter */ | |
582 | u32 tbyt; /* TX Byte Counter Counter */ | |
583 | u32 tpkt; /* TX Packet Counter */ | |
584 | u32 tmca; /* TX Multicast Packet Counter */ | |
585 | u32 tbca; /* TX Broadcast Packet Counter */ | |
586 | u32 txpf; /* TX Pause Control Frame Counter */ | |
587 | u32 tdfr; /* TX Deferral Packet Counter */ | |
588 | u32 tedf; /* TX Excessive Deferral Packet Counter */ | |
589 | u32 tscl; /* TX Single Collision Packet Counter */ | |
590 | u32 tmcl; /* TX Multiple Collision Packet Counter */ | |
591 | u32 tlcl; /* TX Late Collision Packet Counter */ | |
592 | u32 txcl; /* TX Excessive Collision Packet Counter */ | |
593 | u32 tncl; /* TX Total Collision Counter */ | |
594 | u8 res21[4]; | |
595 | u32 tdrp; /* TX Drop Frame Counter */ | |
596 | u32 tjbr; /* TX Jabber Frame Counter */ | |
597 | u32 tfcs; /* TX FCS Error Counter */ | |
598 | u32 txcf; /* TX Control Frame Counter */ | |
599 | u32 tovr; /* TX Oversize Frame Counter */ | |
600 | u32 tund; /* TX Undersize Frame Counter */ | |
601 | u32 tfrg; /* TX Fragments Frame Counter */ | |
602 | u32 car1; /* Carry One */ | |
603 | u32 car2; /* Carry Two */ | |
604 | u32 cam1; /* Carry Mask One */ | |
605 | u32 cam2; /* Carry Mask Two */ | |
606 | u8 res22[192]; | |
607 | u32 iaddr0; /* Indivdual addr 0 */ | |
608 | u32 iaddr1; /* Indivdual addr 1 */ | |
609 | u32 iaddr2; /* Indivdual addr 2 */ | |
610 | u32 iaddr3; /* Indivdual addr 3 */ | |
611 | u32 iaddr4; /* Indivdual addr 4 */ | |
612 | u32 iaddr5; /* Indivdual addr 5 */ | |
613 | u32 iaddr6; /* Indivdual addr 6 */ | |
614 | u32 iaddr7; /* Indivdual addr 7 */ | |
615 | u8 res23[96]; | |
616 | u32 gaddr0; /* Global addr 0 */ | |
617 | u32 gaddr1; /* Global addr 1 */ | |
618 | u32 gaddr2; /* Global addr 2 */ | |
619 | u32 gaddr3; /* Global addr 3 */ | |
620 | u32 gaddr4; /* Global addr 4 */ | |
621 | u32 gaddr5; /* Global addr 5 */ | |
622 | u32 gaddr6; /* Global addr 6 */ | |
623 | u32 gaddr7; /* Global addr 7 */ | |
624 | u8 res24[96]; | |
625 | u32 pmd0; /* Pattern Match Data */ | |
626 | u8 res25[4]; | |
627 | u32 pmask0; /* Pattern Mask */ | |
628 | u8 res26[4]; | |
629 | u32 pcntrl0; /* Pattern Match Control */ | |
630 | u8 res27[4]; | |
631 | u32 pattrb0; /* Pattern Match Attrs */ | |
632 | u32 pattrbeli0; /* Pattern Match Attrs Extract Len & Idx */ | |
633 | u32 pmd1; /* Pattern Match Data */ | |
634 | u8 res28[4]; | |
635 | u32 pmask1; /* Pattern Mask */ | |
636 | u8 res29[4]; | |
637 | u32 pcntrl1; /* Pattern Match Control */ | |
638 | u8 res30[4]; | |
639 | u32 pattrb1; /* Pattern Match Attrs */ | |
640 | u32 pattrbeli1; /* Pattern Match Attrs Extract Len & Idx */ | |
641 | u32 pmd2; /* Pattern Match Data */ | |
642 | u8 res31[4]; | |
643 | u32 pmask2; /* Pattern Mask */ | |
644 | u8 res32[4]; | |
645 | u32 pcntrl2; /* Pattern Match Control */ | |
646 | u8 res33[4]; | |
647 | u32 pattrb2; /* Pattern Match Attrs */ | |
648 | u32 pattrbeli2; /* Pattern Match Attrs Extract Len & Idx */ | |
649 | u32 pmd3; /* Pattern Match Data */ | |
650 | u8 res34[4]; | |
651 | u32 pmask3; /* Pattern Mask */ | |
652 | u8 res35[4]; | |
653 | u32 pcntrl3; /* Pattern Match Control */ | |
654 | u8 res36[4]; | |
655 | u32 pattrb3; /* Pattern Match Attrs */ | |
656 | u32 pattrbeli3; /* Pattern Match Attrs Extract Len & Idx */ | |
657 | u32 pmd4; /* Pattern Match Data */ | |
658 | u8 res37[4]; | |
659 | u32 pmask4; /* Pattern Mask */ | |
660 | u8 res38[4]; | |
661 | u32 pcntrl4; /* Pattern Match Control */ | |
662 | u8 res39[4]; | |
663 | u32 pattrb4; /* Pattern Match Attrs */ | |
664 | u32 pattrbeli4; /* Pattern Match Attrs Extract Len & Idx */ | |
665 | u32 pmd5; /* Pattern Match Data */ | |
666 | u8 res40[4]; | |
667 | u32 pmask5; /* Pattern Mask */ | |
668 | u8 res41[4]; | |
669 | u32 pcntrl5; /* Pattern Match Control */ | |
670 | u8 res42[4]; | |
671 | u32 pattrb5; /* Pattern Match Attrs */ | |
672 | u32 pattrbeli5; /* Pattern Match Attrs Extract Len & Idx */ | |
673 | u32 pmd6; /* Pattern Match Data */ | |
674 | u8 res43[4]; | |
675 | u32 pmask6; /* Pattern Mask */ | |
676 | u8 res44[4]; | |
677 | u32 pcntrl6; /* Pattern Match Control */ | |
678 | u8 res45[4]; | |
679 | u32 pattrb6; /* Pattern Match Attrs */ | |
680 | u32 pattrbeli6; /* Pattern Match Attrs Extract Len & Idx */ | |
681 | u32 pmd7; /* Pattern Match Data */ | |
682 | u8 res46[4]; | |
683 | u32 pmask7; /* Pattern Mask */ | |
684 | u8 res47[4]; | |
685 | u32 pcntrl7; /* Pattern Match Control */ | |
686 | u8 res48[4]; | |
687 | u32 pattrb7; /* Pattern Match Attrs */ | |
688 | u32 pattrbeli7; /* Pattern Match Attrs Extract Len & Idx */ | |
689 | u32 pmd8; /* Pattern Match Data */ | |
690 | u8 res49[4]; | |
691 | u32 pmask8; /* Pattern Mask */ | |
692 | u8 res50[4]; | |
693 | u32 pcntrl8; /* Pattern Match Control */ | |
694 | u8 res51[4]; | |
695 | u32 pattrb8; /* Pattern Match Attrs */ | |
696 | u32 pattrbeli8; /* Pattern Match Attrs Extract Len & Idx */ | |
697 | u32 pmd9; /* Pattern Match Data */ | |
698 | u8 res52[4]; | |
699 | u32 pmask9; /* Pattern Mask */ | |
700 | u8 res53[4]; | |
701 | u32 pcntrl9; /* Pattern Match Control */ | |
702 | u8 res54[4]; | |
703 | u32 pattrb9; /* Pattern Match Attrs */ | |
704 | u32 pattrbeli9; /* Pattern Match Attrs Extract Len & Idx */ | |
705 | u32 pmd10; /* Pattern Match Data */ | |
706 | u8 res55[4]; | |
707 | u32 pmask10; /* Pattern Mask */ | |
708 | u8 res56[4]; | |
709 | u32 pcntrl10; /* Pattern Match Control */ | |
710 | u8 res57[4]; | |
711 | u32 pattrb10; /* Pattern Match Attrs */ | |
712 | u32 pattrbeli10; /* Pattern Match Attrs Extract Len & Idx */ | |
713 | u32 pmd11; /* Pattern Match Data */ | |
714 | u8 res58[4]; | |
715 | u32 pmask11; /* Pattern Mask */ | |
716 | u8 res59[4]; | |
717 | u32 pcntrl11; /* Pattern Match Control */ | |
718 | u8 res60[4]; | |
719 | u32 pattrb11; /* Pattern Match Attrs */ | |
720 | u32 pattrbeli11; /* Pattern Match Attrs Extract Len & Idx */ | |
721 | u32 pmd12; /* Pattern Match Data */ | |
722 | u8 res61[4]; | |
723 | u32 pmask12; /* Pattern Mask */ | |
724 | u8 res62[4]; | |
725 | u32 pcntrl12; /* Pattern Match Control */ | |
726 | u8 res63[4]; | |
727 | u32 pattrb12; /* Pattern Match Attrs */ | |
728 | u32 pattrbeli12; /* Pattern Match Attrs Extract Len & Idx */ | |
729 | u32 pmd13; /* Pattern Match Data */ | |
730 | u8 res64[4]; | |
731 | u32 pmask13; /* Pattern Mask */ | |
732 | u8 res65[4]; | |
733 | u32 pcntrl13; /* Pattern Match Control */ | |
734 | u8 res66[4]; | |
735 | u32 pattrb13; /* Pattern Match Attrs */ | |
736 | u32 pattrbeli13; /* Pattern Match Attrs Extract Len & Idx */ | |
737 | u32 pmd14; /* Pattern Match Data */ | |
738 | u8 res67[4]; | |
739 | u32 pmask14; /* Pattern Mask */ | |
740 | u8 res68[4]; | |
741 | u32 pcntrl14; /* Pattern Match Control */ | |
742 | u8 res69[4]; | |
743 | u32 pattrb14; /* Pattern Match Attrs */ | |
744 | u32 pattrbeli14; /* Pattern Match Attrs Extract Len & Idx */ | |
745 | u32 pmd15; /* Pattern Match Data */ | |
746 | u8 res70[4]; | |
747 | u32 pmask15; /* Pattern Mask */ | |
748 | u8 res71[4]; | |
749 | u32 pcntrl15; /* Pattern Match Control */ | |
750 | u8 res72[4]; | |
751 | u32 pattrb15; /* Pattern Match Attrs */ | |
752 | u32 pattrbeli15; /* Pattern Match Attrs Extract Len & Idx */ | |
753 | u8 res73[248]; | |
754 | u32 attr; /* Attrs */ | |
755 | u32 attreli; /* Attrs Extract Len & Idx */ | |
756 | u8 res74[1024]; | |
42d1f039 WD |
757 | } ccsr_tsec_t; |
758 | ||
8280912e | 759 | /* PIC Registers */ |
42d1f039 | 760 | typedef struct ccsr_pic { |
8280912e KG |
761 | u8 res1[64]; |
762 | u32 ipidr0; /* Interprocessor IRQ Dispatch 0 */ | |
763 | u8 res2[12]; | |
764 | u32 ipidr1; /* Interprocessor IRQ Dispatch 1 */ | |
765 | u8 res3[12]; | |
766 | u32 ipidr2; /* Interprocessor IRQ Dispatch 2 */ | |
767 | u8 res4[12]; | |
768 | u32 ipidr3; /* Interprocessor IRQ Dispatch 3 */ | |
769 | u8 res5[12]; | |
770 | u32 ctpr; /* Current Task Priority */ | |
771 | u8 res6[12]; | |
772 | u32 whoami; /* Who Am I */ | |
773 | u8 res7[12]; | |
774 | u32 iack; /* IRQ Acknowledge */ | |
775 | u8 res8[12]; | |
776 | u32 eoi; /* End Of IRQ */ | |
777 | u8 res9[3916]; | |
778 | u32 frr; /* Feature Reporting */ | |
779 | u8 res10[28]; | |
780 | u32 gcr; /* Global Configuration */ | |
781 | #define MPC85xx_PICGCR_RST 0x80000000 | |
782 | #define MPC85xx_PICGCR_M 0x20000000 | |
783 | u8 res11[92]; | |
784 | u32 vir; /* Vendor Identification */ | |
785 | u8 res12[12]; | |
786 | u32 pir; /* Processor Initialization */ | |
787 | u8 res13[12]; | |
788 | u32 ipivpr0; /* IPI Vector/Priority 0 */ | |
789 | u8 res14[12]; | |
790 | u32 ipivpr1; /* IPI Vector/Priority 1 */ | |
791 | u8 res15[12]; | |
792 | u32 ipivpr2; /* IPI Vector/Priority 2 */ | |
793 | u8 res16[12]; | |
794 | u32 ipivpr3; /* IPI Vector/Priority 3 */ | |
795 | u8 res17[12]; | |
796 | u32 svr; /* Spurious Vector */ | |
797 | u8 res18[12]; | |
798 | u32 tfrr; /* Timer Frequency Reporting */ | |
799 | u8 res19[12]; | |
800 | u32 gtccr0; /* Global Timer Current Count 0 */ | |
801 | u8 res20[12]; | |
802 | u32 gtbcr0; /* Global Timer Base Count 0 */ | |
803 | u8 res21[12]; | |
804 | u32 gtvpr0; /* Global Timer Vector/Priority 0 */ | |
805 | u8 res22[12]; | |
806 | u32 gtdr0; /* Global Timer Destination 0 */ | |
807 | u8 res23[12]; | |
808 | u32 gtccr1; /* Global Timer Current Count 1 */ | |
809 | u8 res24[12]; | |
810 | u32 gtbcr1; /* Global Timer Base Count 1 */ | |
811 | u8 res25[12]; | |
812 | u32 gtvpr1; /* Global Timer Vector/Priority 1 */ | |
813 | u8 res26[12]; | |
814 | u32 gtdr1; /* Global Timer Destination 1 */ | |
815 | u8 res27[12]; | |
816 | u32 gtccr2; /* Global Timer Current Count 2 */ | |
817 | u8 res28[12]; | |
818 | u32 gtbcr2; /* Global Timer Base Count 2 */ | |
819 | u8 res29[12]; | |
820 | u32 gtvpr2; /* Global Timer Vector/Priority 2 */ | |
821 | u8 res30[12]; | |
822 | u32 gtdr2; /* Global Timer Destination 2 */ | |
823 | u8 res31[12]; | |
824 | u32 gtccr3; /* Global Timer Current Count 3 */ | |
825 | u8 res32[12]; | |
826 | u32 gtbcr3; /* Global Timer Base Count 3 */ | |
827 | u8 res33[12]; | |
828 | u32 gtvpr3; /* Global Timer Vector/Priority 3 */ | |
829 | u8 res34[12]; | |
830 | u32 gtdr3; /* Global Timer Destination 3 */ | |
831 | u8 res35[268]; | |
832 | u32 tcr; /* Timer Control */ | |
833 | u8 res36[12]; | |
834 | u32 irqsr0; /* IRQ_OUT Summary 0 */ | |
835 | u8 res37[12]; | |
836 | u32 irqsr1; /* IRQ_OUT Summary 1 */ | |
837 | u8 res38[12]; | |
838 | u32 cisr0; /* Critical IRQ Summary 0 */ | |
839 | u8 res39[12]; | |
840 | u32 cisr1; /* Critical IRQ Summary 1 */ | |
841 | u8 res40[188]; | |
842 | u32 msgr0; /* Message 0 */ | |
843 | u8 res41[12]; | |
844 | u32 msgr1; /* Message 1 */ | |
845 | u8 res42[12]; | |
846 | u32 msgr2; /* Message 2 */ | |
847 | u8 res43[12]; | |
848 | u32 msgr3; /* Message 3 */ | |
849 | u8 res44[204]; | |
850 | u32 mer; /* Message Enable */ | |
851 | u8 res45[12]; | |
852 | u32 msr; /* Message Status */ | |
853 | u8 res46[60140]; | |
854 | u32 eivpr0; /* External IRQ Vector/Priority 0 */ | |
855 | u8 res47[12]; | |
856 | u32 eidr0; /* External IRQ Destination 0 */ | |
857 | u8 res48[12]; | |
858 | u32 eivpr1; /* External IRQ Vector/Priority 1 */ | |
859 | u8 res49[12]; | |
860 | u32 eidr1; /* External IRQ Destination 1 */ | |
861 | u8 res50[12]; | |
862 | u32 eivpr2; /* External IRQ Vector/Priority 2 */ | |
863 | u8 res51[12]; | |
864 | u32 eidr2; /* External IRQ Destination 2 */ | |
865 | u8 res52[12]; | |
866 | u32 eivpr3; /* External IRQ Vector/Priority 3 */ | |
867 | u8 res53[12]; | |
868 | u32 eidr3; /* External IRQ Destination 3 */ | |
869 | u8 res54[12]; | |
870 | u32 eivpr4; /* External IRQ Vector/Priority 4 */ | |
871 | u8 res55[12]; | |
872 | u32 eidr4; /* External IRQ Destination 4 */ | |
873 | u8 res56[12]; | |
874 | u32 eivpr5; /* External IRQ Vector/Priority 5 */ | |
875 | u8 res57[12]; | |
876 | u32 eidr5; /* External IRQ Destination 5 */ | |
877 | u8 res58[12]; | |
878 | u32 eivpr6; /* External IRQ Vector/Priority 6 */ | |
879 | u8 res59[12]; | |
880 | u32 eidr6; /* External IRQ Destination 6 */ | |
881 | u8 res60[12]; | |
882 | u32 eivpr7; /* External IRQ Vector/Priority 7 */ | |
883 | u8 res61[12]; | |
884 | u32 eidr7; /* External IRQ Destination 7 */ | |
885 | u8 res62[12]; | |
886 | u32 eivpr8; /* External IRQ Vector/Priority 8 */ | |
887 | u8 res63[12]; | |
888 | u32 eidr8; /* External IRQ Destination 8 */ | |
889 | u8 res64[12]; | |
890 | u32 eivpr9; /* External IRQ Vector/Priority 9 */ | |
891 | u8 res65[12]; | |
892 | u32 eidr9; /* External IRQ Destination 9 */ | |
893 | u8 res66[12]; | |
894 | u32 eivpr10; /* External IRQ Vector/Priority 10 */ | |
895 | u8 res67[12]; | |
896 | u32 eidr10; /* External IRQ Destination 10 */ | |
897 | u8 res68[12]; | |
898 | u32 eivpr11; /* External IRQ Vector/Priority 11 */ | |
899 | u8 res69[12]; | |
900 | u32 eidr11; /* External IRQ Destination 11 */ | |
901 | u8 res70[140]; | |
902 | u32 iivpr0; /* Internal IRQ Vector/Priority 0 */ | |
903 | u8 res71[12]; | |
904 | u32 iidr0; /* Internal IRQ Destination 0 */ | |
905 | u8 res72[12]; | |
906 | u32 iivpr1; /* Internal IRQ Vector/Priority 1 */ | |
907 | u8 res73[12]; | |
908 | u32 iidr1; /* Internal IRQ Destination 1 */ | |
909 | u8 res74[12]; | |
910 | u32 iivpr2; /* Internal IRQ Vector/Priority 2 */ | |
911 | u8 res75[12]; | |
912 | u32 iidr2; /* Internal IRQ Destination 2 */ | |
913 | u8 res76[12]; | |
914 | u32 iivpr3; /* Internal IRQ Vector/Priority 3 */ | |
915 | u8 res77[12]; | |
916 | u32 iidr3; /* Internal IRQ Destination 3 */ | |
917 | u8 res78[12]; | |
918 | u32 iivpr4; /* Internal IRQ Vector/Priority 4 */ | |
919 | u8 res79[12]; | |
920 | u32 iidr4; /* Internal IRQ Destination 4 */ | |
921 | u8 res80[12]; | |
922 | u32 iivpr5; /* Internal IRQ Vector/Priority 5 */ | |
923 | u8 res81[12]; | |
924 | u32 iidr5; /* Internal IRQ Destination 5 */ | |
925 | u8 res82[12]; | |
926 | u32 iivpr6; /* Internal IRQ Vector/Priority 6 */ | |
927 | u8 res83[12]; | |
928 | u32 iidr6; /* Internal IRQ Destination 6 */ | |
929 | u8 res84[12]; | |
930 | u32 iivpr7; /* Internal IRQ Vector/Priority 7 */ | |
931 | u8 res85[12]; | |
932 | u32 iidr7; /* Internal IRQ Destination 7 */ | |
933 | u8 res86[12]; | |
934 | u32 iivpr8; /* Internal IRQ Vector/Priority 8 */ | |
935 | u8 res87[12]; | |
936 | u32 iidr8; /* Internal IRQ Destination 8 */ | |
937 | u8 res88[12]; | |
938 | u32 iivpr9; /* Internal IRQ Vector/Priority 9 */ | |
939 | u8 res89[12]; | |
940 | u32 iidr9; /* Internal IRQ Destination 9 */ | |
941 | u8 res90[12]; | |
942 | u32 iivpr10; /* Internal IRQ Vector/Priority 10 */ | |
943 | u8 res91[12]; | |
944 | u32 iidr10; /* Internal IRQ Destination 10 */ | |
945 | u8 res92[12]; | |
946 | u32 iivpr11; /* Internal IRQ Vector/Priority 11 */ | |
947 | u8 res93[12]; | |
948 | u32 iidr11; /* Internal IRQ Destination 11 */ | |
949 | u8 res94[12]; | |
950 | u32 iivpr12; /* Internal IRQ Vector/Priority 12 */ | |
951 | u8 res95[12]; | |
952 | u32 iidr12; /* Internal IRQ Destination 12 */ | |
953 | u8 res96[12]; | |
954 | u32 iivpr13; /* Internal IRQ Vector/Priority 13 */ | |
955 | u8 res97[12]; | |
956 | u32 iidr13; /* Internal IRQ Destination 13 */ | |
957 | u8 res98[12]; | |
958 | u32 iivpr14; /* Internal IRQ Vector/Priority 14 */ | |
959 | u8 res99[12]; | |
960 | u32 iidr14; /* Internal IRQ Destination 14 */ | |
961 | u8 res100[12]; | |
962 | u32 iivpr15; /* Internal IRQ Vector/Priority 15 */ | |
963 | u8 res101[12]; | |
964 | u32 iidr15; /* Internal IRQ Destination 15 */ | |
965 | u8 res102[12]; | |
966 | u32 iivpr16; /* Internal IRQ Vector/Priority 16 */ | |
967 | u8 res103[12]; | |
968 | u32 iidr16; /* Internal IRQ Destination 16 */ | |
969 | u8 res104[12]; | |
970 | u32 iivpr17; /* Internal IRQ Vector/Priority 17 */ | |
971 | u8 res105[12]; | |
972 | u32 iidr17; /* Internal IRQ Destination 17 */ | |
973 | u8 res106[12]; | |
974 | u32 iivpr18; /* Internal IRQ Vector/Priority 18 */ | |
975 | u8 res107[12]; | |
976 | u32 iidr18; /* Internal IRQ Destination 18 */ | |
977 | u8 res108[12]; | |
978 | u32 iivpr19; /* Internal IRQ Vector/Priority 19 */ | |
979 | u8 res109[12]; | |
980 | u32 iidr19; /* Internal IRQ Destination 19 */ | |
981 | u8 res110[12]; | |
982 | u32 iivpr20; /* Internal IRQ Vector/Priority 20 */ | |
983 | u8 res111[12]; | |
984 | u32 iidr20; /* Internal IRQ Destination 20 */ | |
985 | u8 res112[12]; | |
986 | u32 iivpr21; /* Internal IRQ Vector/Priority 21 */ | |
987 | u8 res113[12]; | |
988 | u32 iidr21; /* Internal IRQ Destination 21 */ | |
989 | u8 res114[12]; | |
990 | u32 iivpr22; /* Internal IRQ Vector/Priority 22 */ | |
991 | u8 res115[12]; | |
992 | u32 iidr22; /* Internal IRQ Destination 22 */ | |
993 | u8 res116[12]; | |
994 | u32 iivpr23; /* Internal IRQ Vector/Priority 23 */ | |
995 | u8 res117[12]; | |
996 | u32 iidr23; /* Internal IRQ Destination 23 */ | |
997 | u8 res118[12]; | |
998 | u32 iivpr24; /* Internal IRQ Vector/Priority 24 */ | |
999 | u8 res119[12]; | |
1000 | u32 iidr24; /* Internal IRQ Destination 24 */ | |
1001 | u8 res120[12]; | |
1002 | u32 iivpr25; /* Internal IRQ Vector/Priority 25 */ | |
1003 | u8 res121[12]; | |
1004 | u32 iidr25; /* Internal IRQ Destination 25 */ | |
1005 | u8 res122[12]; | |
1006 | u32 iivpr26; /* Internal IRQ Vector/Priority 26 */ | |
1007 | u8 res123[12]; | |
1008 | u32 iidr26; /* Internal IRQ Destination 26 */ | |
1009 | u8 res124[12]; | |
1010 | u32 iivpr27; /* Internal IRQ Vector/Priority 27 */ | |
1011 | u8 res125[12]; | |
1012 | u32 iidr27; /* Internal IRQ Destination 27 */ | |
1013 | u8 res126[12]; | |
1014 | u32 iivpr28; /* Internal IRQ Vector/Priority 28 */ | |
1015 | u8 res127[12]; | |
1016 | u32 iidr28; /* Internal IRQ Destination 28 */ | |
1017 | u8 res128[12]; | |
1018 | u32 iivpr29; /* Internal IRQ Vector/Priority 29 */ | |
1019 | u8 res129[12]; | |
1020 | u32 iidr29; /* Internal IRQ Destination 29 */ | |
1021 | u8 res130[12]; | |
1022 | u32 iivpr30; /* Internal IRQ Vector/Priority 30 */ | |
1023 | u8 res131[12]; | |
1024 | u32 iidr30; /* Internal IRQ Destination 30 */ | |
1025 | u8 res132[12]; | |
1026 | u32 iivpr31; /* Internal IRQ Vector/Priority 31 */ | |
1027 | u8 res133[12]; | |
1028 | u32 iidr31; /* Internal IRQ Destination 31 */ | |
1029 | u8 res134[4108]; | |
1030 | u32 mivpr0; /* Messaging IRQ Vector/Priority 0 */ | |
1031 | u8 res135[12]; | |
1032 | u32 midr0; /* Messaging IRQ Destination 0 */ | |
1033 | u8 res136[12]; | |
1034 | u32 mivpr1; /* Messaging IRQ Vector/Priority 1 */ | |
1035 | u8 res137[12]; | |
1036 | u32 midr1; /* Messaging IRQ Destination 1 */ | |
1037 | u8 res138[12]; | |
1038 | u32 mivpr2; /* Messaging IRQ Vector/Priority 2 */ | |
1039 | u8 res139[12]; | |
1040 | u32 midr2; /* Messaging IRQ Destination 2 */ | |
1041 | u8 res140[12]; | |
1042 | u32 mivpr3; /* Messaging IRQ Vector/Priority 3 */ | |
1043 | u8 res141[12]; | |
1044 | u32 midr3; /* Messaging IRQ Destination 3 */ | |
1045 | u8 res142[59852]; | |
1046 | u32 ipi0dr0; /* Processor 0 Interprocessor IRQ Dispatch 0 */ | |
1047 | u8 res143[12]; | |
1048 | u32 ipi0dr1; /* Processor 0 Interprocessor IRQ Dispatch 1 */ | |
1049 | u8 res144[12]; | |
1050 | u32 ipi0dr2; /* Processor 0 Interprocessor IRQ Dispatch 2 */ | |
1051 | u8 res145[12]; | |
1052 | u32 ipi0dr3; /* Processor 0 Interprocessor IRQ Dispatch 3 */ | |
1053 | u8 res146[12]; | |
1054 | u32 ctpr0; /* Current Task Priority for Processor 0 */ | |
1055 | u8 res147[12]; | |
1056 | u32 whoami0; /* Who Am I for Processor 0 */ | |
1057 | u8 res148[12]; | |
1058 | u32 iack0; /* IRQ Acknowledge for Processor 0 */ | |
1059 | u8 res149[12]; | |
1060 | u32 eoi0; /* End Of IRQ for Processor 0 */ | |
1061 | u8 res150[130892]; | |
42d1f039 WD |
1062 | } ccsr_pic_t; |
1063 | ||
8280912e | 1064 | /* CPM Block */ |
9c4c5ae3 | 1065 | #ifndef CONFIG_CPM2 |
42d1f039 | 1066 | typedef struct ccsr_cpm { |
8280912e | 1067 | u8 res[262144]; |
42d1f039 WD |
1068 | } ccsr_cpm_t; |
1069 | #else | |
de1d0a69 | 1070 | /* |
8280912e KG |
1071 | * DPARM |
1072 | * General SIU | |
de1d0a69 | 1073 | */ |
42d1f039 | 1074 | typedef struct ccsr_cpm_siu { |
8280912e KG |
1075 | u8 res1[80]; |
1076 | u32 smaer; | |
1077 | u32 smser; | |
1078 | u32 smevr; | |
1079 | u8 res2[4]; | |
1080 | u32 lmaer; | |
1081 | u32 lmser; | |
1082 | u32 lmevr; | |
1083 | u8 res3[2964]; | |
42d1f039 WD |
1084 | } ccsr_cpm_siu_t; |
1085 | ||
8280912e | 1086 | /* IRQ Controller */ |
42d1f039 | 1087 | typedef struct ccsr_cpm_intctl { |
8280912e KG |
1088 | u16 sicr; |
1089 | u8 res1[2]; | |
1090 | u32 sivec; | |
1091 | u32 sipnrh; | |
1092 | u32 sipnrl; | |
1093 | u32 siprr; | |
1094 | u32 scprrh; | |
1095 | u32 scprrl; | |
1096 | u32 simrh; | |
1097 | u32 simrl; | |
1098 | u32 siexr; | |
1099 | u8 res2[88]; | |
1100 | u32 sccr; | |
1101 | u8 res3[124]; | |
42d1f039 WD |
1102 | } ccsr_cpm_intctl_t; |
1103 | ||
8280912e | 1104 | /* input/output port */ |
42d1f039 | 1105 | typedef struct ccsr_cpm_iop { |
8280912e KG |
1106 | u32 pdira; |
1107 | u32 ppara; | |
1108 | u32 psora; | |
1109 | u32 podra; | |
1110 | u32 pdata; | |
1111 | u8 res1[12]; | |
1112 | u32 pdirb; | |
1113 | u32 pparb; | |
1114 | u32 psorb; | |
1115 | u32 podrb; | |
1116 | u32 pdatb; | |
1117 | u8 res2[12]; | |
1118 | u32 pdirc; | |
1119 | u32 pparc; | |
1120 | u32 psorc; | |
1121 | u32 podrc; | |
1122 | u32 pdatc; | |
1123 | u8 res3[12]; | |
1124 | u32 pdird; | |
1125 | u32 ppard; | |
1126 | u32 psord; | |
1127 | u32 podrd; | |
1128 | u32 pdatd; | |
1129 | u8 res4[12]; | |
42d1f039 WD |
1130 | } ccsr_cpm_iop_t; |
1131 | ||
8280912e | 1132 | /* CPM timers */ |
42d1f039 | 1133 | typedef struct ccsr_cpm_timer { |
8280912e KG |
1134 | u8 tgcr1; |
1135 | u8 res1[3]; | |
1136 | u8 tgcr2; | |
1137 | u8 res2[11]; | |
1138 | u16 tmr1; | |
1139 | u16 tmr2; | |
1140 | u16 trr1; | |
1141 | u16 trr2; | |
1142 | u16 tcr1; | |
1143 | u16 tcr2; | |
1144 | u16 tcn1; | |
1145 | u16 tcn2; | |
1146 | u16 tmr3; | |
1147 | u16 tmr4; | |
1148 | u16 trr3; | |
1149 | u16 trr4; | |
1150 | u16 tcr3; | |
1151 | u16 tcr4; | |
1152 | u16 tcn3; | |
1153 | u16 tcn4; | |
1154 | u16 ter1; | |
1155 | u16 ter2; | |
1156 | u16 ter3; | |
1157 | u16 ter4; | |
1158 | u8 res3[608]; | |
42d1f039 WD |
1159 | } ccsr_cpm_timer_t; |
1160 | ||
8280912e | 1161 | /* SDMA */ |
42d1f039 | 1162 | typedef struct ccsr_cpm_sdma { |
8280912e KG |
1163 | u8 sdsr; |
1164 | u8 res1[3]; | |
1165 | u8 sdmr; | |
1166 | u8 res2[739]; | |
42d1f039 WD |
1167 | } ccsr_cpm_sdma_t; |
1168 | ||
8280912e | 1169 | /* FCC1 */ |
42d1f039 | 1170 | typedef struct ccsr_cpm_fcc1 { |
8280912e KG |
1171 | u32 gfmr; |
1172 | u32 fpsmr; | |
1173 | u16 ftodr; | |
1174 | u8 res1[2]; | |
1175 | u16 fdsr; | |
1176 | u8 res2[2]; | |
1177 | u16 fcce; | |
1178 | u8 res3[2]; | |
1179 | u16 fccm; | |
1180 | u8 res4[2]; | |
1181 | u8 fccs; | |
1182 | u8 res5[3]; | |
1183 | u8 ftirr_phy[4]; | |
42d1f039 WD |
1184 | } ccsr_cpm_fcc1_t; |
1185 | ||
8280912e | 1186 | /* FCC2 */ |
42d1f039 | 1187 | typedef struct ccsr_cpm_fcc2 { |
8280912e KG |
1188 | u32 gfmr; |
1189 | u32 fpsmr; | |
1190 | u16 ftodr; | |
1191 | u8 res1[2]; | |
1192 | u16 fdsr; | |
1193 | u8 res2[2]; | |
1194 | u16 fcce; | |
1195 | u8 res3[2]; | |
1196 | u16 fccm; | |
1197 | u8 res4[2]; | |
1198 | u8 fccs; | |
1199 | u8 res5[3]; | |
1200 | u8 ftirr_phy[4]; | |
42d1f039 WD |
1201 | } ccsr_cpm_fcc2_t; |
1202 | ||
8280912e | 1203 | /* FCC3 */ |
42d1f039 | 1204 | typedef struct ccsr_cpm_fcc3 { |
8280912e KG |
1205 | u32 gfmr; |
1206 | u32 fpsmr; | |
1207 | u16 ftodr; | |
1208 | u8 res1[2]; | |
1209 | u16 fdsr; | |
1210 | u8 res2[2]; | |
1211 | u16 fcce; | |
1212 | u8 res3[2]; | |
1213 | u16 fccm; | |
1214 | u8 res4[2]; | |
1215 | u8 fccs; | |
1216 | u8 res5[3]; | |
1217 | u8 res[36]; | |
42d1f039 WD |
1218 | } ccsr_cpm_fcc3_t; |
1219 | ||
8280912e | 1220 | /* FCC1 extended */ |
42d1f039 | 1221 | typedef struct ccsr_cpm_fcc1_ext { |
8280912e KG |
1222 | u32 firper; |
1223 | u32 firer; | |
1224 | u32 firsr_h; | |
1225 | u32 firsr_l; | |
1226 | u8 gfemr; | |
1227 | u8 res[15]; | |
42d1f039 WD |
1228 | |
1229 | } ccsr_cpm_fcc1_ext_t; | |
1230 | ||
8280912e | 1231 | /* FCC2 extended */ |
42d1f039 | 1232 | typedef struct ccsr_cpm_fcc2_ext { |
8280912e KG |
1233 | u32 firper; |
1234 | u32 firer; | |
1235 | u32 firsr_h; | |
1236 | u32 firsr_l; | |
1237 | u8 gfemr; | |
1238 | u8 res[31]; | |
42d1f039 WD |
1239 | } ccsr_cpm_fcc2_ext_t; |
1240 | ||
8280912e | 1241 | /* FCC3 extended */ |
42d1f039 | 1242 | typedef struct ccsr_cpm_fcc3_ext { |
8280912e KG |
1243 | u8 gfemr; |
1244 | u8 res[47]; | |
42d1f039 WD |
1245 | } ccsr_cpm_fcc3_ext_t; |
1246 | ||
8280912e | 1247 | /* TC layers */ |
42d1f039 | 1248 | typedef struct ccsr_cpm_tmp1 { |
8280912e | 1249 | u8 res[496]; |
42d1f039 WD |
1250 | } ccsr_cpm_tmp1_t; |
1251 | ||
8280912e | 1252 | /* BRGs:5,6,7,8 */ |
42d1f039 | 1253 | typedef struct ccsr_cpm_brg2 { |
8280912e KG |
1254 | u32 brgc5; |
1255 | u32 brgc6; | |
1256 | u32 brgc7; | |
1257 | u32 brgc8; | |
1258 | u8 res[608]; | |
42d1f039 WD |
1259 | } ccsr_cpm_brg2_t; |
1260 | ||
8280912e | 1261 | /* I2C */ |
42d1f039 | 1262 | typedef struct ccsr_cpm_i2c { |
8280912e KG |
1263 | u8 i2mod; |
1264 | u8 res1[3]; | |
1265 | u8 i2add; | |
1266 | u8 res2[3]; | |
1267 | u8 i2brg; | |
1268 | u8 res3[3]; | |
1269 | u8 i2com; | |
1270 | u8 res4[3]; | |
1271 | u8 i2cer; | |
1272 | u8 res5[3]; | |
1273 | u8 i2cmr; | |
1274 | u8 res6[331]; | |
42d1f039 WD |
1275 | } ccsr_cpm_i2c_t; |
1276 | ||
8280912e | 1277 | /* CPM core */ |
42d1f039 | 1278 | typedef struct ccsr_cpm_cp { |
8280912e KG |
1279 | u32 cpcr; |
1280 | u32 rccr; | |
1281 | u8 res1[14]; | |
1282 | u16 rter; | |
1283 | u8 res2[2]; | |
1284 | u16 rtmr; | |
1285 | u16 rtscr; | |
1286 | u8 res3[2]; | |
1287 | u32 rtsr; | |
1288 | u8 res4[12]; | |
42d1f039 WD |
1289 | } ccsr_cpm_cp_t; |
1290 | ||
8280912e | 1291 | /* BRGs:1,2,3,4 */ |
42d1f039 | 1292 | typedef struct ccsr_cpm_brg1 { |
8280912e KG |
1293 | u32 brgc1; |
1294 | u32 brgc2; | |
1295 | u32 brgc3; | |
1296 | u32 brgc4; | |
42d1f039 WD |
1297 | } ccsr_cpm_brg1_t; |
1298 | ||
8280912e | 1299 | /* SCC1-SCC4 */ |
42d1f039 | 1300 | typedef struct ccsr_cpm_scc { |
8280912e KG |
1301 | u32 gsmrl; |
1302 | u32 gsmrh; | |
1303 | u16 psmr; | |
1304 | u8 res1[2]; | |
1305 | u16 todr; | |
1306 | u16 dsr; | |
1307 | u16 scce; | |
1308 | u8 res2[2]; | |
1309 | u16 sccm; | |
1310 | u8 res3; | |
1311 | u8 sccs; | |
1312 | u8 res4[8]; | |
42d1f039 WD |
1313 | } ccsr_cpm_scc_t; |
1314 | ||
42d1f039 | 1315 | typedef struct ccsr_cpm_tmp2 { |
8280912e | 1316 | u8 res[32]; |
42d1f039 WD |
1317 | } ccsr_cpm_tmp2_t; |
1318 | ||
8280912e | 1319 | /* SPI */ |
42d1f039 | 1320 | typedef struct ccsr_cpm_spi { |
8280912e KG |
1321 | u16 spmode; |
1322 | u8 res1[4]; | |
1323 | u8 spie; | |
1324 | u8 res2[3]; | |
1325 | u8 spim; | |
1326 | u8 res3[2]; | |
1327 | u8 spcom; | |
1328 | u8 res4[82]; | |
42d1f039 WD |
1329 | } ccsr_cpm_spi_t; |
1330 | ||
8280912e | 1331 | /* CPM MUX */ |
42d1f039 | 1332 | typedef struct ccsr_cpm_mux { |
8280912e KG |
1333 | u8 cmxsi1cr; |
1334 | u8 res1; | |
1335 | u8 cmxsi2cr; | |
1336 | u8 res2; | |
1337 | u32 cmxfcr; | |
1338 | u32 cmxscr; | |
1339 | u8 res3[2]; | |
1340 | u16 cmxuar; | |
1341 | u8 res4[16]; | |
42d1f039 WD |
1342 | } ccsr_cpm_mux_t; |
1343 | ||
8280912e | 1344 | /* SI,MCC,etc */ |
42d1f039 | 1345 | typedef struct ccsr_cpm_tmp3 { |
8280912e | 1346 | u8 res[58592]; |
42d1f039 WD |
1347 | } ccsr_cpm_tmp3_t; |
1348 | ||
1349 | typedef struct ccsr_cpm_iram { | |
8280912e KG |
1350 | u32 iram[8192]; |
1351 | u8 res[98304]; | |
42d1f039 WD |
1352 | } ccsr_cpm_iram_t; |
1353 | ||
1354 | typedef struct ccsr_cpm { | |
8280912e | 1355 | /* Some references are into the unique & known dpram spaces, |
42d1f039 WD |
1356 | * others are from the generic base. |
1357 | */ | |
53677ef1 | 1358 | #define im_dprambase im_dpram1 |
8280912e KG |
1359 | u8 im_dpram1[16*1024]; |
1360 | u8 res1[16*1024]; | |
1361 | u8 im_dpram2[16*1024]; | |
1362 | u8 res2[16*1024]; | |
1363 | ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */ | |
1364 | ccsr_cpm_intctl_t im_cpm_intctl; /* IRQ Controller */ | |
1365 | ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */ | |
1366 | ccsr_cpm_timer_t im_cpm_timer; /* CPM timers */ | |
1367 | ccsr_cpm_sdma_t im_cpm_sdma; /* SDMA control/status */ | |
42d1f039 WD |
1368 | ccsr_cpm_fcc1_t im_cpm_fcc1; |
1369 | ccsr_cpm_fcc2_t im_cpm_fcc2; | |
1370 | ccsr_cpm_fcc3_t im_cpm_fcc3; | |
1371 | ccsr_cpm_fcc1_ext_t im_cpm_fcc1_ext; | |
1372 | ccsr_cpm_fcc2_ext_t im_cpm_fcc2_ext; | |
1373 | ccsr_cpm_fcc3_ext_t im_cpm_fcc3_ext; | |
1374 | ccsr_cpm_tmp1_t im_cpm_tmp1; | |
1375 | ccsr_cpm_brg2_t im_cpm_brg2; | |
1376 | ccsr_cpm_i2c_t im_cpm_i2c; | |
1377 | ccsr_cpm_cp_t im_cpm_cp; | |
1378 | ccsr_cpm_brg1_t im_cpm_brg1; | |
1379 | ccsr_cpm_scc_t im_cpm_scc[4]; | |
1380 | ccsr_cpm_tmp2_t im_cpm_tmp2; | |
1381 | ccsr_cpm_spi_t im_cpm_spi; | |
1382 | ccsr_cpm_mux_t im_cpm_mux; | |
1383 | ccsr_cpm_tmp3_t im_cpm_tmp3; | |
1384 | ccsr_cpm_iram_t im_cpm_iram; | |
1385 | } ccsr_cpm_t; | |
1386 | #endif | |
42d1f039 | 1387 | |
8280912e | 1388 | /* RapidIO Registers */ |
42d1f039 | 1389 | typedef struct ccsr_rio { |
8280912e KG |
1390 | u32 didcar; /* Device Identity Capability */ |
1391 | u32 dicar; /* Device Information Capability */ | |
1392 | u32 aidcar; /* Assembly Identity Capability */ | |
1393 | u32 aicar; /* Assembly Information Capability */ | |
1394 | u32 pefcar; /* Processing Element Features Capability */ | |
1395 | u32 spicar; /* Switch Port Information Capability */ | |
1396 | u32 socar; /* Source Operations Capability */ | |
1397 | u32 docar; /* Destination Operations Capability */ | |
1398 | u8 res1[32]; | |
1399 | u32 msr; /* Mailbox Cmd And Status */ | |
1400 | u32 pwdcsr; /* Port-Write & Doorbell Cmd And Status */ | |
1401 | u8 res2[4]; | |
1402 | u32 pellccsr; /* Processing Element Logic Layer CCSR */ | |
1403 | u8 res3[12]; | |
1404 | u32 lcsbacsr; /* Local Cfg Space Base Addr Cmd & Status */ | |
1405 | u32 bdidcsr; /* Base Device ID Cmd & Status */ | |
1406 | u8 res4[4]; | |
1407 | u32 hbdidlcsr; /* Host Base Device ID Lock Cmd & Status */ | |
1408 | u32 ctcsr; /* Component Tag Cmd & Status */ | |
1409 | u8 res5[144]; | |
1410 | u32 pmbh0csr; /* Port Maint. Block Hdr 0 Cmd & Status */ | |
1411 | u8 res6[28]; | |
1412 | u32 pltoccsr; /* Port Link Time-out Ctrl Cmd & Status */ | |
1413 | u32 prtoccsr; /* Port Response Time-out Ctrl Cmd & Status */ | |
1414 | u8 res7[20]; | |
1415 | u32 pgccsr; /* Port General Cmd & Status */ | |
1416 | u32 plmreqcsr; /* Port Link Maint. Request Cmd & Status */ | |
1417 | u32 plmrespcsr; /* Port Link Maint. Response Cmd & Status */ | |
1418 | u32 plascsr; /* Port Local Ackid Status Cmd & Status */ | |
1419 | u8 res8[12]; | |
1420 | u32 pescsr; /* Port Error & Status Cmd & Status */ | |
1421 | u32 pccsr; /* Port Control Cmd & Status */ | |
1422 | u8 res9[65184]; | |
1423 | u32 cr; /* Port Control Cmd & Status */ | |
1424 | u8 res10[12]; | |
1425 | u32 pcr; /* Port Configuration */ | |
1426 | u32 peir; /* Port Error Injection */ | |
1427 | u8 res11[3048]; | |
1428 | u32 rowtar0; /* RIO Outbound Window Translation Addr 0 */ | |
1429 | u8 res12[12]; | |
1430 | u32 rowar0; /* RIO Outbound Attrs 0 */ | |
1431 | u8 res13[12]; | |
1432 | u32 rowtar1; /* RIO Outbound Window Translation Addr 1 */ | |
1433 | u8 res14[4]; | |
1434 | u32 rowbar1; /* RIO Outbound Window Base Addr 1 */ | |
1435 | u8 res15[4]; | |
1436 | u32 rowar1; /* RIO Outbound Attrs 1 */ | |
1437 | u8 res16[12]; | |
1438 | u32 rowtar2; /* RIO Outbound Window Translation Addr 2 */ | |
1439 | u8 res17[4]; | |
1440 | u32 rowbar2; /* RIO Outbound Window Base Addr 2 */ | |
1441 | u8 res18[4]; | |
1442 | u32 rowar2; /* RIO Outbound Attrs 2 */ | |
1443 | u8 res19[12]; | |
1444 | u32 rowtar3; /* RIO Outbound Window Translation Addr 3 */ | |
1445 | u8 res20[4]; | |
1446 | u32 rowbar3; /* RIO Outbound Window Base Addr 3 */ | |
1447 | u8 res21[4]; | |
1448 | u32 rowar3; /* RIO Outbound Attrs 3 */ | |
1449 | u8 res22[12]; | |
1450 | u32 rowtar4; /* RIO Outbound Window Translation Addr 4 */ | |
1451 | u8 res23[4]; | |
1452 | u32 rowbar4; /* RIO Outbound Window Base Addr 4 */ | |
1453 | u8 res24[4]; | |
1454 | u32 rowar4; /* RIO Outbound Attrs 4 */ | |
1455 | u8 res25[12]; | |
1456 | u32 rowtar5; /* RIO Outbound Window Translation Addr 5 */ | |
1457 | u8 res26[4]; | |
1458 | u32 rowbar5; /* RIO Outbound Window Base Addr 5 */ | |
1459 | u8 res27[4]; | |
1460 | u32 rowar5; /* RIO Outbound Attrs 5 */ | |
1461 | u8 res28[12]; | |
1462 | u32 rowtar6; /* RIO Outbound Window Translation Addr 6 */ | |
1463 | u8 res29[4]; | |
1464 | u32 rowbar6; /* RIO Outbound Window Base Addr 6 */ | |
1465 | u8 res30[4]; | |
1466 | u32 rowar6; /* RIO Outbound Attrs 6 */ | |
1467 | u8 res31[12]; | |
1468 | u32 rowtar7; /* RIO Outbound Window Translation Addr 7 */ | |
1469 | u8 res32[4]; | |
1470 | u32 rowbar7; /* RIO Outbound Window Base Addr 7 */ | |
1471 | u8 res33[4]; | |
1472 | u32 rowar7; /* RIO Outbound Attrs 7 */ | |
1473 | u8 res34[12]; | |
1474 | u32 rowtar8; /* RIO Outbound Window Translation Addr 8 */ | |
1475 | u8 res35[4]; | |
1476 | u32 rowbar8; /* RIO Outbound Window Base Addr 8 */ | |
1477 | u8 res36[4]; | |
1478 | u32 rowar8; /* RIO Outbound Attrs 8 */ | |
1479 | u8 res37[76]; | |
1480 | u32 riwtar4; /* RIO Inbound Window Translation Addr 4 */ | |
1481 | u8 res38[4]; | |
1482 | u32 riwbar4; /* RIO Inbound Window Base Addr 4 */ | |
1483 | u8 res39[4]; | |
1484 | u32 riwar4; /* RIO Inbound Attrs 4 */ | |
1485 | u8 res40[12]; | |
1486 | u32 riwtar3; /* RIO Inbound Window Translation Addr 3 */ | |
1487 | u8 res41[4]; | |
1488 | u32 riwbar3; /* RIO Inbound Window Base Addr 3 */ | |
1489 | u8 res42[4]; | |
1490 | u32 riwar3; /* RIO Inbound Attrs 3 */ | |
1491 | u8 res43[12]; | |
1492 | u32 riwtar2; /* RIO Inbound Window Translation Addr 2 */ | |
1493 | u8 res44[4]; | |
1494 | u32 riwbar2; /* RIO Inbound Window Base Addr 2 */ | |
1495 | u8 res45[4]; | |
1496 | u32 riwar2; /* RIO Inbound Attrs 2 */ | |
1497 | u8 res46[12]; | |
1498 | u32 riwtar1; /* RIO Inbound Window Translation Addr 1 */ | |
1499 | u8 res47[4]; | |
1500 | u32 riwbar1; /* RIO Inbound Window Base Addr 1 */ | |
1501 | u8 res48[4]; | |
1502 | u32 riwar1; /* RIO Inbound Attrs 1 */ | |
1503 | u8 res49[12]; | |
1504 | u32 riwtar0; /* RIO Inbound Window Translation Addr 0 */ | |
1505 | u8 res50[12]; | |
1506 | u32 riwar0; /* RIO Inbound Attrs 0 */ | |
1507 | u8 res51[12]; | |
1508 | u32 pnfedr; /* Port Notification/Fatal Error Detect */ | |
1509 | u32 pnfedir; /* Port Notification/Fatal Error Detect */ | |
1510 | u32 pnfeier; /* Port Notification/Fatal Error IRQ Enable */ | |
1511 | u32 pecr; /* Port Error Control */ | |
1512 | u32 pepcsr0; /* Port Error Packet/Control Symbol 0 */ | |
1513 | u32 pepr1; /* Port Error Packet 1 */ | |
1514 | u32 pepr2; /* Port Error Packet 2 */ | |
1515 | u8 res52[4]; | |
1516 | u32 predr; /* Port Recoverable Error Detect */ | |
1517 | u8 res53[4]; | |
1518 | u32 pertr; /* Port Error Recovery Threshold */ | |
1519 | u32 prtr; /* Port Retry Threshold */ | |
1520 | u8 res54[464]; | |
1521 | u32 omr; /* Outbound Mode */ | |
1522 | u32 osr; /* Outbound Status */ | |
1523 | u32 eodqtpar; /* Extended Outbound Desc Queue Tail Ptr Addr */ | |
1524 | u32 odqtpar; /* Outbound Desc Queue Tail Ptr Addr */ | |
1525 | u32 eosar; /* Extended Outbound Unit Source Addr */ | |
1526 | u32 osar; /* Outbound Unit Source Addr */ | |
1527 | u32 odpr; /* Outbound Destination Port */ | |
1528 | u32 odatr; /* Outbound Destination Attrs */ | |
1529 | u32 odcr; /* Outbound Doubleword Count */ | |
1530 | u32 eodqhpar; /* Extended Outbound Desc Queue Head Ptr Addr */ | |
1531 | u32 odqhpar; /* Outbound Desc Queue Head Ptr Addr */ | |
1532 | u8 res55[52]; | |
1533 | u32 imr; /* Outbound Mode */ | |
1534 | u32 isr; /* Inbound Status */ | |
1535 | u32 eidqtpar; /* Extended Inbound Desc Queue Tail Ptr Addr */ | |
1536 | u32 idqtpar; /* Inbound Desc Queue Tail Ptr Addr */ | |
1537 | u32 eifqhpar; /* Extended Inbound Frame Queue Head Ptr Addr */ | |
1538 | u32 ifqhpar; /* Inbound Frame Queue Head Ptr Addr */ | |
1539 | u8 res56[1000]; | |
1540 | u32 dmr; /* Doorbell Mode */ | |
1541 | u32 dsr; /* Doorbell Status */ | |
1542 | u32 edqtpar; /* Extended Doorbell Queue Tail Ptr Addr */ | |
1543 | u32 dqtpar; /* Doorbell Queue Tail Ptr Addr */ | |
1544 | u32 edqhpar; /* Extended Doorbell Queue Head Ptr Addr */ | |
1545 | u32 dqhpar; /* Doorbell Queue Head Ptr Addr */ | |
1546 | u8 res57[104]; | |
1547 | u32 pwmr; /* Port-Write Mode */ | |
1548 | u32 pwsr; /* Port-Write Status */ | |
1549 | u32 epwqbar; /* Extended Port-Write Queue Base Addr */ | |
1550 | u32 pwqbar; /* Port-Write Queue Base Addr */ | |
1551 | u8 res58[60176]; | |
42d1f039 WD |
1552 | } ccsr_rio_t; |
1553 | ||
8280912e | 1554 | /* Quick Engine Block Pin Muxing Registers */ |
c59e4091 | 1555 | typedef struct par_io { |
8280912e KG |
1556 | u32 cpodr; |
1557 | u32 cpdat; | |
1558 | u32 cpdir1; | |
1559 | u32 cpdir2; | |
1560 | u32 cppar1; | |
1561 | u32 cppar2; | |
1562 | u8 res[8]; | |
1563 | } par_io_t; | |
c59e4091 | 1564 | |
8b0ab304 BB |
1565 | #ifdef CONFIG_SYS_FSL_CPC |
1566 | /* | |
1567 | * Define a single offset that is the start of all the CPC register | |
1568 | * blocks - if there is more than one CPC, we expect these to be | |
1569 | * contiguous 4k regions | |
1570 | */ | |
1571 | ||
1572 | typedef struct cpc_corenet { | |
1573 | u32 cpccsr0; /* Config/status reg */ | |
1574 | u32 res1; | |
1575 | u32 cpccfg0; /* Configuration register */ | |
1576 | u32 res2; | |
1577 | u32 cpcewcr0; /* External Write reg 0 */ | |
1578 | u32 cpcewabr0; /* External write base reg 0 */ | |
1579 | u32 res3[2]; | |
1580 | u32 cpcewcr1; /* External Write reg 1 */ | |
1581 | u32 cpcewabr1; /* External write base reg 1 */ | |
1582 | u32 res4[54]; | |
1583 | u32 cpcsrcr1; /* SRAM control reg 1 */ | |
1584 | u32 cpcsrcr0; /* SRAM control reg 0 */ | |
1585 | u32 res5[62]; | |
1586 | struct { | |
1587 | u32 id; /* partition ID */ | |
1588 | u32 res; | |
1589 | u32 alloc; /* partition allocation */ | |
1590 | u32 way; /* partition way */ | |
1591 | } partition_regs[16]; | |
1592 | u32 res6[704]; | |
1593 | u32 cpcerrinjhi; /* Error injection high */ | |
1594 | u32 cpcerrinjlo; /* Error injection lo */ | |
1595 | u32 cpcerrinjctl; /* Error injection control */ | |
1596 | u32 res7[5]; | |
1597 | u32 cpccaptdatahi; /* capture data high */ | |
1598 | u32 cpccaptdatalo; /* capture data low */ | |
1599 | u32 cpcaptecc; /* capture ECC */ | |
1600 | u32 res8[5]; | |
1601 | u32 cpcerrdet; /* error detect */ | |
1602 | u32 cpcerrdis; /* error disable */ | |
1603 | u32 cpcerrinten; /* errir interrupt enable */ | |
1604 | u32 cpcerrattr; /* error attribute */ | |
1605 | u32 cpcerreaddr; /* error extended address */ | |
1606 | u32 cpcerraddr; /* error address */ | |
1607 | u32 cpcerrctl; /* error control */ | |
1608 | u32 res9[105]; /* pad out to 4k */ | |
1609 | } cpc_corenet_t; | |
1610 | ||
1611 | #define CPC_CSR0_CE 0x80000000 /* Cache Enable */ | |
1612 | #define CPC_CSR0_PE 0x40000000 /* Enable ECC */ | |
1613 | #define CPC_CSR0_FI 0x00200000 /* Cache Flash Invalidate */ | |
1614 | #define CPC_CSR0_WT 0x00080000 /* Write-through mode */ | |
1615 | #define CPC_CSR0_FL 0x00000800 /* Hardware cache flush */ | |
1616 | #define CPC_CSR0_LFC 0x00000400 /* Cache Lock Flash Clear */ | |
1617 | #define CPC_CFG0_SZ_MASK 0x00003fff | |
1618 | #define CPC_CFG0_SZ_K(x) ((x & CPC_CFG0_SZ_MASK) << 6) | |
1619 | #define CPC_CFG0_NUM_WAYS(x) (((x >> 14) & 0x1f) + 1) | |
1620 | #define CPC_CFG0_LINE_SZ(x) ((((x >> 23) & 0x3) + 1) * 32) | |
1621 | #define CPC_SRCR1_SRBARU_MASK 0x0000ffff | |
1622 | #define CPC_SRCR1_SRBARU(x) (((unsigned long long)x >> 32) \ | |
1623 | & CPC_SRCR1_SRBARU_MASK) | |
1624 | #define CPC_SRCR0_SRBARL_MASK 0xffff8000 | |
1625 | #define CPC_SRCR0_SRBARL(x) (x & CPC_SRCR0_SRBARL_MASK) | |
1626 | #define CPC_SRCR0_INTLVEN 0x00000100 | |
1627 | #define CPC_SRCR0_SRAMSZ_1_WAY 0x00000000 | |
1628 | #define CPC_SRCR0_SRAMSZ_2_WAY 0x00000002 | |
1629 | #define CPC_SRCR0_SRAMSZ_4_WAY 0x00000004 | |
1630 | #define CPC_SRCR0_SRAMSZ_8_WAY 0x00000006 | |
1631 | #define CPC_SRCR0_SRAMSZ_16_WAY 0x00000008 | |
1632 | #define CPC_SRCR0_SRAMSZ_32_WAY 0x0000000a | |
1633 | #define CPC_SRCR0_SRAMEN 0x00000001 | |
1634 | #define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */ | |
1635 | #endif /* CONFIG_SYS_FSL_CPC */ | |
1636 | ||
8280912e | 1637 | /* Global Utilities Block */ |
01df5212 KG |
1638 | #ifdef CONFIG_FSL_CORENET |
1639 | typedef struct ccsr_gur { | |
8280912e KG |
1640 | u32 porsr1; /* POR status */ |
1641 | u8 res1[28]; | |
1642 | u32 gpporcr1; /* General-purpose POR configuration */ | |
01df5212 | 1643 | u8 res2[12]; |
8280912e | 1644 | u32 gpiocr; /* GPIO control */ |
01df5212 | 1645 | u8 res3[12]; |
8280912e | 1646 | u32 gpoutdr; /* General-purpose output data */ |
01df5212 | 1647 | u8 res4[12]; |
8280912e | 1648 | u32 gpindr; /* General-purpose input data */ |
01df5212 | 1649 | u8 res5[12]; |
8280912e | 1650 | u32 pmuxcr; /* Alt function signal multiplex control */ |
01df5212 | 1651 | u8 res6[12]; |
8280912e | 1652 | u32 devdisr; /* Device disable control */ |
01df5212 KG |
1653 | #define FSL_CORENET_DEVDISR_PCIE1 0x80000000 |
1654 | #define FSL_CORENET_DEVDISR_PCIE2 0x40000000 | |
1655 | #define FSL_CORENET_DEVDISR_PCIE3 0x20000000 | |
1656 | #define FSL_CORENET_DEVDISR_RMU 0x08000000 | |
1657 | #define FSL_CORENET_DEVDISR_SRIO1 0x04000000 | |
1658 | #define FSL_CORENET_DEVDISR_SRIO2 0x02000000 | |
1659 | #define FSL_CORENET_DEVDISR_DMA1 0x00400000 | |
1660 | #define FSL_CORENET_DEVDISR_DMA2 0x00200000 | |
1661 | #define FSL_CORENET_DEVDISR_DDR1 0x00100000 | |
1662 | #define FSL_CORENET_DEVDISR_DDR2 0x00080000 | |
1663 | #define FSL_CORENET_DEVDISR_DBG 0x00010000 | |
1664 | #define FSL_CORENET_DEVDISR_NAL 0x00008000 | |
1665 | #define FSL_CORENET_DEVDISR_ELBC 0x00001000 | |
1666 | #define FSL_CORENET_DEVDISR_USB1 0x00000800 | |
1667 | #define FSL_CORENET_DEVDISR_USB2 0x00000400 | |
1668 | #define FSL_CORENET_DEVDISR_ESDHC 0x00000100 | |
1669 | #define FSL_CORENET_DEVDISR_GPIO 0x00000080 | |
1670 | #define FSL_CORENET_DEVDISR_ESPI 0x00000040 | |
1671 | #define FSL_CORENET_DEVDISR_I2C1 0x00000020 | |
1672 | #define FSL_CORENET_DEVDISR_I2C2 0x00000010 | |
1673 | #define FSL_CORENET_DEVDISR_DUART1 0x00000002 | |
1674 | #define FSL_CORENET_DEVDISR_DUART2 0x00000001 | |
1675 | u8 res7[12]; | |
8280912e | 1676 | u32 powmgtcsr; /* Power management status & control */ |
01df5212 | 1677 | u8 res8[12]; |
8280912e KG |
1678 | u32 coredisru; /* uppper portion for support of 64 cores */ |
1679 | u32 coredisrl; /* lower portion for support of 64 cores */ | |
01df5212 | 1680 | u8 res9[8]; |
8280912e KG |
1681 | u32 pvr; /* Processor version */ |
1682 | u32 svr; /* System version */ | |
01df5212 | 1683 | u8 res10[8]; |
8280912e KG |
1684 | u32 rstcr; /* Reset control */ |
1685 | u32 rstrqpblsr; /* Reset request preboot loader status */ | |
01df5212 | 1686 | u8 res11[8]; |
8280912e KG |
1687 | u32 rstrqmr1; /* Reset request mask */ |
1688 | u8 res12[4]; | |
1689 | u32 rstrqsr1; /* Reset request status */ | |
1690 | u8 res13[4]; | |
1691 | u8 res14[4]; | |
1692 | u32 rstrqwdtmrl; /* Reset request WDT mask */ | |
1693 | u8 res15[4]; | |
1694 | u32 rstrqwdtsrl; /* Reset request WDT status */ | |
1695 | u8 res16[4]; | |
1696 | u32 brrl; /* Boot release */ | |
01df5212 | 1697 | u8 res17[24]; |
8280912e | 1698 | u32 rcwsr[16]; /* Reset control word status */ |
01df5212 KG |
1699 | #define FSL_CORENET_RCWSR4_SRDS_PRTCL 0xfc000000 |
1700 | #define FSL_CORENET_RCWSR5_DDR_SYNC 0x00008000 | |
1701 | #define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 15 | |
1702 | #define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x00400000 | |
1703 | #define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000 | |
1704 | #define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000 | |
8280912e KG |
1705 | u8 res18[192]; |
1706 | u32 scratchrw[4]; /* Scratch Read/Write */ | |
1707 | u8 res19[240]; | |
1708 | u32 scratchw1r[4]; /* Scratch Read (Write once) */ | |
1709 | u8 res20[240]; | |
1710 | u32 scrtsr[8]; /* Core reset status */ | |
1711 | u8 res21[224]; | |
1712 | u32 pex1liodnr; /* PCI Express 1 LIODN */ | |
1713 | u32 pex2liodnr; /* PCI Express 2 LIODN */ | |
1714 | u32 pex3liodnr; /* PCI Express 3 LIODN */ | |
1715 | u32 pex4liodnr; /* PCI Express 4 LIODN */ | |
1716 | u32 rio1liodnr; /* RIO 1 LIODN */ | |
1717 | u32 rio2liodnr; /* RIO 2 LIODN */ | |
1718 | u32 rio3liodnr; /* RIO 3 LIODN */ | |
1719 | u32 rio4liodnr; /* RIO 4 LIODN */ | |
1720 | u32 usb1liodnr; /* USB 1 LIODN */ | |
1721 | u32 usb2liodnr; /* USB 2 LIODN */ | |
1722 | u32 usb3liodnr; /* USB 3 LIODN */ | |
1723 | u32 usb4liodnr; /* USB 4 LIODN */ | |
1724 | u32 sdmmc1liodnr; /* SD/MMC 1 LIODN */ | |
1725 | u32 sdmmc2liodnr; /* SD/MMC 2 LIODN */ | |
1726 | u32 sdmmc3liodnr; /* SD/MMC 3 LIODN */ | |
1727 | u32 sdmmc4liodnr; /* SD/MMC 4 LIODN */ | |
1728 | u32 rmuliodnr; /* RIO Message Unit LIODN */ | |
1729 | u32 rduliodnr; /* RIO Doorbell Unit LIODN */ | |
1730 | u32 rpwuliodnr; /* RIO Port Write Unit LIODN */ | |
1731 | u8 res22[52]; | |
1732 | u32 dma1liodnr; /* DMA 1 LIODN */ | |
1733 | u32 dma2liodnr; /* DMA 2 LIODN */ | |
1734 | u32 dma3liodnr; /* DMA 3 LIODN */ | |
1735 | u32 dma4liodnr; /* DMA 4 LIODN */ | |
1736 | u8 res23[48]; | |
1737 | u8 res24[64]; | |
1738 | u32 pblsr; /* Preboot loader status */ | |
1739 | u32 pamubypenr; /* PAMU bypass enable */ | |
1740 | u32 dmacr1; /* DMA control */ | |
1741 | u8 res25[4]; | |
1742 | u32 gensr1; /* General status */ | |
1743 | u8 res26[12]; | |
1744 | u32 gencr1; /* General control */ | |
1745 | u8 res27[12]; | |
1746 | u8 res28[4]; | |
1747 | u32 cgensrl; /* Core general status */ | |
1748 | u8 res29[8]; | |
1749 | u8 res30[4]; | |
1750 | u32 cgencrl; /* Core general control */ | |
1751 | u8 res31[184]; | |
1752 | u32 sriopstecr; /* SRIO prescaler timer enable control */ | |
1753 | u8 res32[2300]; | |
01df5212 KG |
1754 | } ccsr_gur_t; |
1755 | ||
1756 | typedef struct ccsr_clk { | |
8280912e KG |
1757 | u32 clkc0csr; /* Core 0 Clock control/status */ |
1758 | u8 res1[0x1c]; | |
1759 | u32 clkc1csr; /* Core 1 Clock control/status */ | |
1760 | u8 res2[0x1c]; | |
1761 | u32 clkc2csr; /* Core 2 Clock control/status */ | |
1762 | u8 res3[0x1c]; | |
1763 | u32 clkc3csr; /* Core 3 Clock control/status */ | |
1764 | u8 res4[0x1c]; | |
1765 | u32 clkc4csr; /* Core 4 Clock control/status */ | |
1766 | u8 res5[0x1c]; | |
1767 | u32 clkc5csr; /* Core 5 Clock control/status */ | |
1768 | u8 res6[0x1c]; | |
1769 | u32 clkc6csr; /* Core 6 Clock control/status */ | |
1770 | u8 res7[0x1c]; | |
1771 | u32 clkc7csr; /* Core 7 Clock control/status */ | |
1772 | u8 res8[0x71c]; | |
1773 | u32 pllc1gsr; /* Cluster PLL 1 General Status */ | |
1774 | u8 res10[0x1c]; | |
1775 | u32 pllc2gsr; /* Cluster PLL 2 General Status */ | |
1776 | u8 res11[0x1c]; | |
1777 | u32 pllc3gsr; /* Cluster PLL 3 General Status */ | |
1778 | u8 res12[0x1c]; | |
1779 | u32 pllc4gsr; /* Cluster PLL 4 General Status */ | |
1780 | u8 res13[0x39c]; | |
1781 | u32 pllpgsr; /* Platform PLL General Status */ | |
1782 | u8 res14[0x1c]; | |
1783 | u32 plldgsr; /* DDR PLL General Status */ | |
1784 | u8 res15[0x3dc]; | |
01df5212 KG |
1785 | } ccsr_clk_t; |
1786 | ||
1787 | typedef struct ccsr_rcpm { | |
8280912e KG |
1788 | u8 res1[4]; |
1789 | u32 cdozsrl; /* Core Doze Status */ | |
1790 | u8 res2[4]; | |
1791 | u32 cdozcrl; /* Core Doze Control */ | |
1792 | u8 res3[4]; | |
1793 | u32 cnapsrl; /* Core Nap Status */ | |
1794 | u8 res4[4]; | |
1795 | u32 cnapcrl; /* Core Nap Control */ | |
1796 | u8 res5[4]; | |
1797 | u32 cdozpsrl; /* Core Doze Previous Status */ | |
1798 | u8 res6[4]; | |
1799 | u32 cdozpcrl; /* Core Doze Previous Control */ | |
1800 | u8 res7[4]; | |
1801 | u32 cwaitsrl; /* Core Wait Status */ | |
1802 | u8 res8[8]; | |
1803 | u32 powmgtcsr; /* Power Mangement Control & Status */ | |
1804 | u8 res9[12]; | |
1805 | u32 ippdexpcr0; /* IP Powerdown Exception Control 0 */ | |
1806 | u8 res10[12]; | |
1807 | u8 res11[4]; | |
1808 | u32 cpmimrl; /* Core PM IRQ Masking */ | |
1809 | u8 res12[4]; | |
1810 | u32 cpmcimrl; /* Core PM Critical IRQ Masking */ | |
1811 | u8 res13[4]; | |
1812 | u32 cpmmcimrl; /* Core PM Machine Check IRQ Masking */ | |
1813 | u8 res14[4]; | |
1814 | u32 cpmnmimrl; /* Core PM NMI Masking */ | |
1815 | u8 res15[4]; | |
1816 | u32 ctbenrl; /* Core Time Base Enable */ | |
1817 | u8 res16[4]; | |
1818 | u32 ctbclkselrl; /* Core Time Base Clock Select */ | |
1819 | u8 res17[4]; | |
1820 | u32 ctbhltcrl; /* Core Time Base Halt Control */ | |
01df5212 KG |
1821 | u8 res18[0xf68]; |
1822 | } ccsr_rcpm_t; | |
1823 | ||
1824 | #else | |
42d1f039 | 1825 | typedef struct ccsr_gur { |
8280912e | 1826 | u32 porpllsr; /* POR PLL ratio status */ |
c0391111 JJ |
1827 | #ifdef CONFIG_MPC8536 |
1828 | #define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000 | |
1829 | #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25 | |
1830 | #else | |
1831 | #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00 | |
1832 | #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9 | |
1833 | #endif | |
b3d7f20f HW |
1834 | #define MPC85xx_PORPLLSR_QE_RATIO 0x3e000000 |
1835 | #define MPC85xx_PORPLLSR_QE_RATIO_SHIFT 25 | |
266139b8 | 1836 | #define MPC85xx_PORPLLSR_PLAT_RATIO 0x0000003e |
8280912e KG |
1837 | #define MPC85xx_PORPLLSR_PLAT_RATIO_SHIFT 1 |
1838 | u32 porbmsr; /* POR boot mode status */ | |
53677ef1 | 1839 | #define MPC85xx_PORBMSR_HA 0x00070000 |
6442b71b | 1840 | #define MPC85xx_PORBMSR_HA_SHIFT 16 |
8280912e KG |
1841 | u32 porimpscr; /* POR I/O impedance status & control */ |
1842 | u32 pordevsr; /* POR I/O device status regsiter */ | |
837f1ba0 ES |
1843 | #define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000 |
1844 | #define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000 | |
1845 | #define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000 | |
1846 | #define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000 | |
8280912e | 1847 | #define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000 |
9427ccde | 1848 | #define MPC85xx_PORDEVSR_PCI1 0x00800000 |
4442f45b | 1849 | #define MPC85xx_PORDEVSR_IO_SEL 0x00780000 |
6442b71b | 1850 | #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19 |
53677ef1 WD |
1851 | #define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000 |
1852 | #define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000 | |
1853 | #define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000 | |
1854 | #define MPC85xx_PORDEVSR_PCI1_SPD 0x00008000 | |
1855 | #define MPC85xx_PORDEVSR_PCI2_SPD 0x00004000 | |
837f1ba0 | 1856 | #define MPC85xx_PORDEVSR_DRAM_RTYPE 0x00000060 |
53677ef1 | 1857 | #define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008 |
837f1ba0 | 1858 | #define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007 |
8280912e KG |
1859 | u32 pordbgmsr; /* POR debug mode status */ |
1860 | u32 pordevsr2; /* POR I/O device status 2 */ | |
681c02d0 | 1861 | /* The 8544 RM says this is bit 26, but it's really bit 24 */ |
f7d190b1 | 1862 | #define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080 |
8280912e KG |
1863 | u8 res1[8]; |
1864 | u32 gpporcr; /* General-purpose POR configuration */ | |
1865 | u8 res2[12]; | |
1866 | u32 gpiocr; /* GPIO control */ | |
1867 | u8 res3[12]; | |
22b6dbc1 | 1868 | #if defined(CONFIG_MPC8569) |
8280912e KG |
1869 | u32 plppar1; /* Platform port pin assignment 1 */ |
1870 | u32 plppar2; /* Platform port pin assignment 2 */ | |
1871 | u32 plpdir1; /* Platform port pin direction 1 */ | |
1872 | u32 plpdir2; /* Platform port pin direction 2 */ | |
22b6dbc1 | 1873 | #else |
8280912e KG |
1874 | u32 gpoutdr; /* General-purpose output data */ |
1875 | u8 res4[12]; | |
22b6dbc1 | 1876 | #endif |
8280912e KG |
1877 | u32 gpindr; /* General-purpose input data */ |
1878 | u8 res5[12]; | |
1879 | u32 pmuxcr; /* Alt. function signal multiplex control */ | |
80522dc8 AF |
1880 | #define MPC85xx_PMUXCR_SD_DATA 0x80000000 |
1881 | #define MPC85xx_PMUXCR_SDHC_CD 0x40000000 | |
1882 | #define MPC85xx_PMUXCR_SDHC_WP 0x20000000 | |
8280912e KG |
1883 | u8 res6[12]; |
1884 | u32 devdisr; /* Device disable control */ | |
837f1ba0 ES |
1885 | #define MPC85xx_DEVDISR_PCI1 0x80000000 |
1886 | #define MPC85xx_DEVDISR_PCI2 0x40000000 | |
1887 | #define MPC85xx_DEVDISR_PCIE 0x20000000 | |
1888 | #define MPC85xx_DEVDISR_LBC 0x08000000 | |
1889 | #define MPC85xx_DEVDISR_PCIE2 0x04000000 | |
1890 | #define MPC85xx_DEVDISR_PCIE3 0x02000000 | |
1891 | #define MPC85xx_DEVDISR_SEC 0x01000000 | |
1892 | #define MPC85xx_DEVDISR_SRIO 0x00080000 | |
1893 | #define MPC85xx_DEVDISR_RMSG 0x00040000 | |
53677ef1 WD |
1894 | #define MPC85xx_DEVDISR_DDR 0x00010000 |
1895 | #define MPC85xx_DEVDISR_CPU 0x00008000 | |
1896 | #define MPC85xx_DEVDISR_CPU0 MPC85xx_DEVDISR_CPU | |
1897 | #define MPC85xx_DEVDISR_TB 0x00004000 | |
1898 | #define MPC85xx_DEVDISR_TB0 MPC85xx_DEVDISR_TB | |
1899 | #define MPC85xx_DEVDISR_CPU1 0x00002000 | |
1900 | #define MPC85xx_DEVDISR_TB1 0x00001000 | |
837f1ba0 ES |
1901 | #define MPC85xx_DEVDISR_DMA 0x00000400 |
1902 | #define MPC85xx_DEVDISR_TSEC1 0x00000080 | |
1903 | #define MPC85xx_DEVDISR_TSEC2 0x00000040 | |
1904 | #define MPC85xx_DEVDISR_TSEC3 0x00000020 | |
1905 | #define MPC85xx_DEVDISR_TSEC4 0x00000010 | |
1906 | #define MPC85xx_DEVDISR_I2C 0x00000004 | |
1907 | #define MPC85xx_DEVDISR_DUART 0x00000002 | |
8280912e KG |
1908 | u8 res7[12]; |
1909 | u32 powmgtcsr; /* Power management status & control */ | |
1910 | u8 res8[12]; | |
1911 | u32 mcpsumr; /* Machine check summary */ | |
1912 | u8 res9[12]; | |
1913 | u32 pvr; /* Processor version */ | |
1914 | u32 svr; /* System version */ | |
1915 | u8 res10a[8]; | |
1916 | u32 rstcr; /* Reset control */ | |
22b6dbc1 | 1917 | #if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569) |
8280912e KG |
1918 | u8 res10b[76]; |
1919 | par_io_t qe_par_io[7]; | |
1920 | u8 res10c[3136]; | |
c59e4091 | 1921 | #else |
8280912e | 1922 | u8 res10b[3404]; |
c59e4091 | 1923 | #endif |
8280912e KG |
1924 | u32 clkocr; /* Clock out select */ |
1925 | u8 res11[12]; | |
1926 | u32 ddrdllcr; /* DDR DLL control */ | |
1927 | u8 res12[12]; | |
1928 | u32 lbcdllcr; /* LBC DLL control */ | |
1929 | u8 res13[248]; | |
1930 | u32 lbiuiplldcr0; /* LBIU PLL Debug Reg 0 */ | |
1931 | u32 lbiuiplldcr1; /* LBIU PLL Debug Reg 1 */ | |
1932 | u32 ddrioovcr; /* DDR IO Override Control */ | |
1933 | u32 tsec12ioovcr; /* eTSEC 1/2 IO override control */ | |
1934 | u32 tsec34ioovcr; /* eTSEC 3/4 IO override control */ | |
1935 | u8 res15[61648]; | |
42d1f039 | 1936 | } ccsr_gur_t; |
01df5212 KG |
1937 | #endif |
1938 | ||
11588b5d KG |
1939 | typedef struct serdes_corenet { |
1940 | struct { | |
1941 | u32 rstctl; /* Reset Control Register */ | |
1942 | #define SRDS_RSTCTL_RST 0x80000000 | |
1943 | #define SRDS_RSTCTL_RSTDONE 0x40000000 | |
1944 | #define SRDS_RSTCTL_RSTERR 0x20000000 | |
1945 | u32 pllcr0; /* PLL Control Register 0 */ | |
1946 | u32 pllcr1; /* PLL Control Register 1 */ | |
1947 | #define SRDS_PLLCR1_PLL_BWSEL 0x08000000 | |
1948 | u32 res[5]; | |
1949 | } bank[3]; | |
1950 | u32 res1[12]; | |
1951 | u32 srdstcalcr; /* TX Calibration Control */ | |
1952 | u32 res2[3]; | |
1953 | u32 srdsrcalcr; /* RX Calibration Control */ | |
1954 | u32 res3[3]; | |
1955 | u32 srdsgr0; /* General Register 0 */ | |
1956 | u32 res4[11]; | |
1957 | u32 srdspccr0; /* Protocol Converter Config 0 */ | |
1958 | u32 srdspccr1; /* Protocol Converter Config 1 */ | |
1959 | u32 srdspccr2; /* Protocol Converter Config 2 */ | |
1960 | #define SRDS_PCCR2_RST_XGMII1 0x00800000 | |
1961 | #define SRDS_PCCR2_RST_XGMII2 0x00400000 | |
1962 | u32 res5[197]; | |
1963 | struct { | |
1964 | u32 gcr0; /* General Control Register 0 */ | |
1965 | #define SRDS_GCR0_RRST 0x00400000 | |
1966 | #define SRDS_GCR0_1STLANE 0x00010000 | |
1967 | u32 gcr1; /* General Control Register 1 */ | |
1968 | #define SRDS_GCR1_REIDL_CTL_MASK 0x001f0000 | |
1969 | #define SRDS_GCR1_REIDL_CTL_PCIE 0x00100000 | |
1970 | #define SRDS_GCR1_REIDL_CTL_SRIO 0x00000000 | |
1971 | #define SRDS_GCR1_REIDL_CTL_SGMII 0x00040000 | |
1972 | #define SRDS_GCR1_OPAD_CTL 0x04000000 | |
1973 | u32 res1[4]; | |
1974 | u32 tecr0; /* TX Equalization Control Reg 0 */ | |
1975 | #define SRDS_TECR0_TEQ_TYPE_MASK 0x30000000 | |
1976 | #define SRDS_TECR0_TEQ_TYPE_2LVL 0x10000000 | |
1977 | u32 res3; | |
1978 | u32 ttlcr0; /* Transition Tracking Loop Ctrl 0 */ | |
1979 | u32 res4[7]; | |
1980 | } lane[24]; | |
1981 | u32 res6[384]; | |
1982 | } serdes_corenet_t; | |
1983 | ||
1984 | enum { | |
1985 | FSL_SRDS_B1_LANE_A = 0, | |
1986 | FSL_SRDS_B1_LANE_B = 1, | |
1987 | FSL_SRDS_B1_LANE_C = 2, | |
1988 | FSL_SRDS_B1_LANE_D = 3, | |
1989 | FSL_SRDS_B1_LANE_E = 4, | |
1990 | FSL_SRDS_B1_LANE_F = 5, | |
1991 | FSL_SRDS_B1_LANE_G = 6, | |
1992 | FSL_SRDS_B1_LANE_H = 7, | |
1993 | FSL_SRDS_B1_LANE_I = 8, | |
1994 | FSL_SRDS_B1_LANE_J = 9, | |
1995 | FSL_SRDS_B2_LANE_A = 16, | |
1996 | FSL_SRDS_B2_LANE_B = 17, | |
1997 | FSL_SRDS_B2_LANE_C = 18, | |
1998 | FSL_SRDS_B2_LANE_D = 19, | |
1999 | FSL_SRDS_B3_LANE_A = 20, | |
2000 | FSL_SRDS_B3_LANE_B = 21, | |
2001 | FSL_SRDS_B3_LANE_C = 22, | |
2002 | FSL_SRDS_B3_LANE_D = 23, | |
2003 | }; | |
2004 | ||
01df5212 KG |
2005 | #ifdef CONFIG_FSL_CORENET |
2006 | #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000 | |
2007 | #define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x8000 | |
2008 | #define CONFIG_SYS_MPC85xx_DDR2_OFFSET 0x9000 | |
2009 | #define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000 | |
2010 | #define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000 | |
11588b5d | 2011 | #define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000 |
8b0ab304 | 2012 | #define CONFIG_SYS_FSL_CPC_OFFSET 0x10000 |
01df5212 KG |
2013 | #define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x100000 |
2014 | #define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000 | |
2015 | #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000 | |
2016 | #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000 | |
2017 | #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000 | |
11588b5d | 2018 | #define CONFIG_SYS_MPC85xx_USB_OFFSET 0x210000 |
8280912e KG |
2019 | #define CONFIG_SYS_FSL_CORENET_QMAN_OFFSET 0x318000 |
2020 | #define CONFIG_SYS_FSL_CORENET_BMAN_OFFSET 0x31a000 | |
01df5212 KG |
2021 | #else |
2022 | #define CONFIG_SYS_MPC85xx_ECM_OFFSET 0x0000 | |
2023 | #define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x2000 | |
2024 | #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x5000 | |
2025 | #define CONFIG_SYS_MPC85xx_DDR2_OFFSET 0x6000 | |
2026 | #define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x7000 | |
2027 | #define CONFIG_SYS_MPC85xx_PCIX_OFFSET 0x8000 | |
2028 | #define CONFIG_SYS_MPC85xx_PCIX2_OFFSET 0x9000 | |
2029 | #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0xF000 | |
2030 | #define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x18000 | |
2031 | #define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x19000 | |
2032 | #define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000 | |
2033 | #define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000 | |
8280912e | 2034 | #define CONFIG_SYS_MPC85xx_USB_OFFSET 0x22000 |
3ad89c4e KG |
2035 | #ifdef CONFIG_TSECV2 |
2036 | #define CONFIG_SYS_TSEC1_OFFSET 0xB0000 | |
2037 | #else | |
b9e186fc | 2038 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 |
3ad89c4e KG |
2039 | #endif |
2040 | #define CONFIG_SYS_MDIO1_OFFSET 0x24000 | |
01df5212 KG |
2041 | #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000 |
2042 | #define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100 | |
2043 | #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000 | |
2044 | #define CONFIG_SYS_MPC85xx_CPM_OFFSET 0x80000 | |
2045 | #endif | |
2046 | ||
2047 | #define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000 | |
2048 | #define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000 | |
42d1f039 | 2049 | |
8b0ab304 BB |
2050 | #define CONFIG_SYS_FSL_CPC_ADDR \ |
2051 | (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET) | |
8280912e KG |
2052 | #define CONFIG_SYS_FSL_CORENET_QMAN_ADDR \ |
2053 | (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_QMAN_OFFSET) | |
2054 | #define CONFIG_SYS_FSL_CORENET_BMAN_ADDR \ | |
2055 | (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_BMAN_OFFSET) | |
2056 | #define CONFIG_SYS_MPC85xx_GUTS_ADDR \ | |
2057 | (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET) | |
2058 | #define CONFIG_SYS_FSL_CORENET_CCM_ADDR \ | |
2059 | (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET) | |
2060 | #define CONFIG_SYS_FSL_CORENET_CLK_ADDR \ | |
2061 | (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET) | |
2062 | #define CONFIG_SYS_FSL_CORENET_RCPM_ADDR \ | |
2063 | (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET) | |
2064 | #define CONFIG_SYS_MPC85xx_ECM_ADDR \ | |
2065 | (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET) | |
2066 | #define CONFIG_SYS_MPC85xx_DDR_ADDR \ | |
2067 | (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR_OFFSET) | |
2068 | #define CONFIG_SYS_MPC85xx_DDR2_ADDR \ | |
2069 | (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET) | |
2070 | #define CONFIG_SYS_MPC85xx_LBC_ADDR \ | |
2071 | (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET) | |
2072 | #define CONFIG_SYS_MPC85xx_ESPI_ADDR \ | |
2073 | (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET) | |
2074 | #define CONFIG_SYS_MPC85xx_PCIX_ADDR \ | |
2075 | (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET) | |
2076 | #define CONFIG_SYS_MPC85xx_PCIX2_ADDR \ | |
2077 | (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET) | |
2078 | #define CONFIG_SYS_MPC85xx_GPIO_ADDR \ | |
2079 | (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET) | |
2080 | #define CONFIG_SYS_MPC85xx_SATA1_ADDR \ | |
2081 | (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET) | |
2082 | #define CONFIG_SYS_MPC85xx_SATA2_ADDR \ | |
2083 | (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET) | |
2084 | #define CONFIG_SYS_MPC85xx_L2_ADDR \ | |
2085 | (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET) | |
2086 | #define CONFIG_SYS_MPC85xx_DMA_ADDR \ | |
2087 | (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET) | |
2088 | #define CONFIG_SYS_MPC85xx_ESDHC_ADDR \ | |
2089 | (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET) | |
2090 | #define CONFIG_SYS_MPC85xx_PIC_ADDR \ | |
2091 | (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET) | |
2092 | #define CONFIG_SYS_MPC85xx_CPM_ADDR \ | |
2093 | (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET) | |
2094 | #define CONFIG_SYS_MPC85xx_SERDES1_ADDR \ | |
2095 | (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET) | |
2096 | #define CONFIG_SYS_MPC85xx_SERDES2_ADDR \ | |
2097 | (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET) | |
11588b5d KG |
2098 | #define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \ |
2099 | (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET) | |
a07bf180 | 2100 | #define CONFIG_SYS_MPC85xx_USB_ADDR \ |
8280912e | 2101 | (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET) |
aafeefbd | 2102 | |
b9e186fc SG |
2103 | #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) |
2104 | #define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) | |
2105 | ||
42d1f039 | 2106 | #endif /*__IMMAP_85xx__*/ |