[thirdparty/kernel/stable.git] / arch / powerpc / include / asm / mmu.h

#ifndef _ASM_POWERPC_MMU_H_
#define _ASM_POWERPC_MMU_H_
#ifdef __KERNEL__

#include <linux/types.h>

#include <asm/asm-compat.h>
#include <asm/feature-fixups.h>

/*
 * MMU features bit definitions
 */

/*
 * MMU families
 */
#define MMU_FTR_HPTE_TABLE		ASM_CONST(0x00000001)
#define MMU_FTR_TYPE_8xx		ASM_CONST(0x00000002)
#define MMU_FTR_TYPE_40x		ASM_CONST(0x00000004)
#define MMU_FTR_TYPE_44x		ASM_CONST(0x00000008)
#define MMU_FTR_TYPE_FSL_E		ASM_CONST(0x00000010)
#define MMU_FTR_TYPE_47x		ASM_CONST(0x00000020)

/* Radix page table supported and enabled */
#define MMU_FTR_TYPE_RADIX		ASM_CONST(0x00000040)

/*
 * Individual features below.
 */

/*
 * We need to clear top 16bits of va (from the remaining 64 bits )in
 * tlbie* instructions
 */
#define MMU_FTR_TLBIE_CROP_VA		ASM_CONST(0x00008000)

/* Enable use of high BAT registers */
#define MMU_FTR_USE_HIGH_BATS		ASM_CONST(0x00010000)

/* Enable >32-bit physical addresses on 32-bit processor, only used
 * by CONFIG_6xx currently as BookE supports that from day 1
 */
#define MMU_FTR_BIG_PHYS		ASM_CONST(0x00020000)

/* Enable use of broadcast TLB invalidations. We don't always set it
 * on processors that support it due to other constraints with the
 * use of such invalidations
 */
#define MMU_FTR_USE_TLBIVAX_BCAST	ASM_CONST(0x00040000)

/* Enable use of tlbilx invalidate instructions.
 */
#define MMU_FTR_USE_TLBILX		ASM_CONST(0x00080000)

/* This indicates that the processor cannot handle multiple outstanding
 * broadcast tlbivax or tlbsync. This makes the code use a spinlock
 * around such invalidate forms.
 */
#define MMU_FTR_LOCK_BCAST_INVAL	ASM_CONST(0x00100000)

/* This indicates that the processor doesn't handle way selection
 * properly and needs SW to track and update the LRU state.  This
 * is specific to an errata on e300c2/c3/c4 class parts
 */
#define MMU_FTR_NEED_DTLB_SW_LRU	ASM_CONST(0x00200000)

/* Enable use of TLB reservation.  Processor should support tlbsrx.
 * instruction and MAS0[WQ].
 */
#define MMU_FTR_USE_TLBRSRV		ASM_CONST(0x00800000)

/* Use paired MAS registers (MAS7||MAS3, etc.)
 */
#define MMU_FTR_USE_PAIRED_MAS		ASM_CONST(0x01000000)

/* Doesn't support the B bit (1T segment) in SLBIE
 */
#define MMU_FTR_NO_SLBIE_B		ASM_CONST(0x02000000)

/* Support 16M large pages
 */
#define MMU_FTR_16M_PAGE		ASM_CONST(0x04000000)

/* Supports TLBIEL variant
 */
#define MMU_FTR_TLBIEL			ASM_CONST(0x08000000)

/* Supports tlbies w/o locking
 */
#define MMU_FTR_LOCKLESS_TLBIE		ASM_CONST(0x10000000)

/* Large pages can be marked CI
 */
#define MMU_FTR_CI_LARGE_PAGE		ASM_CONST(0x20000000)

/* 1T segments available
 */
#define MMU_FTR_1T_SEGMENT		ASM_CONST(0x40000000)

/* MMU feature bit sets for various CPUs */
#define MMU_FTRS_DEFAULT_HPTE_ARCH_V2	\
	MMU_FTR_HPTE_TABLE | MMU_FTR_PPCAS_ARCH_V2
#define MMU_FTRS_POWER4		MMU_FTRS_DEFAULT_HPTE_ARCH_V2
#define MMU_FTRS_PPC970		MMU_FTRS_POWER4 | MMU_FTR_TLBIE_CROP_VA
#define MMU_FTRS_POWER5		MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
#define MMU_FTRS_POWER6		MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
#define MMU_FTRS_POWER7		MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
#define MMU_FTRS_POWER8		MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
#define MMU_FTRS_POWER9		MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
#define MMU_FTRS_CELL		MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
				MMU_FTR_CI_LARGE_PAGE
#define MMU_FTRS_PA6T		MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
				MMU_FTR_CI_LARGE_PAGE | MMU_FTR_NO_SLBIE_B
#ifndef __ASSEMBLY__
#include <asm/cputable.h>

#ifdef CONFIG_PPC_FSL_BOOK3E
#include <asm/percpu.h>
DECLARE_PER_CPU(int, next_tlbcam_idx);
#endif

enum {
	MMU_FTRS_POSSIBLE = MMU_FTR_HPTE_TABLE | MMU_FTR_TYPE_8xx |
		MMU_FTR_TYPE_40x | MMU_FTR_TYPE_44x | MMU_FTR_TYPE_FSL_E |
		MMU_FTR_TYPE_47x | MMU_FTR_USE_HIGH_BATS | MMU_FTR_BIG_PHYS |
		MMU_FTR_USE_TLBIVAX_BCAST | MMU_FTR_USE_TLBILX |
		MMU_FTR_LOCK_BCAST_INVAL | MMU_FTR_NEED_DTLB_SW_LRU |
		MMU_FTR_USE_TLBRSRV | MMU_FTR_USE_PAIRED_MAS |
		MMU_FTR_NO_SLBIE_B | MMU_FTR_16M_PAGE | MMU_FTR_TLBIEL |
		MMU_FTR_LOCKLESS_TLBIE | MMU_FTR_CI_LARGE_PAGE |
		MMU_FTR_1T_SEGMENT | MMU_FTR_TLBIE_CROP_VA |
#ifdef CONFIG_PPC_RADIX_MMU
		MMU_FTR_TYPE_RADIX |
#endif
		0,
};

static inline bool mmu_has_feature(unsigned long feature)
{
	return !!(MMU_FTRS_POSSIBLE & cur_cpu_spec->mmu_features & feature);
}

static inline void mmu_clear_feature(unsigned long feature)
{
	cur_cpu_spec->mmu_features &= ~feature;
}

extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup;

#ifdef CONFIG_PPC64
/* This is our real memory area size on ppc64 server, on embedded, we
 * make it match the size our of bolted TLB area
 */
extern u64 ppc64_rma_size;
#endif /* CONFIG_PPC64 */

struct mm_struct;
#ifdef CONFIG_DEBUG_VM
extern void assert_pte_locked(struct mm_struct *mm, unsigned long addr);
#else /* CONFIG_DEBUG_VM */
static inline void assert_pte_locked(struct mm_struct *mm, unsigned long addr)
{
}
#endif /* !CONFIG_DEBUG_VM */

#endif /* !__ASSEMBLY__ */

/* The kernel use the constants below to index in the page sizes array.
 * The use of fixed constants for this purpose is better for performances
 * of the low level hash refill handlers.
 *
 * A non supported page size has a "shift" field set to 0
 *
 * Any new page size being implemented can get a new entry in here. Whether
 * the kernel will use it or not is a different matter though. The actual page
 * size used by hugetlbfs is not defined here and may be made variable
 *
 * Note: This array ended up being a false good idea as it's growing to the
 * point where I wonder if we should replace it with something different,
 * to think about, feedback welcome. --BenH.
 */

/* These are #defines as they have to be used in assembly */
#define MMU_PAGE_4K	0
#define MMU_PAGE_16K	1
#define MMU_PAGE_64K	2
#define MMU_PAGE_64K_AP	3	/* "Admixed pages" (hash64 only) */
#define MMU_PAGE_256K	4
#define MMU_PAGE_1M	5
#define MMU_PAGE_2M	6
#define MMU_PAGE_4M	7
#define MMU_PAGE_8M	8
#define MMU_PAGE_16M	9
#define MMU_PAGE_64M	10
#define MMU_PAGE_256M	11
#define MMU_PAGE_1G	12
#define MMU_PAGE_16G	13
#define MMU_PAGE_64G	14

#define MMU_PAGE_COUNT	15

#ifdef CONFIG_PPC_BOOK3S_64
#include <asm/book3s/64/mmu.h>
#else /* CONFIG_PPC_BOOK3S_64 */

#ifndef __ASSEMBLY__
/* MMU initialization */
extern void early_init_mmu(void);
extern void early_init_mmu_secondary(void);
extern void setup_initial_memory_limit(phys_addr_t first_memblock_base,
				       phys_addr_t first_memblock_size);
static inline void mmu_early_init_devtree(void) { }
#endif /* __ASSEMBLY__ */
#endif

#if defined(CONFIG_PPC_STD_MMU_32)
/* 32-bit classic hash table MMU */
#include <asm/book3s/32/mmu-hash.h>
#elif defined(CONFIG_40x)
/* 40x-style software loaded TLB */
#  include <asm/mmu-40x.h>
#elif defined(CONFIG_44x)
/* 44x-style software loaded TLB */
#  include <asm/mmu-44x.h>
#elif defined(CONFIG_PPC_BOOK3E_MMU)
/* Freescale Book-E software loaded TLB or Book-3e (ISA 2.06+) MMU */
#  include <asm/mmu-book3e.h>
#elif defined (CONFIG_PPC_8xx)
/* Motorola/Freescale 8xx software loaded TLB */
#  include <asm/mmu-8xx.h>
#endif

#ifndef radix_enabled
#define radix_enabled() (0)
#endif

#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_MMU_H_ */
Commit	Line	Data
047ea784 PM	1	#ifndef _ASM_POWERPC_MMU_H_
047ea784 PM	2	#define _ASM_POWERPC_MMU_H_
88ced031	3	#ifdef __KERNEL__
047ea784	4
cd3db0c4 BH	5	#include <linux/types.h>
cd3db0c4 BH	6
7c03d653 BH	7	#include <asm/asm-compat.h>
	8	#include <asm/feature-fixups.h>
	9
	10	/*
	11	* MMU features bit definitions
	12	*/
	13
	14	/*
5a25b6f5	15	* MMU families
7c03d653 BH	16	*/
	17	#define MMU_FTR_HPTE_TABLE ASM_CONST(0x00000001)
	18	#define MMU_FTR_TYPE_8xx ASM_CONST(0x00000002)
	19	#define MMU_FTR_TYPE_40x ASM_CONST(0x00000004)
	20	#define MMU_FTR_TYPE_44x ASM_CONST(0x00000008)
	21	#define MMU_FTR_TYPE_FSL_E ASM_CONST(0x00000010)
cd68098b	22	#define MMU_FTR_TYPE_47x ASM_CONST(0x00000020)
7c03d653	23
5a25b6f5 AK	24	/* Radix page table supported and enabled */
	25	#define MMU_FTR_TYPE_RADIX ASM_CONST(0x00000040)
	26
7c03d653	27	/*
5a25b6f5	28	* Individual features below.
7c03d653	29	*/
5a25b6f5	30
accfad7d AK	31	/*
	32	* We need to clear top 16bits of va (from the remaining 64 bits )in
	33	* tlbie* instructions
	34	*/
	35	#define MMU_FTR_TLBIE_CROP_VA ASM_CONST(0x00008000)
7c03d653 BH	36
	37	/* Enable use of high BAT registers */
	38	#define MMU_FTR_USE_HIGH_BATS ASM_CONST(0x00010000)
	39
	40	/* Enable >32-bit physical addresses on 32-bit processor, only used
	41	* by CONFIG_6xx currently as BookE supports that from day 1
	42	*/
	43	#define MMU_FTR_BIG_PHYS ASM_CONST(0x00020000)
	44
f048aace BH	45	/* Enable use of broadcast TLB invalidations. We don't always set it
	46	* on processors that support it due to other constraints with the
	47	* use of such invalidations
	48	*/
	49	#define MMU_FTR_USE_TLBIVAX_BCAST ASM_CONST(0x00040000)
	50
c3071951	51	/* Enable use of tlbilx invalidate instructions.
f048aace	52	*/
c3071951	53	#define MMU_FTR_USE_TLBILX ASM_CONST(0x00080000)
f048aace BH	54
	55	/* This indicates that the processor cannot handle multiple outstanding
	56	* broadcast tlbivax or tlbsync. This makes the code use a spinlock
	57	* around such invalidate forms.
	58	*/
	59	#define MMU_FTR_LOCK_BCAST_INVAL ASM_CONST(0x00100000)
	60
2319f123 KG	61	/* This indicates that the processor doesn't handle way selection
	62	* properly and needs SW to track and update the LRU state. This
	63	* is specific to an errata on e300c2/c3/c4 class parts
	64	*/
	65	#define MMU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x00200000)
	66
df5d6ecf KG	67	/* Enable use of TLB reservation. Processor should support tlbsrx.
	68	* instruction and MAS0[WQ].
	69	*/
	70	#define MMU_FTR_USE_TLBRSRV ASM_CONST(0x00800000)
	71
	72	/* Use paired MAS registers (MAS7\|\|MAS3, etc.)
	73	*/
	74	#define MMU_FTR_USE_PAIRED_MAS ASM_CONST(0x01000000)
	75
13b3d13b	76	/* Doesn't support the B bit (1T segment) in SLBIE
44ae3ab3	77	*/
13b3d13b	78	#define MMU_FTR_NO_SLBIE_B ASM_CONST(0x02000000)
44ae3ab3 ME	79
	80	/* Support 16M large pages
	81	*/
	82	#define MMU_FTR_16M_PAGE ASM_CONST(0x04000000)
	83
	84	/* Supports TLBIEL variant
	85	*/
	86	#define MMU_FTR_TLBIEL ASM_CONST(0x08000000)
	87
	88	/* Supports tlbies w/o locking
	89	*/
	90	#define MMU_FTR_LOCKLESS_TLBIE ASM_CONST(0x10000000)
	91
	92	/* Large pages can be marked CI
	93	*/
	94	#define MMU_FTR_CI_LARGE_PAGE ASM_CONST(0x20000000)
	95
	96	/* 1T segments available
	97	*/
	98	#define MMU_FTR_1T_SEGMENT ASM_CONST(0x40000000)
	99
44ae3ab3 ME	100	/* MMU feature bit sets for various CPUs */
	101	#define MMU_FTRS_DEFAULT_HPTE_ARCH_V2 \
	102	MMU_FTR_HPTE_TABLE \| MMU_FTR_PPCAS_ARCH_V2
	103	#define MMU_FTRS_POWER4 MMU_FTRS_DEFAULT_HPTE_ARCH_V2
accfad7d	104	#define MMU_FTRS_PPC970 MMU_FTRS_POWER4 \| MMU_FTR_TLBIE_CROP_VA
44ae3ab3 ME	105	#define MMU_FTRS_POWER5 MMU_FTRS_POWER4 \| MMU_FTR_LOCKLESS_TLBIE
44ae3ab3 ME	106	#define MMU_FTRS_POWER6 MMU_FTRS_POWER4 \| MMU_FTR_LOCKLESS_TLBIE
a32e252f	107	#define MMU_FTRS_POWER7 MMU_FTRS_POWER4 \| MMU_FTR_LOCKLESS_TLBIE
71e18497	108	#define MMU_FTRS_POWER8 MMU_FTRS_POWER4 \| MMU_FTR_LOCKLESS_TLBIE
c3ab300e	109	#define MMU_FTRS_POWER9 MMU_FTRS_POWER4 \| MMU_FTR_LOCKLESS_TLBIE
44ae3ab3 ME	110	#define MMU_FTRS_CELL MMU_FTRS_DEFAULT_HPTE_ARCH_V2 \| \
	111	MMU_FTR_CI_LARGE_PAGE
	112	#define MMU_FTRS_PA6T MMU_FTRS_DEFAULT_HPTE_ARCH_V2 \| \
	113	MMU_FTR_CI_LARGE_PAGE \| MMU_FTR_NO_SLBIE_B
7c03d653 BH	114	#ifndef __ASSEMBLY__
	115	#include <asm/cputable.h>
	116
3160b097 BB	117	#ifdef CONFIG_PPC_FSL_BOOK3E
	118	#include <asm/percpu.h>
	119	DECLARE_PER_CPU(int, next_tlbcam_idx);
	120	#endif
	121
773edead ME	122	enum {
	123	MMU_FTRS_POSSIBLE = MMU_FTR_HPTE_TABLE \| MMU_FTR_TYPE_8xx \|
	124	MMU_FTR_TYPE_40x \| MMU_FTR_TYPE_44x \| MMU_FTR_TYPE_FSL_E \|
	125	MMU_FTR_TYPE_47x \| MMU_FTR_USE_HIGH_BATS \| MMU_FTR_BIG_PHYS \|
	126	MMU_FTR_USE_TLBIVAX_BCAST \| MMU_FTR_USE_TLBILX \|
	127	MMU_FTR_LOCK_BCAST_INVAL \| MMU_FTR_NEED_DTLB_SW_LRU \|
	128	MMU_FTR_USE_TLBRSRV \| MMU_FTR_USE_PAIRED_MAS \|
	129	MMU_FTR_NO_SLBIE_B \| MMU_FTR_16M_PAGE \| MMU_FTR_TLBIEL \|
	130	MMU_FTR_LOCKLESS_TLBIE \| MMU_FTR_CI_LARGE_PAGE \|
accfad7d	131	MMU_FTR_1T_SEGMENT \| MMU_FTR_TLBIE_CROP_VA \|
a8ed87c9	132	#ifdef CONFIG_PPC_RADIX_MMU
5a25b6f5	133	MMU_FTR_TYPE_RADIX \|
a8ed87c9 AK	134	#endif
a8ed87c9 AK	135	0,
773edead ME	136	};
773edead ME	137
a81dc9d9	138	static inline bool mmu_has_feature(unsigned long feature)
7c03d653	139	{
a81dc9d9	140	return !!(MMU_FTRS_POSSIBLE & cur_cpu_spec->mmu_features & feature);
7c03d653 BH	141	}
7c03d653 BH	142
91b191c7 DK	143	static inline void mmu_clear_feature(unsigned long feature)
	144	{
	145	cur_cpu_spec->mmu_features &= ~feature;
	146	}
	147
7c03d653 BH	148	extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup;
7c03d653 BH	149
cd3db0c4 BH	150	#ifdef CONFIG_PPC64
	151	/* This is our real memory area size on ppc64 server, on embedded, we
	152	* make it match the size our of bolted TLB area
	153	*/
	154	extern u64 ppc64_rma_size;
	155	#endif /* CONFIG_PPC64 */
	156
78f1dbde AK	157	struct mm_struct;
	158	#ifdef CONFIG_DEBUG_VM
	159	extern void assert_pte_locked(struct mm_struct *mm, unsigned long addr);
	160	#else /* CONFIG_DEBUG_VM */
	161	static inline void assert_pte_locked(struct mm_struct *mm, unsigned long addr)
	162	{
	163	}
	164	#endif /* !CONFIG_DEBUG_VM */
	165
7c03d653 BH	166	#endif /* !__ASSEMBLY__ */
7c03d653 BH	167
57e2a99f BH	168	/* The kernel use the constants below to index in the page sizes array.
	169	* The use of fixed constants for this purpose is better for performances
	170	* of the low level hash refill handlers.
	171	*
	172	* A non supported page size has a "shift" field set to 0
	173	*
	174	* Any new page size being implemented can get a new entry in here. Whether
	175	* the kernel will use it or not is a different matter though. The actual page
	176	* size used by hugetlbfs is not defined here and may be made variable
	177	*
	178	* Note: This array ended up being a false good idea as it's growing to the
	179	* point where I wonder if we should replace it with something different,
	180	* to think about, feedback welcome. --BenH.
	181	*/
	182
a8b91e43	183	/* These are #defines as they have to be used in assembly */
57e2a99f BH	184	#define MMU_PAGE_4K 0
	185	#define MMU_PAGE_16K 1
	186	#define MMU_PAGE_64K 2
	187	#define MMU_PAGE_64K_AP 3 /* "Admixed pages" (hash64 only) */
	188	#define MMU_PAGE_256K 4
	189	#define MMU_PAGE_1M 5
28efc35f SW	190	#define MMU_PAGE_2M 6
	191	#define MMU_PAGE_4M 7
	192	#define MMU_PAGE_8M 8
	193	#define MMU_PAGE_16M 9
	194	#define MMU_PAGE_64M 10
	195	#define MMU_PAGE_256M 11
	196	#define MMU_PAGE_1G 12
	197	#define MMU_PAGE_16G 13
	198	#define MMU_PAGE_64G 14
	199
	200	#define MMU_PAGE_COUNT 15
7c03d653	201
11a6f6ab AK	202	#ifdef CONFIG_PPC_BOOK3S_64
	203	#include <asm/book3s/64/mmu.h>
	204	#else /* CONFIG_PPC_BOOK3S_64 */
	205
756d08d1 AK	206	#ifndef __ASSEMBLY__
	207	/* MMU initialization */
	208	extern void early_init_mmu(void);
	209	extern void early_init_mmu_secondary(void);
	210	extern void setup_initial_memory_limit(phys_addr_t first_memblock_base,
	211	phys_addr_t first_memblock_size);
1a01dc87	212	static inline void mmu_early_init_devtree(void) { }
756d08d1	213	#endif /* __ASSEMBLY__ */
11a6f6ab AK	214	#endif
	215
	216	#if defined(CONFIG_PPC_STD_MMU_32)
4db68bfe	217	/* 32-bit classic hash table MMU */
f64e8084	218	#include <asm/book3s/32/mmu-hash.h>
4d922c8d JB	219	#elif defined(CONFIG_40x)
	220	/* 40x-style software loaded TLB */
	221	# include <asm/mmu-40x.h>
57d7909e DG	222	#elif defined(CONFIG_44x)
	223	/* 44x-style software loaded TLB */
	224	# include <asm/mmu-44x.h>
70fe3af8 KG	225	#elif defined(CONFIG_PPC_BOOK3E_MMU)
	226	/* Freescale Book-E software loaded TLB or Book-3e (ISA 2.06+) MMU */
	227	# include <asm/mmu-book3e.h>
31202345 DG	228	#elif defined (CONFIG_PPC_8xx)
	229	/* Motorola/Freescale 8xx software loaded TLB */
	230	# include <asm/mmu-8xx.h>
1f8d419e	231	#endif
1f8d419e	232
566ca99a AK	233	#ifndef radix_enabled
	234	#define radix_enabled() (0)
	235	#endif
57e2a99f	236
88ced031	237	#endif /* __KERNEL__ */
047ea784	238	#endif /* _ASM_POWERPC_MMU_H_ */