[thirdparty/kernel/stable.git] / arch / powerpc / include / asm / mmu.h

#ifndef _ASM_POWERPC_MMU_H_
#define _ASM_POWERPC_MMU_H_
#ifdef __KERNEL__

#include <linux/types.h>

#include <asm/asm-compat.h>
#include <asm/feature-fixups.h>

/*
 * MMU features bit definitions
 */

/*
 * First half is MMU families
 */
#define MMU_FTR_HPTE_TABLE		ASM_CONST(0x00000001)
#define MMU_FTR_TYPE_8xx		ASM_CONST(0x00000002)
#define MMU_FTR_TYPE_40x		ASM_CONST(0x00000004)
#define MMU_FTR_TYPE_44x		ASM_CONST(0x00000008)
#define MMU_FTR_TYPE_FSL_E		ASM_CONST(0x00000010)
#define MMU_FTR_TYPE_47x		ASM_CONST(0x00000020)

/*
 * This is individual features
 */

/* Enable use of high BAT registers */
#define MMU_FTR_USE_HIGH_BATS		ASM_CONST(0x00010000)

/* Enable >32-bit physical addresses on 32-bit processor, only used
 * by CONFIG_6xx currently as BookE supports that from day 1
 */
#define MMU_FTR_BIG_PHYS		ASM_CONST(0x00020000)

/* Enable use of broadcast TLB invalidations. We don't always set it
 * on processors that support it due to other constraints with the
 * use of such invalidations
 */
#define MMU_FTR_USE_TLBIVAX_BCAST	ASM_CONST(0x00040000)

/* Enable use of tlbilx invalidate instructions.
 */
#define MMU_FTR_USE_TLBILX		ASM_CONST(0x00080000)

/* This indicates that the processor cannot handle multiple outstanding
 * broadcast tlbivax or tlbsync. This makes the code use a spinlock
 * around such invalidate forms.
 */
#define MMU_FTR_LOCK_BCAST_INVAL	ASM_CONST(0x00100000)

/* This indicates that the processor doesn't handle way selection
 * properly and needs SW to track and update the LRU state.  This
 * is specific to an errata on e300c2/c3/c4 class parts
 */
#define MMU_FTR_NEED_DTLB_SW_LRU	ASM_CONST(0x00200000)

/* Enable use of TLB reservation.  Processor should support tlbsrx.
 * instruction and MAS0[WQ].
 */
#define MMU_FTR_USE_TLBRSRV		ASM_CONST(0x00800000)

/* Use paired MAS registers (MAS7||MAS3, etc.)
 */
#define MMU_FTR_USE_PAIRED_MAS		ASM_CONST(0x01000000)

/* Doesn't support the B bit (1T segment) in SLBIE
 */
#define MMU_FTR_NO_SLBIE_B		ASM_CONST(0x02000000)

/* Support 16M large pages
 */
#define MMU_FTR_16M_PAGE		ASM_CONST(0x04000000)

/* Supports TLBIEL variant
 */
#define MMU_FTR_TLBIEL			ASM_CONST(0x08000000)

/* Supports tlbies w/o locking
 */
#define MMU_FTR_LOCKLESS_TLBIE		ASM_CONST(0x10000000)

/* Large pages can be marked CI
 */
#define MMU_FTR_CI_LARGE_PAGE		ASM_CONST(0x20000000)

/* 1T segments available
 */
#define MMU_FTR_1T_SEGMENT		ASM_CONST(0x40000000)

/* MMU feature bit sets for various CPUs */
#define MMU_FTRS_DEFAULT_HPTE_ARCH_V2	\
	MMU_FTR_HPTE_TABLE | MMU_FTR_PPCAS_ARCH_V2
#define MMU_FTRS_POWER4		MMU_FTRS_DEFAULT_HPTE_ARCH_V2
#define MMU_FTRS_PPC970		MMU_FTRS_POWER4
#define MMU_FTRS_POWER5		MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
#define MMU_FTRS_POWER6		MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
#define MMU_FTRS_POWER7		MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
#define MMU_FTRS_POWER8		MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
#define MMU_FTRS_POWER9		MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
#define MMU_FTRS_CELL		MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
				MMU_FTR_CI_LARGE_PAGE
#define MMU_FTRS_PA6T		MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
				MMU_FTR_CI_LARGE_PAGE | MMU_FTR_NO_SLBIE_B
#ifndef __ASSEMBLY__
#include <asm/cputable.h>

#ifdef CONFIG_PPC_FSL_BOOK3E
#include <asm/percpu.h>
DECLARE_PER_CPU(int, next_tlbcam_idx);
#endif

static inline int mmu_has_feature(unsigned long feature)
{
	return (cur_cpu_spec->mmu_features & feature);
}

static inline void mmu_clear_feature(unsigned long feature)
{
	cur_cpu_spec->mmu_features &= ~feature;
}

extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup;

/* MMU initialization */
extern void early_init_mmu(void);
extern void early_init_mmu_secondary(void);

extern void setup_initial_memory_limit(phys_addr_t first_memblock_base,
				       phys_addr_t first_memblock_size);

#ifdef CONFIG_PPC64
/* This is our real memory area size on ppc64 server, on embedded, we
 * make it match the size our of bolted TLB area
 */
extern u64 ppc64_rma_size;
#endif /* CONFIG_PPC64 */

struct mm_struct;
#ifdef CONFIG_DEBUG_VM
extern void assert_pte_locked(struct mm_struct *mm, unsigned long addr);
#else /* CONFIG_DEBUG_VM */
static inline void assert_pte_locked(struct mm_struct *mm, unsigned long addr)
{
}
#endif /* !CONFIG_DEBUG_VM */

#endif /* !__ASSEMBLY__ */

/* The kernel use the constants below to index in the page sizes array.
 * The use of fixed constants for this purpose is better for performances
 * of the low level hash refill handlers.
 *
 * A non supported page size has a "shift" field set to 0
 *
 * Any new page size being implemented can get a new entry in here. Whether
 * the kernel will use it or not is a different matter though. The actual page
 * size used by hugetlbfs is not defined here and may be made variable
 *
 * Note: This array ended up being a false good idea as it's growing to the
 * point where I wonder if we should replace it with something different,
 * to think about, feedback welcome. --BenH.
 */

/* These are #defines as they have to be used in assembly */
#define MMU_PAGE_4K	0
#define MMU_PAGE_16K	1
#define MMU_PAGE_64K	2
#define MMU_PAGE_64K_AP	3	/* "Admixed pages" (hash64 only) */
#define MMU_PAGE_256K	4
#define MMU_PAGE_1M	5
#define MMU_PAGE_2M	6
#define MMU_PAGE_4M	7
#define MMU_PAGE_8M	8
#define MMU_PAGE_16M	9
#define MMU_PAGE_64M	10
#define MMU_PAGE_256M	11
#define MMU_PAGE_1G	12
#define MMU_PAGE_16G	13
#define MMU_PAGE_64G	14

#define MMU_PAGE_COUNT	15

#ifdef CONFIG_PPC_BOOK3S_64
#include <asm/book3s/64/mmu.h>
#else /* CONFIG_PPC_BOOK3S_64 */

#endif

#if defined(CONFIG_PPC_STD_MMU_32)
/* 32-bit classic hash table MMU */
#include <asm/book3s/32/mmu-hash.h>
#elif defined(CONFIG_40x)
/* 40x-style software loaded TLB */
#  include <asm/mmu-40x.h>
#elif defined(CONFIG_44x)
/* 44x-style software loaded TLB */
#  include <asm/mmu-44x.h>
#elif defined(CONFIG_PPC_BOOK3E_MMU)
/* Freescale Book-E software loaded TLB or Book-3e (ISA 2.06+) MMU */
#  include <asm/mmu-book3e.h>
#elif defined (CONFIG_PPC_8xx)
/* Motorola/Freescale 8xx software loaded TLB */
#  include <asm/mmu-8xx.h>
#endif

#ifndef radix_enabled
#define radix_enabled() (0)
#endif

#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_MMU_H_ */
Commit	Line	Data
047ea784 PM	1	#ifndef _ASM_POWERPC_MMU_H_
047ea784 PM	2	#define _ASM_POWERPC_MMU_H_
88ced031	3	#ifdef __KERNEL__
047ea784	4
cd3db0c4 BH	5	#include <linux/types.h>
cd3db0c4 BH	6
7c03d653 BH	7	#include <asm/asm-compat.h>
	8	#include <asm/feature-fixups.h>
	9
	10	/*
	11	* MMU features bit definitions
	12	*/
	13
	14	/*
	15	* First half is MMU families
	16	*/
	17	#define MMU_FTR_HPTE_TABLE ASM_CONST(0x00000001)
	18	#define MMU_FTR_TYPE_8xx ASM_CONST(0x00000002)
	19	#define MMU_FTR_TYPE_40x ASM_CONST(0x00000004)
	20	#define MMU_FTR_TYPE_44x ASM_CONST(0x00000008)
	21	#define MMU_FTR_TYPE_FSL_E ASM_CONST(0x00000010)
cd68098b	22	#define MMU_FTR_TYPE_47x ASM_CONST(0x00000020)
7c03d653 BH	23
	24	/*
	25	* This is individual features
	26	*/
	27
	28	/* Enable use of high BAT registers */
	29	#define MMU_FTR_USE_HIGH_BATS ASM_CONST(0x00010000)
	30
	31	/* Enable >32-bit physical addresses on 32-bit processor, only used
	32	* by CONFIG_6xx currently as BookE supports that from day 1
	33	*/
	34	#define MMU_FTR_BIG_PHYS ASM_CONST(0x00020000)
	35
f048aace BH	36	/* Enable use of broadcast TLB invalidations. We don't always set it
	37	* on processors that support it due to other constraints with the
	38	* use of such invalidations
	39	*/
	40	#define MMU_FTR_USE_TLBIVAX_BCAST ASM_CONST(0x00040000)
	41
c3071951	42	/* Enable use of tlbilx invalidate instructions.
f048aace	43	*/
c3071951	44	#define MMU_FTR_USE_TLBILX ASM_CONST(0x00080000)
f048aace BH	45
	46	/* This indicates that the processor cannot handle multiple outstanding
	47	* broadcast tlbivax or tlbsync. This makes the code use a spinlock
	48	* around such invalidate forms.
	49	*/
	50	#define MMU_FTR_LOCK_BCAST_INVAL ASM_CONST(0x00100000)
	51
2319f123 KG	52	/* This indicates that the processor doesn't handle way selection
	53	* properly and needs SW to track and update the LRU state. This
	54	* is specific to an errata on e300c2/c3/c4 class parts
	55	*/
	56	#define MMU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x00200000)
	57
df5d6ecf KG	58	/* Enable use of TLB reservation. Processor should support tlbsrx.
	59	* instruction and MAS0[WQ].
	60	*/
	61	#define MMU_FTR_USE_TLBRSRV ASM_CONST(0x00800000)
	62
	63	/* Use paired MAS registers (MAS7\|\|MAS3, etc.)
	64	*/
	65	#define MMU_FTR_USE_PAIRED_MAS ASM_CONST(0x01000000)
	66
13b3d13b	67	/* Doesn't support the B bit (1T segment) in SLBIE
44ae3ab3	68	*/
13b3d13b	69	#define MMU_FTR_NO_SLBIE_B ASM_CONST(0x02000000)
44ae3ab3 ME	70
	71	/* Support 16M large pages
	72	*/
	73	#define MMU_FTR_16M_PAGE ASM_CONST(0x04000000)
	74
	75	/* Supports TLBIEL variant
	76	*/
	77	#define MMU_FTR_TLBIEL ASM_CONST(0x08000000)
	78
	79	/* Supports tlbies w/o locking
	80	*/
	81	#define MMU_FTR_LOCKLESS_TLBIE ASM_CONST(0x10000000)
	82
	83	/* Large pages can be marked CI
	84	*/
	85	#define MMU_FTR_CI_LARGE_PAGE ASM_CONST(0x20000000)
	86
	87	/* 1T segments available
	88	*/
	89	#define MMU_FTR_1T_SEGMENT ASM_CONST(0x40000000)
	90
44ae3ab3 ME	91	/* MMU feature bit sets for various CPUs */
	92	#define MMU_FTRS_DEFAULT_HPTE_ARCH_V2 \
	93	MMU_FTR_HPTE_TABLE \| MMU_FTR_PPCAS_ARCH_V2
	94	#define MMU_FTRS_POWER4 MMU_FTRS_DEFAULT_HPTE_ARCH_V2
	95	#define MMU_FTRS_PPC970 MMU_FTRS_POWER4
	96	#define MMU_FTRS_POWER5 MMU_FTRS_POWER4 \| MMU_FTR_LOCKLESS_TLBIE
	97	#define MMU_FTRS_POWER6 MMU_FTRS_POWER4 \| MMU_FTR_LOCKLESS_TLBIE
a32e252f	98	#define MMU_FTRS_POWER7 MMU_FTRS_POWER4 \| MMU_FTR_LOCKLESS_TLBIE
71e18497	99	#define MMU_FTRS_POWER8 MMU_FTRS_POWER4 \| MMU_FTR_LOCKLESS_TLBIE
c3ab300e	100	#define MMU_FTRS_POWER9 MMU_FTRS_POWER4 \| MMU_FTR_LOCKLESS_TLBIE
44ae3ab3 ME	101	#define MMU_FTRS_CELL MMU_FTRS_DEFAULT_HPTE_ARCH_V2 \| \
	102	MMU_FTR_CI_LARGE_PAGE
	103	#define MMU_FTRS_PA6T MMU_FTRS_DEFAULT_HPTE_ARCH_V2 \| \
	104	MMU_FTR_CI_LARGE_PAGE \| MMU_FTR_NO_SLBIE_B
7c03d653 BH	105	#ifndef __ASSEMBLY__
	106	#include <asm/cputable.h>
	107
3160b097 BB	108	#ifdef CONFIG_PPC_FSL_BOOK3E
	109	#include <asm/percpu.h>
	110	DECLARE_PER_CPU(int, next_tlbcam_idx);
	111	#endif
	112
7c03d653 BH	113	static inline int mmu_has_feature(unsigned long feature)
	114	{
	115	return (cur_cpu_spec->mmu_features & feature);
	116	}
	117
91b191c7 DK	118	static inline void mmu_clear_feature(unsigned long feature)
	119	{
	120	cur_cpu_spec->mmu_features &= ~feature;
	121	}
	122
7c03d653 BH	123	extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup;
7c03d653 BH	124
91b191c7	125	/* MMU initialization */
757c74d2 BH	126	extern void early_init_mmu(void);
	127	extern void early_init_mmu_secondary(void);
	128
cd3db0c4 BH	129	extern void setup_initial_memory_limit(phys_addr_t first_memblock_base,
	130	phys_addr_t first_memblock_size);
	131
	132	#ifdef CONFIG_PPC64
	133	/* This is our real memory area size on ppc64 server, on embedded, we
	134	* make it match the size our of bolted TLB area
	135	*/
	136	extern u64 ppc64_rma_size;
	137	#endif /* CONFIG_PPC64 */
	138
78f1dbde AK	139	struct mm_struct;
	140	#ifdef CONFIG_DEBUG_VM
	141	extern void assert_pte_locked(struct mm_struct *mm, unsigned long addr);
	142	#else /* CONFIG_DEBUG_VM */
	143	static inline void assert_pte_locked(struct mm_struct *mm, unsigned long addr)
	144	{
	145	}
	146	#endif /* !CONFIG_DEBUG_VM */
	147
7c03d653 BH	148	#endif /* !__ASSEMBLY__ */
7c03d653 BH	149
57e2a99f BH	150	/* The kernel use the constants below to index in the page sizes array.
	151	* The use of fixed constants for this purpose is better for performances
	152	* of the low level hash refill handlers.
	153	*
	154	* A non supported page size has a "shift" field set to 0
	155	*
	156	* Any new page size being implemented can get a new entry in here. Whether
	157	* the kernel will use it or not is a different matter though. The actual page
	158	* size used by hugetlbfs is not defined here and may be made variable
	159	*
	160	* Note: This array ended up being a false good idea as it's growing to the
	161	* point where I wonder if we should replace it with something different,
	162	* to think about, feedback welcome. --BenH.
	163	*/
	164
a8b91e43	165	/* These are #defines as they have to be used in assembly */
57e2a99f BH	166	#define MMU_PAGE_4K 0
	167	#define MMU_PAGE_16K 1
	168	#define MMU_PAGE_64K 2
	169	#define MMU_PAGE_64K_AP 3 /* "Admixed pages" (hash64 only) */
	170	#define MMU_PAGE_256K 4
	171	#define MMU_PAGE_1M 5
28efc35f SW	172	#define MMU_PAGE_2M 6
	173	#define MMU_PAGE_4M 7
	174	#define MMU_PAGE_8M 8
	175	#define MMU_PAGE_16M 9
	176	#define MMU_PAGE_64M 10
	177	#define MMU_PAGE_256M 11
	178	#define MMU_PAGE_1G 12
	179	#define MMU_PAGE_16G 13
	180	#define MMU_PAGE_64G 14
	181
	182	#define MMU_PAGE_COUNT 15
7c03d653	183
11a6f6ab AK	184	#ifdef CONFIG_PPC_BOOK3S_64
	185	#include <asm/book3s/64/mmu.h>
	186	#else /* CONFIG_PPC_BOOK3S_64 */
	187
	188	#endif
	189
	190	#if defined(CONFIG_PPC_STD_MMU_32)
4db68bfe	191	/* 32-bit classic hash table MMU */
f64e8084	192	#include <asm/book3s/32/mmu-hash.h>
4d922c8d JB	193	#elif defined(CONFIG_40x)
	194	/* 40x-style software loaded TLB */
	195	# include <asm/mmu-40x.h>
57d7909e DG	196	#elif defined(CONFIG_44x)
	197	/* 44x-style software loaded TLB */
	198	# include <asm/mmu-44x.h>
70fe3af8 KG	199	#elif defined(CONFIG_PPC_BOOK3E_MMU)
	200	/* Freescale Book-E software loaded TLB or Book-3e (ISA 2.06+) MMU */
	201	# include <asm/mmu-book3e.h>
31202345 DG	202	#elif defined (CONFIG_PPC_8xx)
	203	/* Motorola/Freescale 8xx software loaded TLB */
	204	# include <asm/mmu-8xx.h>
1f8d419e	205	#endif
1f8d419e	206
566ca99a AK	207	#ifndef radix_enabled
	208	#define radix_enabled() (0)
	209	#endif
57e2a99f	210
88ced031	211	#endif /* __KERNEL__ */
047ea784	212	#endif /* _ASM_POWERPC_MMU_H_ */