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3b759bd6
WD		 1/*
2 * PowerPC memory management structures
3 */
4
5#ifndef _PPC_MMU_H_
6#define _PPC_MMU_H_
7
8#include <linux/config.h>
9
10#ifndef __ASSEMBLY__
11/* Hardware Page Table Entry */
12typedef struct _PTE {
13#ifdef CONFIG_PPC64BRIDGE
14 unsigned long long vsid:52;
15 unsigned long api:5;
16 unsigned long :5;
17 unsigned long h:1;
18 unsigned long v:1;
19 unsigned long long rpn:52;
20#else /* CONFIG_PPC64BRIDGE */
21 unsigned long v:1; /* Entry is valid */
22 unsigned long vsid:24; /* Virtual segment identifier */
23 unsigned long h:1; /* Hash algorithm indicator */
24 unsigned long api:6; /* Abbreviated page index */
25 unsigned long rpn:20; /* Real (physical) page number */
26#endif /* CONFIG_PPC64BRIDGE */
27 unsigned long :3; /* Unused */
28 unsigned long r:1; /* Referenced */
29 unsigned long c:1; /* Changed */
30 unsigned long w:1; /* Write-thru cache mode */
31 unsigned long i:1; /* Cache inhibited */
32 unsigned long m:1; /* Memory coherence */
33 unsigned long g:1; /* Guarded */
34 unsigned long :1; /* Unused */
35 unsigned long pp:2; /* Page protection */
36} PTE;
37
38/* Values for PP (assumes Ks=0, Kp=1) */
39#define PP_RWXX 0 /* Supervisor read/write, User none */
40#define PP_RWRX 1 /* Supervisor read/write, User read */
41#define PP_RWRW 2 /* Supervisor read/write, User read/write */
42#define PP_RXRX 3 /* Supervisor read, User read */
43
44/* Segment Register */
45typedef struct _SEGREG {
46 unsigned long t:1; /* Normal or I/O type */
47 unsigned long ks:1; /* Supervisor 'key' (normally 0) */
48 unsigned long kp:1; /* User 'key' (normally 1) */
49 unsigned long n:1; /* No-execute */
50 unsigned long :4; /* Unused */
51 unsigned long vsid:24; /* Virtual Segment Identifier */
52} SEGREG;
53
54/* Block Address Translation (BAT) Registers */
55typedef struct _P601_BATU { /* Upper part of BAT for 601 processor */
56 unsigned long bepi:15; /* Effective page index (virtual address) */
57 unsigned long :8; /* unused */
58 unsigned long w:1;
59 unsigned long i:1; /* Cache inhibit */
60 unsigned long m:1; /* Memory coherence */
61 unsigned long ks:1; /* Supervisor key (normally 0) */
62 unsigned long kp:1; /* User key (normally 1) */
63 unsigned long pp:2; /* Page access protections */
64} P601_BATU;
65
66typedef struct _BATU { /* Upper part of BAT (all except 601) */
67#ifdef CONFIG_PPC64BRIDGE
68 unsigned long long bepi:47;
69#else /* CONFIG_PPC64BRIDGE */
70 unsigned long bepi:15; /* Effective page index (virtual address) */
71#endif /* CONFIG_PPC64BRIDGE */
72 unsigned long :4; /* Unused */
73 unsigned long bl:11; /* Block size mask */
74 unsigned long vs:1; /* Supervisor valid */
75 unsigned long vp:1; /* User valid */
76} BATU;
77
78typedef struct _P601_BATL { /* Lower part of BAT for 601 processor */
79 unsigned long brpn:15; /* Real page index (physical address) */
80 unsigned long :10; /* Unused */
81 unsigned long v:1; /* Valid bit */
82 unsigned long bl:6; /* Block size mask */
83} P601_BATL;
84
85typedef struct _BATL { /* Lower part of BAT (all except 601) */
86#ifdef CONFIG_PPC64BRIDGE
87 unsigned long long brpn:47;
88#else /* CONFIG_PPC64BRIDGE */
89 unsigned long brpn:15; /* Real page index (physical address) */
90#endif /* CONFIG_PPC64BRIDGE */
91 unsigned long :10; /* Unused */
92 unsigned long w:1; /* Write-thru cache */
93 unsigned long i:1; /* Cache inhibit */
94 unsigned long m:1; /* Memory coherence */
95 unsigned long g:1; /* Guarded (MBZ in IBAT) */
96 unsigned long :1; /* Unused */
97 unsigned long pp:2; /* Page access protections */
98} BATL;
99
100typedef struct _BAT {
101 BATU batu; /* Upper register */
102 BATL batl; /* Lower register */
103} BAT;
104
105typedef struct _P601_BAT {
106 P601_BATU batu; /* Upper register */
107 P601_BATL batl; /* Lower register */
108} P601_BAT;
109
110/*
111 * Simulated two-level MMU. This structure is used by the kernel
112 * to keep track of MMU mappings and is used to update/maintain
113 * the hardware HASH table which is really a cache of mappings.
114 *
115 * The simulated structures mimic the hardware available on other
116 * platforms, notably the 80x86 and 680x0.
117 */
118
119typedef struct _pte {
5f3249a0
JL		 120 unsigned long page_num:20;
121 unsigned long flags:12; /* Page flags (some unused bits) */
3b759bd6
WD		 122} pte;
123
124#define PD_SHIFT (10+12) /* Page directory */
125#define PD_MASK 0x02FF
126#define PT_SHIFT (12) /* Page Table */
127#define PT_MASK 0x02FF
128#define PG_SHIFT (12) /* Page Entry */
129
130
131/* MMU context */
132
133typedef struct _MMU_context {
134 SEGREG segs[16]; /* Segment registers */
135 pte **pmap; /* Two-level page-map structure */
136} MMU_context;
137
138extern void _tlbie(unsigned long va); /* invalidate a TLB entry */
139extern void _tlbia(void); /* invalidate all TLB entries */
140
c9315e6b
BB		 141#ifdef CONFIG_ADDR_MAP
142extern void init_addr_map(void);
143#endif
144
3b759bd6
WD		 145typedef enum {
146 IBAT0 = 0, IBAT1, IBAT2, IBAT3,
c148f24c
BB		 147 DBAT0, DBAT1, DBAT2, DBAT3,
148#ifdef CONFIG_HIGH_BATS
149 IBAT4, IBAT5, IBAT6, IBAT7,
150 DBAT4, DBAT5, DBAT6, DBAT7
151#endif
3b759bd6
WD		 152} ppc_bat_t;
153
154extern int read_bat(ppc_bat_t bat, unsigned long *upper, unsigned long *lower);
155extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
d5b9b8cd 156extern void print_bats(void);
3b759bd6
WD		 157
158#endif /* __ASSEMBLY__ */
159
d35ae5a9
BB		 160#define BATU_VS 0x00000002
161#define BATU_VP 0x00000001
162#define BATU_INVALID 0x00000000
163
164#define BATL_WRITETHROUGH 0x00000040
165#define BATL_CACHEINHIBIT 0x00000020
166#define BATL_MEMCOHERENCE 0x00000010
167#define BATL_GUARDEDSTORAGE 0x00000008
168#define BATL_NO_ACCESS 0x00000000
169
170#define BATL_PP_MSK 0x00000003
171#define BATL_PP_00 0x00000000 /* No access */
172#define BATL_PP_01 0x00000001 /* Read-only */
173#define BATL_PP_10 0x00000002 /* Read-write */
174#define BATL_PP_11 0x00000003
175
176#define BATL_PP_NO_ACCESS BATL_PP_00
177#define BATL_PP_RO BATL_PP_01
178#define BATL_PP_RW BATL_PP_10
179
180/* BAT Block size values */
181#define BATU_BL_128K 0x00000000
182#define BATU_BL_256K 0x00000004
183#define BATU_BL_512K 0x0000000c
184#define BATU_BL_1M 0x0000001c
185#define BATU_BL_2M 0x0000003c
186#define BATU_BL_4M 0x0000007c
187#define BATU_BL_8M 0x000000fc
188#define BATU_BL_16M 0x000001fc
189#define BATU_BL_32M 0x000003fc
190#define BATU_BL_64M 0x000007fc
191#define BATU_BL_128M 0x00000ffc
192#define BATU_BL_256M 0x00001ffc
193
194/* Block lengths for processors that support extended block length */
195#ifdef HID0_XBSEN
196#define BATU_BL_512M 0x00003ffc
197#define BATU_BL_1G 0x00007ffc
198#define BATU_BL_2G 0x0000fffc
199#define BATU_BL_4G 0x0001fffc
200#define BATU_BL_MAX BATU_BL_4G
201#else
202#define BATU_BL_MAX BATU_BL_256M
203#endif
3b759bd6
WD		 204
205/* BAT Access Protection */
206#define BPP_XX 0x00 /* No access */
207#define BPP_RX 0x01 /* Read only */
208#define BPP_RW 0x02 /* Read/write */
209
c9315e6b
BB		 210/* Macros to get values from BATs, once data is in the BAT register format */
211#define BATU_VALID(x) (x & 0x3)
212#define BATU_VADDR(x) (x & 0xfffe0000)
213#define BATL_PADDR(x) ((phys_addr_t)((x & 0xfffe0000) \
214 | ((x & 0x0e00ULL) << 24) \
215 | ((x & 0x04ULL) << 30)))
9ff32d8c
TT		 216#define BATU_SIZE(x) (1ULL << (fls((x & BATU_BL_MAX) >> 2) + 17))
217
218/* bytes into BATU_BL */
219#define TO_BATU_BL(x) \
220 (u32)((((1ull << __ilog2_u64((u64)x)) / (128 * 1024)) - 1) * 4)
c9315e6b 221
3b759bd6
WD		 222/* Used to set up SDR1 register */
223#define HASH_TABLE_SIZE_64K 0x00010000
224#define HASH_TABLE_SIZE_128K 0x00020000
225#define HASH_TABLE_SIZE_256K 0x00040000
226#define HASH_TABLE_SIZE_512K 0x00080000
227#define HASH_TABLE_SIZE_1M 0x00100000
228#define HASH_TABLE_SIZE_2M 0x00200000
229#define HASH_TABLE_SIZE_4M 0x00400000
230#define HASH_TABLE_MASK_64K 0x000
231#define HASH_TABLE_MASK_128K 0x001
232#define HASH_TABLE_MASK_256K 0x003
233#define HASH_TABLE_MASK_512K 0x007
234#define HASH_TABLE_MASK_1M 0x00F
235#define HASH_TABLE_MASK_2M 0x01F
236#define HASH_TABLE_MASK_4M 0x03F
237
238/* Control/status registers for the MPC8xx.
239 * A write operation to these registers causes serialized access.
240 * During software tablewalk, the registers used perform mask/shift-add
241 * operations when written/read. A TLB entry is created when the Mx_RPN
242 * is written, and the contents of several registers are used to
243 * create the entry.
244 */
245#define MI_CTR 784 /* Instruction TLB control register */
246#define MI_GPM 0x80000000 /* Set domain manager mode */
247#define MI_PPM 0x40000000 /* Set subpage protection */
248#define MI_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */
249#define MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */
250#define MI_PPCS 0x02000000 /* Use MI_RPN prob/priv state */
251#define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */
252#define MI_RESETVAL 0x00000000 /* Value of register at reset */
253
254/* These are the Ks and Kp from the PowerPC books. For proper operation,
255 * Ks = 0, Kp = 1.
256 */
257#define MI_AP 786
258#define MI_Ks 0x80000000 /* Should not be set */
259#define MI_Kp 0x40000000 /* Should always be set */
260
261/* The effective page number register. When read, contains the information
262 * about the last instruction TLB miss. When MI_RPN is written, bits in
263 * this register are used to create the TLB entry.
264 */
265#define MI_EPN 787
266#define MI_EPNMASK 0xfffff000 /* Effective page number for entry */
267#define MI_EVALID 0x00000200 /* Entry is valid */
268#define MI_ASIDMASK 0x0000000f /* ASID match value */
269 /* Reset value is undefined */
270
271/* A "level 1" or "segment" or whatever you want to call it register.
272 * For the instruction TLB, it contains bits that get loaded into the
273 * TLB entry when the MI_RPN is written.
274 */
275#define MI_TWC 789
276#define MI_APG 0x000001e0 /* Access protection group (0) */
277#define MI_GUARDED 0x00000010 /* Guarded storage */
278#define MI_PSMASK 0x0000000c /* Mask of page size bits */
279#define MI_PS8MEG 0x0000000c /* 8M page size */
280#define MI_PS512K 0x00000004 /* 512K page size */
281#define MI_PS4K_16K 0x00000000 /* 4K or 16K page size */
282#define MI_SVALID 0x00000001 /* Segment entry is valid */
283 /* Reset value is undefined */
284
285/* Real page number. Defined by the pte. Writing this register
286 * causes a TLB entry to be created for the instruction TLB, using
287 * additional information from the MI_EPN, and MI_TWC registers.
288 */
289#define MI_RPN 790
290
291/* Define an RPN value for mapping kernel memory to large virtual
292 * pages for boot initialization. This has real page number of 0,
293 * large page size, shared page, cache enabled, and valid.
294 * Also mark all subpages valid and write access.
295 */
296#define MI_BOOTINIT 0x000001fd
297
298#define MD_CTR 792 /* Data TLB control register */
299#define MD_GPM 0x80000000 /* Set domain manager mode */
300#define MD_PPM 0x40000000 /* Set subpage protection */
301#define MD_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */
302#define MD_WTDEF 0x10000000 /* Set writethrough when MMU dis */
303#define MD_RSV4I 0x08000000 /* Reserve 4 TLB entries */
304#define MD_TWAM 0x04000000 /* Use 4K page hardware assist */
305#define MD_PPCS 0x02000000 /* Use MI_RPN prob/priv state */
306#define MD_IDXMASK 0x00001f00 /* TLB index to be loaded */
307#define MD_RESETVAL 0x04000000 /* Value of register at reset */
308
309#define M_CASID 793 /* Address space ID (context) to match */
310#define MC_ASIDMASK 0x0000000f /* Bits used for ASID value */
311
312
313/* These are the Ks and Kp from the PowerPC books. For proper operation,
314 * Ks = 0, Kp = 1.
315 */
316#define MD_AP 794
317#define MD_Ks 0x80000000 /* Should not be set */
318#define MD_Kp 0x40000000 /* Should always be set */
319
320/* The effective page number register. When read, contains the information
321 * about the last instruction TLB miss. When MD_RPN is written, bits in
322 * this register are used to create the TLB entry.
323 */
324#define MD_EPN 795
325#define MD_EPNMASK 0xfffff000 /* Effective page number for entry */
326#define MD_EVALID 0x00000200 /* Entry is valid */
327#define MD_ASIDMASK 0x0000000f /* ASID match value */
328 /* Reset value is undefined */
329
330/* The pointer to the base address of the first level page table.
331 * During a software tablewalk, reading this register provides the address
332 * of the entry associated with MD_EPN.
333 */
334#define M_TWB 796
335#define M_L1TB 0xfffff000 /* Level 1 table base address */
336#define M_L1INDX 0x00000ffc /* Level 1 index, when read */
337 /* Reset value is undefined */
338
339/* A "level 1" or "segment" or whatever you want to call it register.
340 * For the data TLB, it contains bits that get loaded into the TLB entry
341 * when the MD_RPN is written. It is also provides the hardware assist
342 * for finding the PTE address during software tablewalk.
343 */
344#define MD_TWC 797
345#define MD_L2TB 0xfffff000 /* Level 2 table base address */
346#define MD_L2INDX 0xfffffe00 /* Level 2 index (*pte), when read */
347#define MD_APG 0x000001e0 /* Access protection group (0) */
348#define MD_GUARDED 0x00000010 /* Guarded storage */
349#define MD_PSMASK 0x0000000c /* Mask of page size bits */
350#define MD_PS8MEG 0x0000000c /* 8M page size */
351#define MD_PS512K 0x00000004 /* 512K page size */
352#define MD_PS4K_16K 0x00000000 /* 4K or 16K page size */
353#define MD_WT 0x00000002 /* Use writethrough page attribute */
354#define MD_SVALID 0x00000001 /* Segment entry is valid */
355 /* Reset value is undefined */
356
357
358/* Real page number. Defined by the pte. Writing this register
359 * causes a TLB entry to be created for the data TLB, using
360 * additional information from the MD_EPN, and MD_TWC registers.
361 */
362#define MD_RPN 798
363
364/* This is a temporary storage register that could be used to save
365 * a processor working register during a tablewalk.
366 */
367#define M_TW 799
368
369/*
370 * At present, all PowerPC 400-class processors share a similar TLB
371 * architecture. The instruction and data sides share a unified,
372 * 64-entry, fully-associative TLB which is maintained totally under
373 * software control. In addition, the instruction side has a
374 * hardware-managed, 4-entry, fully- associative TLB which serves as a
375 * first level to the shared TLB. These two TLBs are known as the UTLB
376 * and ITLB, respectively.
377 */
378
379#define PPC4XX_TLB_SIZE 64
380
381/*
382 * TLB entries are defined by a "high" tag portion and a "low" data
383 * portion. On all architectures, the data portion is 32-bits.
384 *
385 * TLB entries are managed entirely under software control by reading,
386 * writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx
387 * instructions.
388 */
389
42d1f039 390/*
1d47273d 391 * FSL Book-E support
42d1f039
WD		 392 */
393
c2287af1
KG		 394#define MAS0_TLBSEL_MSK 0x30000000
395#define MAS0_TLBSEL(x) ((x << 28) & MAS0_TLBSEL_MSK)
396#define MAS0_ESEL_MSK 0x0FFF0000
397#define MAS0_ESEL(x) ((x << 16) & MAS0_ESEL_MSK)
1d47273d
KG		 398#define MAS0_NV(x) ((x) & 0x00000FFF)
399
53677ef1 400#define MAS1_VALID 0x80000000
1d47273d
KG		 401#define MAS1_IPROT 0x40000000
402#define MAS1_TID(x) ((x << 16) & 0x3FFF0000)
403#define MAS1_TS 0x00001000
404#define MAS1_TSIZE(x) ((x << 8) & 0x00000F00)
405
406#define MAS2_EPN 0xFFFFF000
407#define MAS2_X0 0x00000040
408#define MAS2_X1 0x00000020
409#define MAS2_W 0x00000010
410#define MAS2_I 0x00000008
411#define MAS2_M 0x00000004
412#define MAS2_G 0x00000002
413#define MAS2_E 0x00000001
414
415#define MAS3_RPN 0xFFFFF000
416#define MAS3_U0 0x00000200
417#define MAS3_U1 0x00000100
418#define MAS3_U2 0x00000080
419#define MAS3_U3 0x00000040
420#define MAS3_UX 0x00000020
421#define MAS3_SX 0x00000010
422#define MAS3_UW 0x00000008
423#define MAS3_SW 0x00000004
424#define MAS3_UR 0x00000002
425#define MAS3_SR 0x00000001
426
427#define MAS4_TLBSELD(x) MAS0_TLBSEL(x)
428#define MAS4_TIDDSEL 0x000F0000
429#define MAS4_TSIZED(x) MAS1_TSIZE(x)
430#define MAS4_X0D 0x00000040
431#define MAS4_X1D 0x00000020
432#define MAS4_WD 0x00000010
433#define MAS4_ID 0x00000008
434#define MAS4_MD 0x00000004
435#define MAS4_GD 0x00000002
436#define MAS4_ED 0x00000001
437
438#define MAS6_SPID0 0x3FFF0000
439#define MAS6_SPID1 0x00007FFE
440#define MAS6_SAS 0x00000001
441#define MAS6_SPID MAS6_SPID0
442
443#define MAS7_RPN 0xFFFFFFFF
42d1f039 444
2146cf56
KG		 445#define FSL_BOOKE_MAS0(tlbsel,esel,nv) \
446 (MAS0_TLBSEL(tlbsel) | MAS0_ESEL(esel) | MAS0_NV(nv))
447#define FSL_BOOKE_MAS1(v,iprot,tid,ts,tsize) \
448 ((((v) << 31) & MAS1_VALID) |\
449 (((iprot) << 30) & MAS1_IPROT) |\
450 (MAS1_TID(tid)) |\
451 (((ts) << 12) & MAS1_TS) |\
452 (MAS1_TSIZE(tsize)))
453#define FSL_BOOKE_MAS2(epn, wimge) \
454 (((epn) & MAS3_RPN) | (wimge))
455#define FSL_BOOKE_MAS3(rpn, user, perms) \
456 (((rpn) & MAS3_RPN) | (user) | (perms))
d30f9043
KG		 457#define FSL_BOOKE_MAS7(rpn) \
458 (((u64)(rpn)) >> 32)
2146cf56 459
42d1f039
WD		 460#define BOOKE_PAGESZ_1K 0
461#define BOOKE_PAGESZ_4K 1
462#define BOOKE_PAGESZ_16K 2
463#define BOOKE_PAGESZ_64K 3
464#define BOOKE_PAGESZ_256K 4
465#define BOOKE_PAGESZ_1M 5
466#define BOOKE_PAGESZ_4M 6
467#define BOOKE_PAGESZ_16M 7
468#define BOOKE_PAGESZ_64M 8
469#define BOOKE_PAGESZ_256M 9
45cef612
AF		 470#define BOOKE_PAGESZ_1G 10
471#define BOOKE_PAGESZ_4G 11
1d47273d
KG		 472#define BOOKE_PAGESZ_16GB 12
473#define BOOKE_PAGESZ_64GB 13
474#define BOOKE_PAGESZ_256GB 14
475#define BOOKE_PAGESZ_1TB 15
42d1f039 476
44a23cfd
KG		 477#ifdef CONFIG_E500
478#ifndef __ASSEMBLY__
479extern void set_tlb(u8 tlb, u32 epn, u64 rpn,
480 u8 perms, u8 wimge,
481 u8 ts, u8 esel, u8 tsize, u8 iprot);
482extern void disable_tlb(u8 esel);
483extern void invalidate_tlb(u8 tlb);
484extern void init_tlbs(void);
c2287af1 485extern int find_tlb_idx(void *addr, u8 tlbsel);
94e9411b
KG		 486extern void init_used_tlb_cams(void);
487extern int find_free_tlbcam(void);
c9315e6b 488
6fb1b734 489extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg);
44a23cfd 490
d30f9043
KG		 491extern void write_tlb(u32 _mas0, u32 _mas1, u32 _mas2, u32 _mas3, u32 _mas7);
492
44a23cfd 493#define SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz, _iprot) \
206af352
KG		 494 { .mas0 = FSL_BOOKE_MAS0(_tlb, _esel, 0), \
495 .mas1 = FSL_BOOKE_MAS1(1, _iprot, 0, _ts, _sz), \
496 .mas2 = FSL_BOOKE_MAS2(_epn, _wimge), \
497 .mas3 = FSL_BOOKE_MAS3(_rpn, 0, _perms), \
498 .mas7 = FSL_BOOKE_MAS7(_rpn), }
44a23cfd
KG		 499
500struct fsl_e_tlb_entry {
206af352
KG		 501 u32 mas0;
502 u32 mas1;
503 u32 mas2;
504 u32 mas3;
505 u32 mas7;
44a23cfd
KG		 506};
507
508extern struct fsl_e_tlb_entry tlb_table[];
509extern int num_tlb_entries;
510#endif
511#endif
512
9d142ea8 513#ifdef CONFIG_E300
debb7354 514#define LAWAR_EN 0x80000000
42d1f039
WD		 515#define LAWAR_SIZE 0x0000003F
516
517#define LAWAR_TRGT_IF_PCI 0x00000000
0ac6f8b7 518#define LAWAR_TRGT_IF_PCI1 0x00000000
42d1f039 519#define LAWAR_TRGT_IF_PCIX 0x00000000
0ac6f8b7 520#define LAWAR_TRGT_IF_PCI2 0x00100000
a853d56c
KG		 521#define LAWAR_TRGT_IF_PCIE1 0x00200000
522#define LAWAR_TRGT_IF_PCIE2 0x00100000
523#define LAWAR_TRGT_IF_PCIE3 0x00300000
42d1f039
WD		 524#define LAWAR_TRGT_IF_LBC 0x00400000
525#define LAWAR_TRGT_IF_CCSR 0x00800000
debb7354 526#define LAWAR_TRGT_IF_DDR_INTERLEAVED 0x00B00000
42d1f039
WD		 527#define LAWAR_TRGT_IF_RIO 0x00c00000
528#define LAWAR_TRGT_IF_DDR 0x00f00000
2c33e8a1
JL		 529#define LAWAR_TRGT_IF_DDR1 0x00f00000
530#define LAWAR_TRGT_IF_DDR2 0x01600000
42d1f039
WD		 531
532#define LAWAR_SIZE_BASE 0xa
533#define LAWAR_SIZE_4K (LAWAR_SIZE_BASE+1)
534#define LAWAR_SIZE_8K (LAWAR_SIZE_BASE+2)
535#define LAWAR_SIZE_16K (LAWAR_SIZE_BASE+3)
536#define LAWAR_SIZE_32K (LAWAR_SIZE_BASE+4)
537#define LAWAR_SIZE_64K (LAWAR_SIZE_BASE+5)
538#define LAWAR_SIZE_128K (LAWAR_SIZE_BASE+6)
539#define LAWAR_SIZE_256K (LAWAR_SIZE_BASE+7)
540#define LAWAR_SIZE_512K (LAWAR_SIZE_BASE+8)
541#define LAWAR_SIZE_1M (LAWAR_SIZE_BASE+9)
542#define LAWAR_SIZE_2M (LAWAR_SIZE_BASE+10)
543#define LAWAR_SIZE_4M (LAWAR_SIZE_BASE+11)
544#define LAWAR_SIZE_8M (LAWAR_SIZE_BASE+12)
545#define LAWAR_SIZE_16M (LAWAR_SIZE_BASE+13)
546#define LAWAR_SIZE_32M (LAWAR_SIZE_BASE+14)
547#define LAWAR_SIZE_64M (LAWAR_SIZE_BASE+15)
548#define LAWAR_SIZE_128M (LAWAR_SIZE_BASE+16)
549#define LAWAR_SIZE_256M (LAWAR_SIZE_BASE+17)
550#define LAWAR_SIZE_512M (LAWAR_SIZE_BASE+18)
551#define LAWAR_SIZE_1G (LAWAR_SIZE_BASE+19)
552#define LAWAR_SIZE_2G (LAWAR_SIZE_BASE+20)
2c33e8a1
JL		 553#define LAWAR_SIZE_4G (LAWAR_SIZE_BASE+21)
554#define LAWAR_SIZE_8G (LAWAR_SIZE_BASE+22)
555#define LAWAR_SIZE_16G (LAWAR_SIZE_BASE+23)
556#define LAWAR_SIZE_32G (LAWAR_SIZE_BASE+24)
002741ae 557#endif
42d1f039 558
4037ed3b
SR		 559#ifdef CONFIG_440
560/* General */
561#define TLB_VALID 0x00000200
562
563/* Supported page sizes */
564
565#define SZ_1K 0x00000000
566#define SZ_4K 0x00000010
567#define SZ_16K 0x00000020
568#define SZ_64K 0x00000030
569#define SZ_256K 0x00000040
570#define SZ_1M 0x00000050
571#define SZ_16M 0x00000070
572#define SZ_256M 0x00000090
573
574/* Storage attributes */
575#define SA_W 0x00000800 /* Write-through */
576#define SA_I 0x00000400 /* Caching inhibited */
577#define SA_M 0x00000200 /* Memory coherence */
578#define SA_G 0x00000100 /* Guarded */
579#define SA_E 0x00000080 /* Endian */
580
581/* Access control */
582#define AC_X 0x00000024 /* Execute */
583#define AC_W 0x00000012 /* Write */
584#define AC_R 0x00000009 /* Read */
585
586/* Some handy macros */
587
588#define EPN(e) ((e) & 0xfffffc00)
589#define TLB0(epn,sz) ((EPN((epn)) | (sz) | TLB_VALID ))
590#define TLB1(rpn,erpn) (((rpn) & 0xfffffc00) | (erpn))
591#define TLB2(a) ((a) & 0x00000fbf)
592
593#define tlbtab_start\
594 mflr r1 ;\
595 bl 0f ;
596
597#define tlbtab_end\
598 .long 0, 0, 0 ;\
5990: mflr r0 ;\
600 mtlr r1 ;\
601 blr ;
602
603#define tlbentry(epn,sz,rpn,erpn,attr)\
604 .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
605
606/*----------------------------------------------------------------------------+
607| TLB specific defines.
608+----------------------------------------------------------------------------*/
84a999b6
SR		 609#define TLB_256MB_ALIGN_MASK 0xFF0000000ULL
610#define TLB_16MB_ALIGN_MASK 0xFFF000000ULL
611#define TLB_1MB_ALIGN_MASK 0xFFFF00000ULL
612#define TLB_256KB_ALIGN_MASK 0xFFFFC0000ULL
613#define TLB_64KB_ALIGN_MASK 0xFFFFF0000ULL
614#define TLB_16KB_ALIGN_MASK 0xFFFFFC000ULL
615#define TLB_4KB_ALIGN_MASK 0xFFFFFF000ULL
616#define TLB_1KB_ALIGN_MASK 0xFFFFFFC00ULL
4037ed3b
SR		 617#define TLB_256MB_SIZE 0x10000000
618#define TLB_16MB_SIZE 0x01000000
619#define TLB_1MB_SIZE 0x00100000
620#define TLB_256KB_SIZE 0x00040000
621#define TLB_64KB_SIZE 0x00010000
622#define TLB_16KB_SIZE 0x00004000
623#define TLB_4KB_SIZE 0x00001000
624#define TLB_1KB_SIZE 0x00000400
625
626#define TLB_WORD0_EPN_MASK 0xFFFFFC00
627#define TLB_WORD0_EPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00)
628#define TLB_WORD0_EPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00)
629#define TLB_WORD0_V_MASK 0x00000200
630#define TLB_WORD0_V_ENABLE 0x00000200
631#define TLB_WORD0_V_DISABLE 0x00000000
632#define TLB_WORD0_TS_MASK 0x00000100
633#define TLB_WORD0_TS_1 0x00000100
634#define TLB_WORD0_TS_0 0x00000000
635#define TLB_WORD0_SIZE_MASK 0x000000F0
636#define TLB_WORD0_SIZE_1KB 0x00000000
637#define TLB_WORD0_SIZE_4KB 0x00000010
638#define TLB_WORD0_SIZE_16KB 0x00000020
639#define TLB_WORD0_SIZE_64KB 0x00000030
640#define TLB_WORD0_SIZE_256KB 0x00000040
641#define TLB_WORD0_SIZE_1MB 0x00000050
642#define TLB_WORD0_SIZE_16MB 0x00000070
643#define TLB_WORD0_SIZE_256MB 0x00000090
644#define TLB_WORD0_TPAR_MASK 0x0000000F
645#define TLB_WORD0_TPAR_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0)
646#define TLB_WORD0_TPAR_DECODE(n) ((((unsigned long)(n))>>0)&0x0F)
647
648#define TLB_WORD1_RPN_MASK 0xFFFFFC00
649#define TLB_WORD1_RPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00)
650#define TLB_WORD1_RPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00)
651#define TLB_WORD1_PAR1_MASK 0x00000300
652#define TLB_WORD1_PAR1_ENCODE(n) ((((unsigned long)(n))&0x03)<<8)
653#define TLB_WORD1_PAR1_DECODE(n) ((((unsigned long)(n))>>8)&0x03)
654#define TLB_WORD1_PAR1_0 0x00000000
655#define TLB_WORD1_PAR1_1 0x00000100
656#define TLB_WORD1_PAR1_2 0x00000200
657#define TLB_WORD1_PAR1_3 0x00000300
658#define TLB_WORD1_ERPN_MASK 0x0000000F
659#define TLB_WORD1_ERPN_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0)
660#define TLB_WORD1_ERPN_DECODE(n) ((((unsigned long)(n))>>0)&0x0F)
661
662#define TLB_WORD2_PAR2_MASK 0xC0000000
663#define TLB_WORD2_PAR2_ENCODE(n) ((((unsigned long)(n))&0x03)<<30)
664#define TLB_WORD2_PAR2_DECODE(n) ((((unsigned long)(n))>>30)&0x03)
665#define TLB_WORD2_PAR2_0 0x00000000
666#define TLB_WORD2_PAR2_1 0x40000000
667#define TLB_WORD2_PAR2_2 0x80000000
668#define TLB_WORD2_PAR2_3 0xC0000000
669#define TLB_WORD2_U0_MASK 0x00008000
670#define TLB_WORD2_U0_ENABLE 0x00008000
671#define TLB_WORD2_U0_DISABLE 0x00000000
672#define TLB_WORD2_U1_MASK 0x00004000
673#define TLB_WORD2_U1_ENABLE 0x00004000
674#define TLB_WORD2_U1_DISABLE 0x00000000
675#define TLB_WORD2_U2_MASK 0x00002000
676#define TLB_WORD2_U2_ENABLE 0x00002000
677#define TLB_WORD2_U2_DISABLE 0x00000000
678#define TLB_WORD2_U3_MASK 0x00001000
679#define TLB_WORD2_U3_ENABLE 0x00001000
680#define TLB_WORD2_U3_DISABLE 0x00000000
681#define TLB_WORD2_W_MASK 0x00000800
682#define TLB_WORD2_W_ENABLE 0x00000800
683#define TLB_WORD2_W_DISABLE 0x00000000
684#define TLB_WORD2_I_MASK 0x00000400
685#define TLB_WORD2_I_ENABLE 0x00000400
686#define TLB_WORD2_I_DISABLE 0x00000000
687#define TLB_WORD2_M_MASK 0x00000200
688#define TLB_WORD2_M_ENABLE 0x00000200
689#define TLB_WORD2_M_DISABLE 0x00000000
690#define TLB_WORD2_G_MASK 0x00000100
691#define TLB_WORD2_G_ENABLE 0x00000100
692#define TLB_WORD2_G_DISABLE 0x00000000
693#define TLB_WORD2_E_MASK 0x00000080
694#define TLB_WORD2_E_ENABLE 0x00000080
695#define TLB_WORD2_E_DISABLE 0x00000000
696#define TLB_WORD2_UX_MASK 0x00000020
697#define TLB_WORD2_UX_ENABLE 0x00000020
698#define TLB_WORD2_UX_DISABLE 0x00000000
699#define TLB_WORD2_UW_MASK 0x00000010
700#define TLB_WORD2_UW_ENABLE 0x00000010
701#define TLB_WORD2_UW_DISABLE 0x00000000
702#define TLB_WORD2_UR_MASK 0x00000008
703#define TLB_WORD2_UR_ENABLE 0x00000008
704#define TLB_WORD2_UR_DISABLE 0x00000000
705#define TLB_WORD2_SX_MASK 0x00000004
706#define TLB_WORD2_SX_ENABLE 0x00000004
707#define TLB_WORD2_SX_DISABLE 0x00000000
708#define TLB_WORD2_SW_MASK 0x00000002
709#define TLB_WORD2_SW_ENABLE 0x00000002
710#define TLB_WORD2_SW_DISABLE 0x00000000
711#define TLB_WORD2_SR_MASK 0x00000001
712#define TLB_WORD2_SR_ENABLE 0x00000001
713#define TLB_WORD2_SR_DISABLE 0x00000000
714
6c5879f3
MB		 715/*----------------------------------------------------------------------------+
716| Following instructions are not available in Book E mode of the GNU assembler.
717+----------------------------------------------------------------------------*/
718#define DCCCI(ra,rb) .long 0x7c000000|\
719 (ra<<16)|(rb<<11)|(454<<1)
720
721#define ICCCI(ra,rb) .long 0x7c000000|\
722 (ra<<16)|(rb<<11)|(966<<1)
723
724#define DCREAD(rt,ra,rb) .long 0x7c000000|\
725 (rt<<21)|(ra<<16)|(rb<<11)|(486<<1)
726
727#define ICREAD(ra,rb) .long 0x7c000000|\
728 (ra<<16)|(rb<<11)|(998<<1)
729
730#define TLBSX(rt,ra,rb) .long 0x7c000000|\
731 (rt<<21)|(ra<<16)|(rb<<11)|(914<<1)
732
733#define TLBWE(rs,ra,ws) .long 0x7c000000|\
734 (rs<<21)|(ra<<16)|(ws<<11)|(978<<1)
735
736#define TLBRE(rt,ra,ws) .long 0x7c000000|\
737 (rt<<21)|(ra<<16)|(ws<<11)|(946<<1)
738
739#define TLBSXDOT(rt,ra,rb) .long 0x7c000001|\
740 (rt<<21)|(ra<<16)|(rb<<11)|(914<<1)
741
742#define MSYNC .long 0x7c000000|\
743 (598<<1)
744
53677ef1 745#define MBAR_INST .long 0x7c000000|\
6c5879f3
MB		 746 (854<<1)
747
4037ed3b
SR		 748#ifndef __ASSEMBLY__
749/* Prototypes */
750void mttlb1(unsigned long index, unsigned long value);
751void mttlb2(unsigned long index, unsigned long value);
752void mttlb3(unsigned long index, unsigned long value);
753unsigned long mftlb1(unsigned long index);
754unsigned long mftlb2(unsigned long index);
755unsigned long mftlb3(unsigned long index);
5743a920 756
84a999b6 757void program_tlb(u64 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
5743a920 758void remove_tlb(u32 vaddr, u32 size);
483e09a2 759void change_tlb(u32 vaddr, u32 size, u32 tlb_word2_i_value);
4037ed3b 760#endif /* __ASSEMBLY__ */
6c5879f3 761
4037ed3b 762#endif /* CONFIG_440 */
3b759bd6 763#endif /* _PPC_MMU_H_ */
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