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5e7abce9 SR |
1 | /* |
2 | * (C) Copyright 2010 | |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
4 | * | |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
5e7abce9 SR |
6 | */ |
7 | ||
8 | #ifndef _PPC440EP_GR_H_ | |
9 | #define _PPC440EP_GR_H_ | |
10 | ||
11 | #define CONFIG_SDRAM_PPC4xx_IBM_DDR /* IBM DDR controller */ | |
12 | ||
13 | #define CONFIG_NAND_NDFC | |
14 | ||
5e7abce9 SR |
15 | /* |
16 | * Some SoC specific registers (not common for all 440 SoC's) | |
17 | */ | |
5e7abce9 | 18 | |
550650dd SR |
19 | /* Memory mapped registers */ |
20 | #define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* Internal Peripherals */ | |
21 | ||
22 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300) | |
23 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0400) | |
24 | #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_PERIPHERAL_BASE + 0x0500) | |
25 | #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_PERIPHERAL_BASE + 0x0600) | |
26 | ||
27 | #define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0b00) | |
28 | #define GPIO1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0c00) | |
29 | ||
30 | /* SDR's */ | |
5e7abce9 SR |
31 | #define SDR0_PCI0 0x0300 |
32 | #define SDR0_SDSTP2 0x4001 | |
33 | #define SDR0_SDSTP3 0x4003 | |
34 | ||
35 | #define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 21) | |
36 | #define SDR0_SDSTP1_PAME_MASK (0x80000000 >> 27) | |
37 | ||
38 | /* Pin Function Control Register 1 */ | |
39 | #define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */ | |
40 | #define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */ | |
41 | #define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */ | |
42 | #define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */ | |
43 | #define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */ | |
44 | #define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */ | |
45 | #define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */ | |
46 | #define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */ | |
47 | #define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */ | |
48 | #define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */ | |
49 | #define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */ | |
50 | #define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */ | |
51 | #define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold | |
52 | Req Selection */ | |
53 | #define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */ | |
54 | #define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */ | |
55 | #define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) | |
56 | Selection */ | |
57 | #define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */ | |
58 | #define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */ | |
59 | #define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) | |
60 | Selection */ | |
61 | #define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. | |
62 | Selected */ | |
63 | #define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */ | |
64 | #define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject | |
65 | Selection */ | |
66 | #define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject | |
67 | Disable */ | |
68 | #define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject | |
69 | Enable */ | |
70 | #define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor Enable | |
71 | Selection */ | |
72 | #define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor | |
73 | Enable */ | |
74 | #define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor | |
75 | Enable */ | |
76 | #define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation | |
77 | Gated In */ | |
78 | ||
79 | /* USB Control Register */ | |
80 | #define SDR0_USB0_USB_DEVSEL_MASK 0x00000002 /* USB Device Selection */ | |
81 | #define SDR0_USB0_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */ | |
82 | #define SDR0_USB0_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */ | |
83 | #define SDR0_USB0_LEEN_MASK 0x00000001 /* Little Endian selection */ | |
84 | #define SDR0_USB0_LEEN_DISABLE 0x00000000 /* Little Endian Disable */ | |
85 | #define SDR0_USB0_LEEN_ENABLE 0x00000001 /* Little Endian Enable */ | |
86 | ||
87 | /* Miscealleneaous Function Reg. */ | |
88 | #define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */ | |
89 | #define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000 | |
90 | #define SDR0_MFR_ETH1_CLK_SEL_MASK 0x04000000 /* Ethernet1 Clock Select */ | |
91 | #define SDR0_MFR_ETH1_CLK_SEL_EXT 0x00000000 | |
92 | #define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */ | |
93 | #define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */ | |
94 | #define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */ | |
95 | #define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */ | |
96 | #define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */ | |
97 | #define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */ | |
98 | #define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */ | |
99 | #define SDR0_MFR_ZM_ENCODE(n) ((((u32)(n)) & 0x3) << 24) | |
100 | #define SDR0_MFR_ZM_DECODE(n) ((((u32)(n)) << 24) & 0x3) | |
101 | ||
102 | #define SDR0_MFR_ERRATA3_EN0 0x00800000 | |
103 | #define SDR0_MFR_ERRATA3_EN1 0x00400000 | |
104 | #define SDR0_MFR_PKT_REJ_MASK 0x00180000 /* Pkt Rej. Enable Mask */ | |
105 | #define SDR0_MFR_PKT_REJ_EN 0x00180000 /* Pkt Rej. Ena. on both EMAC3 0-1 */ | |
106 | #define SDR0_MFR_PKT_REJ_EN0 0x00100000 /* Pkt Rej. Enable on EMAC3(0) */ | |
107 | #define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */ | |
108 | #define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */ | |
109 | ||
110 | /* CUST0 Customer Configuration Register0 */ | |
111 | #define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */ | |
112 | #define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */ | |
113 | #define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */ | |
114 | #define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */ | |
115 | ||
116 | #define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */ | |
117 | #define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */ | |
118 | #define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */ | |
119 | ||
120 | #define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */ | |
121 | #define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */ | |
122 | #define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */ | |
123 | ||
124 | #define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */ | |
125 | #define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((u32)(n)) & 0xF) << 24) | |
126 | #define SDR0_CUST0_NDFC_BP_DECODE(n) ((((u32)(n)) >> 24) & 0xF) | |
127 | ||
128 | #define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */ | |
129 | #define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((u32)(n)) & 0x3) << 22) | |
130 | #define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((u32)(n)) >> 22) & 0x3) | |
131 | ||
132 | #define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */ | |
133 | #define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */ | |
134 | #define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */ | |
135 | ||
136 | #define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */ | |
137 | #define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */ | |
138 | #define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */ | |
139 | ||
140 | #define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */ | |
141 | #define SDR0_CUST0_NDRSC_ENCODE(n) ((((u32)(n)) & 0xFFF) << 4) | |
142 | #define SDR0_CUST0_NDRSC_DECODE(n) ((((u32)(n)) >> 4) & 0xFFF) | |
143 | ||
144 | #define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */ | |
145 | #define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */ | |
146 | #define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /*All Chip Select Gating Enable*/ | |
147 | #define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */ | |
148 | #define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */ | |
149 | #define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */ | |
150 | #define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */ | |
151 | ||
152 | #define SDR0_SRST_DMC 0x00200000 | |
153 | ||
154 | #define PLLSYS0_ENG_MASK 0x80000000 /* 0 = SysClk, 1 = PLL VCO */ | |
155 | #define PLLSYS0_SRC_MASK 0x40000000 /* 0 = PLL A, 1 = PLL B */ | |
156 | #define PLLSYS0_SEL_MASK 0x38000000 /* 0 = PLL, 1 = CPU, 5 = PerClk */ | |
157 | #define PLLSYS0_TUNE_MASK 0x07fe0000 /* PLL Tune bits */ | |
158 | #define PLLSYS0_FB_DIV_MASK 0x0001f000 /* Feedback divisor */ | |
159 | #define PLLSYS0_FWD_DIV_A_MASK 0x00000f00 /* Fwd Div A */ | |
160 | #define PLLSYS0_FWD_DIV_B_MASK 0x000000e0 /* Fwd Div B */ | |
161 | #define PLLSYS0_PRI_DIV_B_MASK 0x0000001c /* PLL Primary Divisor B */ | |
162 | #define PLLSYS0_OPB_DIV_MASK 0x00000003 /* OPB Divisor */ | |
163 | ||
164 | #define PLLC_ENG_MASK 0x20000000 /* PLL primary forward divisor source */ | |
165 | #define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */ | |
166 | #define PLLD_FBDV_MASK 0x1f000000 /* PLL Feedback Divisor */ | |
167 | #define PLLD_FWDVA_MASK 0x000f0000 /* PLL Forward Divisor A */ | |
168 | #define PLLD_FWDVB_MASK 0x00000700 /* PLL Forward Divisor B */ | |
169 | #define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */ | |
170 | ||
171 | #define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */ | |
16263087 | 172 | #define PERDV_MASK 0x07000000 /* Peripheral Clock Divisor */ |
5e7abce9 SR |
173 | #define PRADV_MASK 0x07000000 /* Primary Divisor A */ |
174 | #define PRBDV_MASK 0x07000000 /* Primary Divisor B */ | |
175 | #define SPCID_MASK 0x03000000 /* Sync PCI Divisor */ | |
176 | ||
177 | /* Strap 1 Register */ | |
178 | #define PLLSYS1_LF_DIV_MASK 0xfc000000 /* PLL Local Feedback Divisor */ | |
179 | #define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */ | |
180 | #define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */ | |
181 | #define PLLSYS1_RW_MASK 0x00300000 /* ROM width */ | |
16263087 | 182 | #define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Address reset vector */ |
5e7abce9 SR |
183 | #define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */ |
184 | #define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */ | |
185 | #define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */ | |
186 | #define PLLSYS1_PCWE_MASK 0x00008000 /* PCI local cpu wait enable */ | |
187 | #define PLLSYS1_PPIM_MASK 0x00007800 /* PCI inbound map */ | |
188 | #define PLLSYS1_PR64E_MASK 0x00000400 /* PCI init Req64 enable */ | |
189 | #define PLLSYS1_PXFS_MASK 0x00000300 /* PCI-X Freq Sel */ | |
190 | #define PLLSYS1_RSVD_MASK 0x00000080 /* RSVD */ | |
191 | #define PLLSYS1_PDM_MASK 0x00000040 /* PCI-X Driver Mode */ | |
192 | #define PLLSYS1_EPS_MASK 0x00000038 /* Ethernet Pin Select */ | |
193 | #define PLLSYS1_RMII_MASK 0x00000004 /* RMII Mode */ | |
194 | #define PLLSYS1_TRE_MASK 0x00000002 /* GPIO Trace Enable */ | |
195 | #define PLLSYS1_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */ | |
196 | ||
197 | #define CPR0_ICFG_RLI_MASK 0x80000000 | |
198 | #define CPR0_ICFG_ICS_MASK 0x00000007 | |
199 | #define CPR0_SPCID_SPCIDV0_MASK 0x03000000 | |
200 | #define CPR0_SPCID_SPCIDV0_DIV1 0x01000000 | |
201 | #define CPR0_SPCID_SPCIDV0_DIV2 0x02000000 | |
202 | #define CPR0_SPCID_SPCIDV0_DIV3 0x03000000 | |
203 | #define CPR0_SPCID_SPCIDV0_DIV4 0x00000000 | |
204 | #define CPR0_PERD_PERDV0_MASK 0x07000000 | |
205 | ||
206 | #define PCI_MMIO_LCR_BASE (CONFIG_SYS_PCI_BASE + 0x0f400000) /* Real => | |
207 | 0x0EF400000 */ | |
208 | ||
209 | /* PCI Master Local Configuration Registers */ | |
210 | #define PCIL0_PMM0LA (PCI_MMIO_LCR_BASE + 0x00) /* PMM0 Local Address */ | |
211 | #define PCIL0_PMM0MA (PCI_MMIO_LCR_BASE + 0x04) /* PMM0 Mask/Attribute */ | |
212 | #define PCIL0_PMM0PCILA (PCI_MMIO_LCR_BASE + 0x08) /* PMM0 PCI Low Address */ | |
213 | #define PCIL0_PMM0PCIHA (PCI_MMIO_LCR_BASE + 0x0C) /* PMM0 PCI High Address */ | |
214 | #define PCIL0_PMM1LA (PCI_MMIO_LCR_BASE + 0x10) /* PMM1 Local Address */ | |
215 | #define PCIL0_PMM1MA (PCI_MMIO_LCR_BASE + 0x14) /* PMM1 Mask/Attribute */ | |
216 | #define PCIL0_PMM1PCILA (PCI_MMIO_LCR_BASE + 0x18) /* PMM1 PCI Low Address */ | |
217 | #define PCIL0_PMM1PCIHA (PCI_MMIO_LCR_BASE + 0x1C) /* PMM1 PCI High Address */ | |
218 | #define PCIL0_PMM2LA (PCI_MMIO_LCR_BASE + 0x20) /* PMM2 Local Address */ | |
219 | #define PCIL0_PMM2MA (PCI_MMIO_LCR_BASE + 0x24) /* PMM2 Mask/Attribute */ | |
220 | #define PCIL0_PMM2PCILA (PCI_MMIO_LCR_BASE + 0x28) /* PMM2 PCI Low Address */ | |
221 | #define PCIL0_PMM2PCIHA (PCI_MMIO_LCR_BASE + 0x2C) /* PMM2 PCI High Address */ | |
222 | ||
223 | /* PCI Target Local Configuration Registers */ | |
224 | #define PCIL0_PTM1MS (PCI_MMIO_LCR_BASE + 0x30) /* PTM1 Memory Size/ | |
225 | Attribute */ | |
226 | #define PCIL0_PTM1LA (PCI_MMIO_LCR_BASE + 0x34) /* PTM1 Local Addr. Reg */ | |
227 | #define PCIL0_PTM2MS (PCI_MMIO_LCR_BASE + 0x38) /* PTM2 Memory Size/ | |
228 | Attribute */ | |
229 | #define PCIL0_PTM2LA (PCI_MMIO_LCR_BASE + 0x3C) /* PTM2 Local Addr. Reg */ | |
230 | ||
231 | #endif /* _PPC440EP_GR_H_ */ |