projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 46263f2d WD |
1 | /* |
| 2 | * SPDX-License-Identifier: GPL-2.0 ibm-pibs | |
| 3 | */ | |
| 935ecca1 WD |
4 | |
| 5 | #ifndef __PPC4XX_H__ | |
| 6 | #define __PPC4XX_H__ | |
| 7 | ||
| 36ea16f6 | 8 | /* |
| 5e7abce9 | 9 | * Include SoC specific headers |
| 36ea16f6 | 10 | */ |
| 5e7abce9 SR |
11 | #if defined(CONFIG_405CR) |
| 12 | #include <asm/ppc405cr.h> | |
| 13 | #endif | |
| 14 | ||
| 15 | #if defined(CONFIG_405EP) | |
| 16 | #include <asm/ppc405ep.h> | |
| 17 | #endif | |
| 18 | ||
| 19 | #if defined(CONFIG_405EX) | |
| 20 | #include <asm/ppc405ex.h> | |
| 21 | #endif | |
| 22 | ||
| 23 | #if defined(CONFIG_405EZ) | |
| 24 | #include <asm/ppc405ez.h> | |
| 25 | #endif | |
| 26 | ||
| 27 | #if defined(CONFIG_405GP) | |
| 28 | #include <asm/ppc405gp.h> | |
| 36ea16f6 SR |
29 | #endif |
| 30 | ||
| 5e7abce9 SR |
31 | #if defined(CONFIG_440EP) || defined(CONFIG_440GR) |
| 32 | #include <asm/ppc440ep_gr.h> | |
| 36ea16f6 SR |
33 | #endif |
| 34 | ||
| 35 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) | |
| 5e7abce9 SR |
36 | #include <asm/ppc440epx_grx.h> |
| 37 | #endif | |
| 38 | ||
| 39 | #if defined(CONFIG_440GP) | |
| 40 | #include <asm/ppc440gp.h> | |
| 41 | #endif | |
| 42 | ||
| 43 | #if defined(CONFIG_440GX) | |
| 44 | #include <asm/ppc440gx.h> | |
| 36ea16f6 SR |
45 | #endif |
| 46 | ||
| 5e7abce9 SR |
47 | #if defined(CONFIG_440SP) |
| 48 | #include <asm/ppc440sp.h> | |
| 36ea16f6 SR |
49 | #endif |
| 50 | ||
| 5e7abce9 SR |
51 | #if defined(CONFIG_440SPE) |
| 52 | #include <asm/ppc440spe.h> | |
| 5d841fac SR |
53 | #endif |
| 54 | ||
| 5e7abce9 SR |
55 | #if defined(CONFIG_460EX) || defined(CONFIG_460GT) |
| 56 | #include <asm/ppc460ex_gt.h> | |
| 57 | #endif | |
| 58 | ||
| 59 | #if defined(CONFIG_460SX) | |
| 60 | #include <asm/ppc460sx.h> | |
| 61 | #endif | |
| 62 | ||
| 1b8fec13 TM |
63 | #if defined(CONFIG_APM821XX) |
| 64 | #include <asm/apm821xx.h> | |
| 65 | #endif | |
| 66 | ||
| 5e7abce9 SR |
67 | /* |
| 68 | * Common registers for all SoC's | |
| 69 | */ | |
| 70 | /* DCR registers */ | |
| 71 | #define PLB3A0_ACR 0x0077 | |
| 72 | #define PLB4A0_ACR 0x0081 | |
| 73 | #define PLB4A1_ACR 0x0089 | |
| 74 | ||
| afabb498 SR |
75 | /* CPR register declarations */ |
| 76 | ||
| 5e7abce9 SR |
77 | #define PLB4Ax_ACR_PPM_MASK 0xf0000000 |
| 78 | #define PLB4Ax_ACR_PPM_FIXED 0x00000000 | |
| 79 | #define PLB4Ax_ACR_PPM_FAIR 0xd0000000 | |
| 80 | #define PLB4Ax_ACR_HBU_MASK 0x08000000 | |
| 81 | #define PLB4Ax_ACR_HBU_DISABLED 0x00000000 | |
| 82 | #define PLB4Ax_ACR_HBU_ENABLED 0x08000000 | |
| 83 | #define PLB4Ax_ACR_RDP_MASK 0x06000000 | |
| 84 | #define PLB4Ax_ACR_RDP_DISABLED 0x00000000 | |
| 85 | #define PLB4Ax_ACR_RDP_2DEEP 0x02000000 | |
| 86 | #define PLB4Ax_ACR_RDP_3DEEP 0x04000000 | |
| 87 | #define PLB4Ax_ACR_RDP_4DEEP 0x06000000 | |
| 88 | #define PLB4Ax_ACR_WRP_MASK 0x01000000 | |
| 89 | #define PLB4Ax_ACR_WRP_DISABLED 0x00000000 | |
| 90 | #define PLB4Ax_ACR_WRP_2DEEP 0x01000000 | |
| 91 | ||
| afabb498 SR |
92 | /* |
| 93 | * External Bus Controller | |
| 94 | */ | |
| 95 | /* Values for EBC0_CFGADDR register - indirect addressing of these regs */ | |
| 96 | #define PB0CR 0x00 /* periph bank 0 config reg */ | |
| 97 | #define PB1CR 0x01 /* periph bank 1 config reg */ | |
| 98 | #define PB2CR 0x02 /* periph bank 2 config reg */ | |
| 99 | #define PB3CR 0x03 /* periph bank 3 config reg */ | |
| 100 | #define PB4CR 0x04 /* periph bank 4 config reg */ | |
| 101 | #define PB5CR 0x05 /* periph bank 5 config reg */ | |
| 102 | #define PB6CR 0x06 /* periph bank 6 config reg */ | |
| 103 | #define PB7CR 0x07 /* periph bank 7 config reg */ | |
| 104 | #define PB0AP 0x10 /* periph bank 0 access parameters */ | |
| 105 | #define PB1AP 0x11 /* periph bank 1 access parameters */ | |
| 106 | #define PB2AP 0x12 /* periph bank 2 access parameters */ | |
| 107 | #define PB3AP 0x13 /* periph bank 3 access parameters */ | |
| 108 | #define PB4AP 0x14 /* periph bank 4 access parameters */ | |
| 109 | #define PB5AP 0x15 /* periph bank 5 access parameters */ | |
| 110 | #define PB6AP 0x16 /* periph bank 6 access parameters */ | |
| 111 | #define PB7AP 0x17 /* periph bank 7 access parameters */ | |
| 112 | #define PBEAR 0x20 /* periph bus error addr reg */ | |
| 113 | #define PBESR0 0x21 /* periph bus error status reg 0 */ | |
| 114 | #define PBESR1 0x22 /* periph bus error status reg 1 */ | |
| 115 | #define EBC0_CFG 0x23 /* external bus configuration reg */ | |
| 116 | ||
| 117 | /* | |
| 118 | * GPIO macro register defines | |
| 119 | */ | |
| 120 | /* todo: merge with gpio.h header */ | |
| 121 | #define GPIO_BASE GPIO0_BASE | |
| 122 | ||
| 123 | #define GPIO0_OR (GPIO0_BASE + 0x0) | |
| 124 | #define GPIO0_TCR (GPIO0_BASE + 0x4) | |
| 125 | #define GPIO0_OSRL (GPIO0_BASE + 0x8) | |
| 126 | #define GPIO0_OSRH (GPIO0_BASE + 0xC) | |
| 127 | #define GPIO0_TSRL (GPIO0_BASE + 0x10) | |
| 128 | #define GPIO0_TSRH (GPIO0_BASE + 0x14) | |
| 129 | #define GPIO0_ODR (GPIO0_BASE + 0x18) | |
| 130 | #define GPIO0_IR (GPIO0_BASE + 0x1C) | |
| 131 | #define GPIO0_RR1 (GPIO0_BASE + 0x20) | |
| 132 | #define GPIO0_RR2 (GPIO0_BASE + 0x24) | |
| 133 | #define GPIO0_RR3 (GPIO0_BASE + 0x28) | |
| 134 | #define GPIO0_ISR1L (GPIO0_BASE + 0x30) | |
| 135 | #define GPIO0_ISR1H (GPIO0_BASE + 0x34) | |
| 136 | #define GPIO0_ISR2L (GPIO0_BASE + 0x38) | |
| 137 | #define GPIO0_ISR2H (GPIO0_BASE + 0x3C) | |
| 138 | #define GPIO0_ISR3L (GPIO0_BASE + 0x40) | |
| 139 | #define GPIO0_ISR3H (GPIO0_BASE + 0x44) | |
| 140 | ||
| 141 | #define GPIO1_OR (GPIO1_BASE + 0x0) | |
| 142 | #define GPIO1_TCR (GPIO1_BASE + 0x4) | |
| 143 | #define GPIO1_OSRL (GPIO1_BASE + 0x8) | |
| 144 | #define GPIO1_OSRH (GPIO1_BASE + 0xC) | |
| 145 | #define GPIO1_TSRL (GPIO1_BASE + 0x10) | |
| 146 | #define GPIO1_TSRH (GPIO1_BASE + 0x14) | |
| 147 | #define GPIO1_ODR (GPIO1_BASE + 0x18) | |
| 148 | #define GPIO1_IR (GPIO1_BASE + 0x1C) | |
| 149 | #define GPIO1_RR1 (GPIO1_BASE + 0x20) | |
| 150 | #define GPIO1_RR2 (GPIO1_BASE + 0x24) | |
| 151 | #define GPIO1_RR3 (GPIO1_BASE + 0x28) | |
| 152 | #define GPIO1_ISR1L (GPIO1_BASE + 0x30) | |
| 153 | #define GPIO1_ISR1H (GPIO1_BASE + 0x34) | |
| 154 | #define GPIO1_ISR2L (GPIO1_BASE + 0x38) | |
| 155 | #define GPIO1_ISR2H (GPIO1_BASE + 0x3C) | |
| 156 | #define GPIO1_ISR3L (GPIO1_BASE + 0x40) | |
| 157 | #define GPIO1_ISR3H (GPIO1_BASE + 0x44) | |
| 158 | ||
| 5e7abce9 SR |
159 | /* General Purpose Timer (GPT) Register Offsets */ |
| 160 | #define GPT0_TBC 0x00000000 | |
| 161 | #define GPT0_IM 0x00000018 | |
| 162 | #define GPT0_ISS 0x0000001C | |
| 163 | #define GPT0_ISC 0x00000020 | |
| 164 | #define GPT0_IE 0x00000024 | |
| 165 | #define GPT0_COMP0 0x00000080 | |
| 166 | #define GPT0_COMP1 0x00000084 | |
| 167 | #define GPT0_COMP2 0x00000088 | |
| 168 | #define GPT0_COMP3 0x0000008C | |
| 169 | #define GPT0_COMP4 0x00000090 | |
| 170 | #define GPT0_COMP5 0x00000094 | |
| 171 | #define GPT0_COMP6 0x00000098 | |
| 172 | #define GPT0_MASK0 0x000000C0 | |
| 173 | #define GPT0_MASK1 0x000000C4 | |
| 174 | #define GPT0_MASK2 0x000000C8 | |
| 175 | #define GPT0_MASK3 0x000000CC | |
| 176 | #define GPT0_MASK4 0x000000D0 | |
| 177 | #define GPT0_MASK5 0x000000D4 | |
| 178 | #define GPT0_MASK6 0x000000D8 | |
| 179 | #define GPT0_DCT0 0x00000110 | |
| 180 | #define GPT0_DCIS 0x0000011C | |
| 079589bc | 181 | |
| 935ecca1 | 182 | #if defined(CONFIG_440) |
| b36df561 | 183 | #include <asm/ppc440.h> |
| 935ecca1 | 184 | #else |
| b36df561 | 185 | #include <asm/ppc405.h> |
| 935ecca1 WD |
186 | #endif |
| 187 | ||
| 36ea16f6 | 188 | #include <asm/ppc4xx-sdram.h> |
| 7ee2619c | 189 | #include <asm/ppc4xx-ebc.h> |
| d865fd09 | 190 | #if !defined(CONFIG_XILINX_440) |
| 4fb25a3d | 191 | #include <asm/ppc4xx-uic.h> |
| d865fd09 | 192 | #endif |
| 36ea16f6 | 193 | |
| c821b5f1 GE |
194 | /* |
| 195 | * Macro for generating register field mnemonics | |
| 196 | */ | |
| 197 | #define PPC_REG_BITS 32 | |
| 198 | #define PPC_REG_VAL(bit, value) ((value) << ((PPC_REG_BITS - 1) - (bit))) | |
| 199 | ||
| 200 | /* | |
| 201 | * Elide casts when assembling register mnemonics | |
| 202 | */ | |
| 203 | #ifndef __ASSEMBLY__ | |
| 204 | #define static_cast(type, val) (type)(val) | |
| 205 | #else | |
| 206 | #define static_cast(type, val) (val) | |
| 207 | #endif | |
| 208 | ||
| 087dfdb7 SR |
209 | /* |
| 210 | * Common stuff for 4xx (405 and 440) | |
| 211 | */ | |
| 212 | ||
| dbcc3571 | 213 | #define EXC_OFF_SYS_RESET 0x0100 /* System reset */ |
| 087dfdb7 SR |
214 | #define _START_OFFSET (EXC_OFF_SYS_RESET + 0x2000) |
| 215 | ||
| 216 | #define RESET_VECTOR 0xfffffffc | |
| dbcc3571 NG |
217 | #define CACHELINE_MASK (CONFIG_SYS_CACHELINE_SIZE - 1) /* Address mask for |
| 218 | cache line aligned data. */ | |
| 087dfdb7 SR |
219 | |
| 220 | #define CPR0_DCR_BASE 0x0C | |
| d1c3b275 SR |
221 | #define CPR0_CFGADDR (CPR0_DCR_BASE + 0x0) |
| 222 | #define CPR0_CFGDATA (CPR0_DCR_BASE + 0x1) | |
| 087dfdb7 SR |
223 | |
| 224 | #define SDR_DCR_BASE 0x0E | |
| d1c3b275 SR |
225 | #define SDR0_CFGADDR (SDR_DCR_BASE + 0x0) |
| 226 | #define SDR0_CFGDATA (SDR_DCR_BASE + 0x1) | |
| 087dfdb7 SR |
227 | |
| 228 | #define SDRAM_DCR_BASE 0x10 | |
| d1c3b275 SR |
229 | #define SDRAM0_CFGADDR (SDRAM_DCR_BASE + 0x0) |
| 230 | #define SDRAM0_CFGDATA (SDRAM_DCR_BASE + 0x1) | |
| 087dfdb7 SR |
231 | |
| 232 | #define EBC_DCR_BASE 0x12 | |
| d1c3b275 SR |
233 | #define EBC0_CFGADDR (EBC_DCR_BASE + 0x0) |
| 234 | #define EBC0_CFGDATA (EBC_DCR_BASE + 0x1) | |
| 087dfdb7 SR |
235 | |
| 236 | /* | |
| 237 | * Macros for indirect DCR access | |
| 238 | */ | |
| dbcc3571 NG |
239 | #define mtcpr(reg, d) \ |
| 240 | do { mtdcr(CPR0_CFGADDR, reg); mtdcr(CPR0_CFGDATA, d); } while (0) | |
| 241 | #define mfcpr(reg, d) \ | |
| 242 | do { mtdcr(CPR0_CFGADDR, reg); d = mfdcr(CPR0_CFGDATA); } while (0) | |
| 243 | ||
| 244 | #define mtebc(reg, d) \ | |
| 245 | do { mtdcr(EBC0_CFGADDR, reg); mtdcr(EBC0_CFGDATA, d); } while (0) | |
| 246 | #define mfebc(reg, d) \ | |
| 247 | do { mtdcr(EBC0_CFGADDR, reg); d = mfdcr(EBC0_CFGDATA); } while (0) | |
| 248 | ||
| 249 | #define mtsdram(reg, d) \ | |
| 250 | do { mtdcr(SDRAM0_CFGADDR, reg); mtdcr(SDRAM0_CFGDATA, d); } while (0) | |
| 251 | #define mfsdram(reg, d) \ | |
| 252 | do { mtdcr(SDRAM0_CFGADDR, reg); d = mfdcr(SDRAM0_CFGDATA); } while (0) | |
| 253 | ||
| 254 | #define mtsdr(reg, d) \ | |
| 255 | do { mtdcr(SDR0_CFGADDR, reg); mtdcr(SDR0_CFGDATA, d); } while (0) | |
| 256 | #define mfsdr(reg, d) \ | |
| 257 | do { mtdcr(SDR0_CFGADDR, reg); d = mfdcr(SDR0_CFGDATA); } while (0) | |
| 087dfdb7 SR |
258 | |
| 259 | #ifndef __ASSEMBLY__ | |
| 260 | ||
| 261 | typedef struct | |
| 262 | { | |
| 263 | unsigned long freqDDR; | |
| 264 | unsigned long freqEBC; | |
| 265 | unsigned long freqOPB; | |
| 266 | unsigned long freqPCI; | |
| 267 | unsigned long freqPLB; | |
| 268 | unsigned long freqTmrClk; | |
| 269 | unsigned long freqUART; | |
| 270 | unsigned long freqProcessor; | |
| 271 | unsigned long freqVCOHz; | |
| 272 | unsigned long freqVCOMhz; /* in MHz */ | |
| 273 | unsigned long pciClkSync; /* PCI clock is synchronous */ | |
| 274 | unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */ | |
| 275 | unsigned long pllExtBusDiv; | |
| 276 | unsigned long pllFbkDiv; | |
| 277 | unsigned long pllFwdDiv; | |
| 278 | unsigned long pllFwdDivA; | |
| 279 | unsigned long pllFwdDivB; | |
| 280 | unsigned long pllOpbDiv; | |
| 281 | unsigned long pllPciDiv; | |
| 282 | unsigned long pllPlbDiv; | |
| 283 | } PPC4xx_SYS_INFO; | |
| 284 | ||
| f6b6c458 AG |
285 | static inline u32 get_mcsr(void) |
| 286 | { | |
| 287 | u32 val; | |
| 288 | ||
| 289 | asm volatile("mfspr %0, 0x23c" : "=r" (val) :); | |
| 290 | return val; | |
| 291 | } | |
| 292 | ||
| 293 | static inline void set_mcsr(u32 val) | |
| 294 | { | |
| 295 | asm volatile("mtspr 0x23c, %0" : "=r" (val) :); | |
| 296 | } | |
| 297 | ||
| 5e47f953 SR |
298 | int ppc4xx_pci_sync_clock_config(u32 async); |
| 299 | ||
| 087dfdb7 SR |
300 | #endif /* __ASSEMBLY__ */ |
| 301 | ||
| c9c11d75 AG |
302 | /* for multi-cpu support */ |
| 303 | #define NA_OR_UNKNOWN_CPU -1 | |
| 304 | ||
| 935ecca1 | 305 | #endif /* __PPC4XX_H__ */ |