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Commit | Line | Data |
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2874c5fd | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
1da177e4 | 2 | /* |
5ad57078 | 3 | * smp.h: PowerPC-specific SMP code. |
1da177e4 LT |
4 | * |
5 | * Original was a copy of sparc smp.h. Now heavily modified | |
6 | * for PPC. | |
7 | * | |
8 | * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu) | |
9 | * Copyright (C) 1996-2001 Cort Dougan <cort@fsmlabs.com> | |
1da177e4 LT |
10 | */ |
11 | ||
5ad57078 PM |
12 | #ifndef _ASM_POWERPC_SMP_H |
13 | #define _ASM_POWERPC_SMP_H | |
1da177e4 | 14 | #ifdef __KERNEL__ |
1da177e4 | 15 | |
1da177e4 LT |
16 | #include <linux/threads.h> |
17 | #include <linux/cpumask.h> | |
18 | #include <linux/kernel.h> | |
23d72bfd | 19 | #include <linux/irqreturn.h> |
1da177e4 LT |
20 | |
21 | #ifndef __ASSEMBLY__ | |
22 | ||
5ad57078 | 23 | #ifdef CONFIG_PPC64 |
1da177e4 | 24 | #include <asm/paca.h> |
5ad57078 | 25 | #endif |
d5a7430d | 26 | #include <asm/percpu.h> |
1da177e4 LT |
27 | |
28 | extern int boot_cpuid; | |
7ac87abb | 29 | extern int spinning_secondaries; |
9f593f13 | 30 | extern u32 *cpu_to_phys_id; |
1da177e4 LT |
31 | |
32 | extern void cpu_die(void); | |
3eb906c6 | 33 | extern int cpu_to_chip_id(int cpu); |
1da177e4 LT |
34 | |
35 | #ifdef CONFIG_SMP | |
36 | ||
17f9c8a7 MM |
37 | struct smp_ops_t { |
38 | void (*message_pass)(int cpu, int msg); | |
1ece355b | 39 | #ifdef CONFIG_PPC_SMP_MUXED_IPI |
b866cc21 | 40 | void (*cause_ipi)(int cpu); |
1ece355b | 41 | #endif |
c64af645 | 42 | int (*cause_nmi_ipi)(int cpu); |
a7f4ee1f | 43 | void (*probe)(void); |
17f9c8a7 | 44 | int (*kick_cpu)(int nr); |
14d4ae5c | 45 | int (*prepare_cpu)(int nr); |
17f9c8a7 MM |
46 | void (*setup_cpu)(int nr); |
47 | void (*bringup_done)(void); | |
48 | void (*take_timebase)(void); | |
49 | void (*give_timebase)(void); | |
50 | int (*cpu_disable)(void); | |
51 | void (*cpu_die)(unsigned int nr); | |
52 | int (*cpu_bootable)(unsigned int nr); | |
53 | }; | |
54 | ||
2104180a | 55 | extern int smp_send_nmi_ipi(int cpu, void (*fn)(struct pt_regs *), u64 delay_us); |
6ba55716 | 56 | extern int smp_send_safe_nmi_ipi(int cpu, void (*fn)(struct pt_regs *), u64 delay_us); |
e0476371 | 57 | extern void smp_send_debugger_break(void); |
fa3f82c8 | 58 | extern void start_secondary_resume(void); |
cad5cef6 GKH |
59 | extern void smp_generic_give_timebase(void); |
60 | extern void smp_generic_take_timebase(void); | |
1da177e4 | 61 | |
6b7487fc | 62 | DECLARE_PER_CPU(unsigned int, cpu_pvr); |
1c21a293 | 63 | |
1da177e4 | 64 | #ifdef CONFIG_HOTPLUG_CPU |
1da177e4 | 65 | int generic_cpu_disable(void); |
1da177e4 | 66 | void generic_cpu_die(unsigned int cpu); |
105765f4 | 67 | void generic_set_cpu_dead(unsigned int cpu); |
ae5cab47 | 68 | void generic_set_cpu_up(unsigned int cpu); |
fb82b839 | 69 | int generic_check_cpu_restart(unsigned int cpu); |
2f4f1f81 | 70 | int is_cpu_dead(unsigned int cpu); |
71 | #else | |
72 | #define generic_set_cpu_up(i) do { } while (0) | |
1da177e4 LT |
73 | #endif |
74 | ||
5ad57078 | 75 | #ifdef CONFIG_PPC64 |
048c8bc9 | 76 | #define raw_smp_processor_id() (local_paca->paca_index) |
1da177e4 | 77 | #define hard_smp_processor_id() (get_paca()->hw_cpu_id) |
5ad57078 PM |
78 | #else |
79 | /* 32-bit */ | |
80 | extern int smp_hw_index[]; | |
81 | ||
ed1cd6de CL |
82 | /* |
83 | * This is particularly ugly: it appears we can't actually get the definition | |
84 | * of task_struct here, but we need access to the CPU this task is running on. | |
85 | * Instead of using task_struct we're using _TASK_CPU which is extracted from | |
86 | * asm-offsets.h by kbuild to get the current processor ID. | |
87 | * | |
88 | * This also needs to be safeguarded when building asm-offsets.s because at | |
89 | * that time _TASK_CPU is not defined yet. It could have been guarded by | |
90 | * _TASK_CPU itself, but we want the build to fail if _TASK_CPU is missing | |
91 | * when building something else than asm-offsets.s | |
92 | */ | |
93 | #ifdef GENERATING_ASM_OFFSETS | |
94 | #define raw_smp_processor_id() (0) | |
95 | #else | |
96 | #define raw_smp_processor_id() (*(unsigned int *)((void *)current + _TASK_CPU)) | |
97 | #endif | |
5ad57078 | 98 | #define hard_smp_processor_id() (smp_hw_index[smp_processor_id()]) |
41eba0ad BH |
99 | |
100 | static inline int get_hard_smp_processor_id(int cpu) | |
101 | { | |
102 | return smp_hw_index[cpu]; | |
103 | } | |
104 | ||
105 | static inline void set_hard_smp_processor_id(int cpu, int phys) | |
106 | { | |
107 | smp_hw_index[cpu] = phys; | |
108 | } | |
5ad57078 | 109 | #endif |
1da177e4 | 110 | |
cc1ba8ea | 111 | DECLARE_PER_CPU(cpumask_var_t, cpu_sibling_map); |
2a636a56 | 112 | DECLARE_PER_CPU(cpumask_var_t, cpu_l2_cache_map); |
cc1ba8ea | 113 | DECLARE_PER_CPU(cpumask_var_t, cpu_core_map); |
425752c6 | 114 | DECLARE_PER_CPU(cpumask_var_t, cpu_smallcore_map); |
cc1ba8ea AB |
115 | |
116 | static inline struct cpumask *cpu_sibling_mask(int cpu) | |
117 | { | |
118 | return per_cpu(cpu_sibling_map, cpu); | |
119 | } | |
120 | ||
121 | static inline struct cpumask *cpu_core_mask(int cpu) | |
122 | { | |
123 | return per_cpu(cpu_core_map, cpu); | |
124 | } | |
125 | ||
2a636a56 OH |
126 | static inline struct cpumask *cpu_l2_cache_mask(int cpu) |
127 | { | |
128 | return per_cpu(cpu_l2_cache_map, cpu); | |
129 | } | |
130 | ||
425752c6 GS |
131 | static inline struct cpumask *cpu_smallcore_mask(int cpu) |
132 | { | |
133 | return per_cpu(cpu_smallcore_map, cpu); | |
134 | } | |
135 | ||
e9efed3b | 136 | extern int cpu_to_core_id(int cpu); |
1da177e4 LT |
137 | |
138 | /* Since OpenPIC has only 4 IPIs, we use slightly different message numbers. | |
139 | * | |
140 | * Make sure this matches openpic_request_IPIs in open_pic.c, or what shows up | |
141 | * in /proc/interrupts will be wrong!!! --Troy */ | |
ddd703ca NP |
142 | #define PPC_MSG_CALL_FUNCTION 0 |
143 | #define PPC_MSG_RESCHEDULE 1 | |
1b67bee1 | 144 | #define PPC_MSG_TICK_BROADCAST 2 |
ddd703ca | 145 | #define PPC_MSG_NMI_IPI 3 |
1da177e4 | 146 | |
bd7f561f SW |
147 | /* This is only used by the powernv kernel */ |
148 | #define PPC_MSG_RM_HOST_ACTION 4 | |
149 | ||
ddd703ca NP |
150 | #define NMI_IPI_ALL_OTHERS -2 |
151 | ||
152 | #ifdef CONFIG_NMI_IPI | |
153 | extern int smp_handle_nmi_ipi(struct pt_regs *regs); | |
154 | #else | |
155 | static inline int smp_handle_nmi_ipi(struct pt_regs *regs) { return 0; } | |
156 | #endif | |
157 | ||
23d72bfd | 158 | /* for irq controllers that have dedicated ipis per message (4) */ |
25ddd738 MM |
159 | extern int smp_request_message_ipi(int virq, int message); |
160 | extern const char *smp_ipi_name[]; | |
161 | ||
23d72bfd | 162 | /* for irq controllers with only a single ipi */ |
23d72bfd | 163 | extern void smp_muxed_ipi_message_pass(int cpu, int msg); |
31639c77 | 164 | extern void smp_muxed_ipi_set_message(int cpu, int msg); |
23d72bfd | 165 | extern irqreturn_t smp_ipi_demux(void); |
b87ac021 | 166 | extern irqreturn_t smp_ipi_demux_relaxed(void); |
23d72bfd | 167 | |
1da177e4 | 168 | void smp_init_pSeries(void); |
19fe0475 | 169 | void smp_init_cell(void); |
5ad57078 | 170 | void smp_setup_cpu_maps(void); |
1da177e4 LT |
171 | |
172 | extern int __cpu_disable(void); | |
173 | extern void __cpu_die(unsigned int cpu); | |
5ad57078 PM |
174 | |
175 | #else | |
176 | /* for UP */ | |
78b5b626 | 177 | #define hard_smp_processor_id() get_hard_smp_processor_id(0) |
5ad57078 | 178 | #define smp_setup_cpu_maps() |
3cc33d50 PM |
179 | static inline void inhibit_secondary_onlining(void) {} |
180 | static inline void uninhibit_secondary_onlining(void) {} | |
3be7db6a RJ |
181 | static inline const struct cpumask *cpu_sibling_mask(int cpu) |
182 | { | |
183 | return cpumask_of(cpu); | |
184 | } | |
5ad57078 | 185 | |
425752c6 GS |
186 | static inline const struct cpumask *cpu_smallcore_mask(int cpu) |
187 | { | |
188 | return cpumask_of(cpu); | |
189 | } | |
190 | ||
1da177e4 LT |
191 | #endif /* CONFIG_SMP */ |
192 | ||
5ad57078 | 193 | #ifdef CONFIG_PPC64 |
41eba0ad BH |
194 | static inline int get_hard_smp_processor_id(int cpu) |
195 | { | |
d2e60075 | 196 | return paca_ptrs[cpu]->hw_cpu_id; |
41eba0ad BH |
197 | } |
198 | ||
199 | static inline void set_hard_smp_processor_id(int cpu, int phys) | |
200 | { | |
d2e60075 | 201 | paca_ptrs[cpu]->hw_cpu_id = phys; |
41eba0ad | 202 | } |
5ad57078 PM |
203 | #else |
204 | /* 32-bit */ | |
205 | #ifndef CONFIG_SMP | |
4df20460 | 206 | extern int boot_cpuid_phys; |
41eba0ad BH |
207 | static inline int get_hard_smp_processor_id(int cpu) |
208 | { | |
209 | return boot_cpuid_phys; | |
210 | } | |
211 | ||
212 | static inline void set_hard_smp_processor_id(int cpu, int phys) | |
213 | { | |
78b5b626 | 214 | boot_cpuid_phys = phys; |
41eba0ad BH |
215 | } |
216 | #endif /* !CONFIG_SMP */ | |
217 | #endif /* !CONFIG_PPC64 */ | |
1da177e4 | 218 | |
da665885 | 219 | #if defined(CONFIG_PPC64) && (defined(CONFIG_SMP) || defined(CONFIG_KEXEC_CORE)) |
b1923caa BH |
220 | extern void smp_release_cpus(void); |
221 | #else | |
222 | static inline void smp_release_cpus(void) { }; | |
223 | #endif | |
224 | ||
1da177e4 LT |
225 | extern int smt_enabled_at_boot; |
226 | ||
a7f4ee1f | 227 | extern void smp_mpic_probe(void); |
1da177e4 | 228 | extern void smp_mpic_setup_cpu(int cpu); |
de300974 | 229 | extern int smp_generic_kick_cpu(int nr); |
3cd85250 AF |
230 | extern int smp_generic_cpu_bootable(unsigned int nr); |
231 | ||
1da177e4 LT |
232 | |
233 | extern void smp_generic_give_timebase(void); | |
234 | extern void smp_generic_take_timebase(void); | |
235 | ||
236 | extern struct smp_ops_t *smp_ops; | |
237 | ||
b7d7a240 | 238 | extern void arch_send_call_function_single_ipi(int cpu); |
f063ea02 | 239 | extern void arch_send_call_function_ipi_mask(const struct cpumask *mask); |
b7d7a240 | 240 | |
cf54dc7c BH |
241 | /* Definitions relative to the secondary CPU spin loop |
242 | * and entry point. Not all of them exist on both 32 and | |
243 | * 64-bit but defining them all here doesn't harm | |
244 | */ | |
245 | extern void generic_secondary_smp_init(void); | |
2d27cfd3 | 246 | extern void generic_secondary_thread_init(void); |
cf54dc7c BH |
247 | extern unsigned long __secondary_hold_spinloop; |
248 | extern unsigned long __secondary_hold_acknowledge; | |
249 | extern char __secondary_hold; | |
6becef7e | 250 | extern unsigned int booting_thread_hwid; |
cf54dc7c | 251 | |
d0832a75 | 252 | extern void __early_start(void); |
1da177e4 LT |
253 | #endif /* __ASSEMBLY__ */ |
254 | ||
1da177e4 | 255 | #endif /* __KERNEL__ */ |
5ad57078 | 256 | #endif /* _ASM_POWERPC_SMP_H) */ |