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Commit | Line | Data |
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fe8c2806 | 1 | /* |
9b998b0c | 2 | * (C) Copyright 2000-2011 |
fe8c2806 WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | #include <watchdog.h> | |
26 | #include <command.h> | |
27 | #include <malloc.h> | |
52cb4d4f | 28 | #include <stdio_dev.h> |
fe8c2806 WD |
29 | #ifdef CONFIG_8xx |
30 | #include <mpc8xx.h> | |
31 | #endif | |
0db5bca8 WD |
32 | #ifdef CONFIG_5xx |
33 | #include <mpc5xx.h> | |
34 | #endif | |
cbd8a35c | 35 | #ifdef CONFIG_MPC5xxx |
945af8d7 WD |
36 | #include <mpc5xxx.h> |
37 | #endif | |
7def6b34 | 38 | #if defined(CONFIG_CMD_IDE) |
fe8c2806 WD |
39 | #include <ide.h> |
40 | #endif | |
7def6b34 | 41 | #if defined(CONFIG_CMD_SCSI) |
fe8c2806 WD |
42 | #include <scsi.h> |
43 | #endif | |
7def6b34 | 44 | #if defined(CONFIG_CMD_KGDB) |
fe8c2806 WD |
45 | #include <kgdb.h> |
46 | #endif | |
47 | #ifdef CONFIG_STATUS_LED | |
48 | #include <status_led.h> | |
49 | #endif | |
50 | #include <net.h> | |
272cc70b AF |
51 | #ifdef CONFIG_GENERIC_MMC |
52 | #include <mmc.h> | |
53 | #endif | |
281e00a3 | 54 | #include <serial.h> |
6d0f6bcf | 55 | #ifdef CONFIG_SYS_ALLOC_DPRAM |
9c4c5ae3 | 56 | #if !defined(CONFIG_CPM2) |
fe8c2806 WD |
57 | #include <commproc.h> |
58 | #endif | |
7aa78614 | 59 | #endif |
fe8c2806 WD |
60 | #include <version.h> |
61 | #if defined(CONFIG_BAB7xx) | |
62 | #include <w83c553f.h> | |
63 | #endif | |
64 | #include <dtt.h> | |
65 | #if defined(CONFIG_POST) | |
66 | #include <post.h> | |
67 | #endif | |
56f94be3 WD |
68 | #if defined(CONFIG_LOGBUFFER) |
69 | #include <logbuff.h> | |
70 | #endif | |
9c67352f | 71 | #if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500) |
42d1f039 WD |
72 | #include <asm/cache.h> |
73 | #endif | |
1c43771b WD |
74 | #ifdef CONFIG_PS2KBD |
75 | #include <keyboard.h> | |
76 | #endif | |
fe8c2806 | 77 | |
ecf5b98c KG |
78 | #ifdef CONFIG_ADDR_MAP |
79 | #include <asm/mmu.h> | |
80 | #endif | |
81 | ||
fc39c2fd KG |
82 | #ifdef CONFIG_MP |
83 | #include <asm/mp.h> | |
84 | #endif | |
85 | ||
310cecb8 LCM |
86 | #ifdef CONFIG_BITBANGMII |
87 | #include <miiphy.h> | |
88 | #endif | |
89 | ||
6d0f6bcf | 90 | #ifdef CONFIG_SYS_UPDATE_FLASH_SIZE |
9b998b0c | 91 | extern int update_flash_size(int flash_size); |
fa230445 HS |
92 | #endif |
93 | ||
9045f33c | 94 | #if defined(CONFIG_SC3) |
ca43ba18 HS |
95 | extern void sc3_read_eeprom(void); |
96 | #endif | |
97 | ||
7def6b34 | 98 | #if defined(CONFIG_CMD_DOC) |
9b998b0c | 99 | void doc_init(void); |
fe8c2806 WD |
100 | #endif |
101 | #if defined(CONFIG_HARD_I2C) || \ | |
102 | defined(CONFIG_SOFT_I2C) | |
103 | #include <i2c.h> | |
104 | #endif | |
04a9e118 | 105 | #include <spi.h> |
d6ac2ed8 | 106 | #include <nand.h> |
fe8c2806 WD |
107 | |
108 | static char *failed = "*** failed ***\n"; | |
109 | ||
544d97e9 | 110 | #if defined(CONFIG_OXC) || defined(CONFIG_RMU) |
fe8c2806 | 111 | extern flash_info_t flash_info[]; |
17d704eb | 112 | #endif |
fe8c2806 | 113 | |
ca43ba18 HS |
114 | #if defined(CONFIG_START_IDE) |
115 | extern int board_start_ide(void); | |
116 | #endif | |
fe8c2806 | 117 | #include <environment.h> |
d87080b7 | 118 | |
bce84c4d | 119 | DECLARE_GLOBAL_DATA_PTR; |
fe8c2806 | 120 | |
6d0f6bcf JCPV |
121 | #if !defined(CONFIG_SYS_MEM_TOP_HIDE) |
122 | #define CONFIG_SYS_MEM_TOP_HIDE 0 | |
6fb4b640 SR |
123 | #endif |
124 | ||
3b57fe0a | 125 | extern ulong __init_end; |
3929fb0a | 126 | extern ulong __bss_end; |
3b57fe0a WD |
127 | ulong monitor_flash_len; |
128 | ||
7def6b34 | 129 | #if defined(CONFIG_CMD_BEDBUG) |
8bde7f77 WD |
130 | #include <bedbug/type.h> |
131 | #endif | |
132 | ||
9b998b0c WD |
133 | /* |
134 | * Utilities | |
fe8c2806 WD |
135 | */ |
136 | ||
fe8c2806 WD |
137 | /* |
138 | * All attempts to come up with a "common" initialization sequence | |
139 | * that works for all boards and architectures failed: some of the | |
140 | * requirements are just _too_ different. To get rid of the resulting | |
141 | * mess of board dependend #ifdef'ed code we now make the whole | |
142 | * initialization sequence configurable to the user. | |
143 | * | |
144 | * The requirements for any new initalization function is simple: it | |
145 | * receives a pointer to the "global data" structure as it's only | |
146 | * argument, and returns an integer return code, where 0 means | |
147 | * "continue" and != 0 means "fatal error, hang the system". | |
148 | */ | |
9b998b0c | 149 | typedef int (init_fnc_t)(void); |
fe8c2806 | 150 | |
9b998b0c WD |
151 | /* |
152 | * Init Utilities | |
153 | * | |
fe8c2806 WD |
154 | * Some of this code should be moved into the core functions, |
155 | * but let's get it working (again) first... | |
156 | */ | |
157 | ||
9b998b0c | 158 | static int init_baudrate(void) |
fe8c2806 | 159 | { |
1272592e SG |
160 | gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE); |
161 | return 0; | |
fe8c2806 WD |
162 | } |
163 | ||
164 | /***********************************************************************/ | |
165 | ||
20051f2a | 166 | static void __board_add_ram_info(int use_default) |
79f240f7 KP |
167 | { |
168 | /* please define platform specific board_add_ram_info() */ | |
169 | } | |
9b998b0c WD |
170 | |
171 | void board_add_ram_info(int) | |
172 | __attribute__ ((weak, alias("__board_add_ram_info"))); | |
79f240f7 | 173 | |
20051f2a | 174 | static int __board_flash_wp_on(void) |
c62491d2 JS |
175 | { |
176 | /* | |
177 | * Most flashes can't be detected when write protection is enabled, | |
178 | * so provide a way to let U-Boot gracefully ignore write protected | |
179 | * devices. | |
180 | */ | |
181 | return 0; | |
182 | } | |
9b998b0c WD |
183 | |
184 | int board_flash_wp_on(void) | |
185 | __attribute__ ((weak, alias("__board_flash_wp_on"))); | |
d96f41e0 | 186 | |
20051f2a | 187 | static void __cpu_secondary_init_r(void) |
f9a33f1c KG |
188 | { |
189 | } | |
9b998b0c | 190 | |
f9a33f1c | 191 | void cpu_secondary_init_r(void) |
9b998b0c | 192 | __attribute__ ((weak, alias("__cpu_secondary_init_r"))); |
f9a33f1c | 193 | |
9b998b0c | 194 | static int init_func_ram(void) |
fe8c2806 | 195 | { |
fe8c2806 WD |
196 | #ifdef CONFIG_BOARD_TYPES |
197 | int board_type = gd->board_type; | |
198 | #else | |
199 | int board_type = 0; /* use dummy arg */ | |
200 | #endif | |
9b998b0c | 201 | puts("DRAM: "); |
fe8c2806 | 202 | |
9b998b0c WD |
203 | gd->ram_size = initdram(board_type); |
204 | ||
205 | if (gd->ram_size > 0) { | |
206 | print_size(gd->ram_size, ""); | |
d96f41e0 | 207 | board_add_ram_info(0); |
d96f41e0 | 208 | putc('\n'); |
9b998b0c | 209 | return 0; |
fe8c2806 | 210 | } |
9b998b0c WD |
211 | puts(failed); |
212 | return 1; | |
fe8c2806 WD |
213 | } |
214 | ||
215 | /***********************************************************************/ | |
216 | ||
217 | #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) | |
9b998b0c | 218 | static int init_func_i2c(void) |
fe8c2806 | 219 | { |
9b998b0c WD |
220 | puts("I2C: "); |
221 | i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); | |
222 | puts("ready\n"); | |
223 | return 0; | |
fe8c2806 WD |
224 | } |
225 | #endif | |
226 | ||
04a9e118 | 227 | #if defined(CONFIG_HARD_SPI) |
9b998b0c | 228 | static int init_func_spi(void) |
04a9e118 | 229 | { |
9b998b0c WD |
230 | puts("SPI: "); |
231 | spi_init(); | |
232 | puts("ready\n"); | |
233 | return 0; | |
04a9e118 BW |
234 | } |
235 | #endif | |
236 | ||
fe8c2806 WD |
237 | /***********************************************************************/ |
238 | ||
239 | #if defined(CONFIG_WATCHDOG) | |
9b998b0c | 240 | static int init_func_watchdog_init(void) |
fe8c2806 | 241 | { |
9b998b0c WD |
242 | puts(" Watchdog enabled\n"); |
243 | WATCHDOG_RESET(); | |
244 | return 0; | |
fe8c2806 | 245 | } |
fe8c2806 | 246 | |
9b998b0c WD |
247 | #define INIT_FUNC_WATCHDOG_INIT init_func_watchdog_init, |
248 | ||
249 | static int init_func_watchdog_reset(void) | |
fe8c2806 | 250 | { |
9b998b0c WD |
251 | WATCHDOG_RESET(); |
252 | return 0; | |
fe8c2806 | 253 | } |
9b998b0c WD |
254 | |
255 | #define INIT_FUNC_WATCHDOG_RESET init_func_watchdog_reset, | |
fe8c2806 | 256 | #else |
9b998b0c WD |
257 | #define INIT_FUNC_WATCHDOG_INIT /* undef */ |
258 | #define INIT_FUNC_WATCHDOG_RESET /* undef */ | |
fe8c2806 WD |
259 | #endif /* CONFIG_WATCHDOG */ |
260 | ||
9b998b0c WD |
261 | /* |
262 | * Initialization sequence | |
fe8c2806 WD |
263 | */ |
264 | ||
20051f2a | 265 | static init_fnc_t *init_sequence[] = { |
0e870980 PA |
266 | #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) |
267 | probecpu, | |
268 | #endif | |
91525c67 AV |
269 | #if defined(CONFIG_BOARD_EARLY_INIT_F) |
270 | board_early_init_f, | |
271 | #endif | |
66ca92a5 | 272 | #if !defined(CONFIG_8xx_CPUCLK_DEFAULT) |
fe8c2806 | 273 | get_clocks, /* get CPU and bus clocks (etc.) */ |
090eb735 MK |
274 | #if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \ |
275 | && !defined(CONFIG_TQM885D) | |
e9132ea9 WD |
276 | adjust_sdram_tbs_8xx, |
277 | #endif | |
fe8c2806 | 278 | init_timebase, |
c178d3da | 279 | #endif |
6d0f6bcf | 280 | #ifdef CONFIG_SYS_ALLOC_DPRAM |
9c4c5ae3 | 281 | #if !defined(CONFIG_CPM2) |
fe8c2806 WD |
282 | dpram_init, |
283 | #endif | |
7aa78614 | 284 | #endif |
fe8c2806 WD |
285 | #if defined(CONFIG_BOARD_POSTCLK_INIT) |
286 | board_postclk_init, | |
287 | #endif | |
288 | env_init, | |
66ca92a5 | 289 | #if defined(CONFIG_8xx_CPUCLK_DEFAULT) |
9b998b0c WD |
290 | /* get CPU and bus clocks according to the environment variable */ |
291 | get_clocks_866, | |
292 | /* adjust sdram refresh rate according to the new clock */ | |
293 | sdram_adjust_866, | |
c178d3da WD |
294 | init_timebase, |
295 | #endif | |
fe8c2806 WD |
296 | init_baudrate, |
297 | serial_init, | |
298 | console_init_f, | |
299 | display_options, | |
300 | #if defined(CONFIG_8260) | |
301 | prt_8260_rsr, | |
302 | prt_8260_clks, | |
303 | #endif /* CONFIG_8260 */ | |
0f898604 | 304 | #if defined(CONFIG_MPC83xx) |
9be39a67 DL |
305 | prt_83xx_rsr, |
306 | #endif | |
fe8c2806 | 307 | checkcpu, |
cbd8a35c | 308 | #if defined(CONFIG_MPC5xxx) |
945af8d7 | 309 | prt_mpc5xxx_clks, |
cbd8a35c | 310 | #endif /* CONFIG_MPC5xxx */ |
983fda83 WD |
311 | #if defined(CONFIG_MPC8220) |
312 | prt_mpc8220_clks, | |
313 | #endif | |
fe8c2806 WD |
314 | checkboard, |
315 | INIT_FUNC_WATCHDOG_INIT | |
c837dcb1 | 316 | #if defined(CONFIG_MISC_INIT_F) |
fe8c2806 WD |
317 | misc_init_f, |
318 | #endif | |
319 | INIT_FUNC_WATCHDOG_RESET | |
320 | #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) | |
321 | init_func_i2c, | |
322 | #endif | |
04a9e118 BW |
323 | #if defined(CONFIG_HARD_SPI) |
324 | init_func_spi, | |
325 | #endif | |
4532cb69 WD |
326 | #ifdef CONFIG_POST |
327 | post_init_f, | |
fe8c2806 | 328 | #endif |
9b998b0c | 329 | INIT_FUNC_WATCHDOG_RESET init_func_ram, |
6d0f6bcf | 330 | #if defined(CONFIG_SYS_DRAM_TEST) |
fe8c2806 | 331 | testdram, |
6d0f6bcf | 332 | #endif /* CONFIG_SYS_DRAM_TEST */ |
fe8c2806 | 333 | INIT_FUNC_WATCHDOG_RESET |
9b998b0c | 334 | NULL, /* Terminate this list */ |
fe8c2806 WD |
335 | }; |
336 | ||
81d93e5c KG |
337 | ulong get_effective_memsize(void) |
338 | { | |
339 | #ifndef CONFIG_VERY_BIG_RAM | |
340 | return gd->ram_size; | |
341 | #else | |
342 | /* limit stack to what we can reasonable map */ | |
343 | return ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ? | |
9b998b0c | 344 | CONFIG_MAX_MEM_MAPPED : gd->ram_size); |
81d93e5c KG |
345 | #endif |
346 | } | |
347 | ||
20051f2a | 348 | static int __fixup_cpu(void) |
123bd96d YS |
349 | { |
350 | return 0; | |
351 | } | |
352 | ||
353 | int fixup_cpu(void) __attribute__((weak, alias("__fixup_cpu"))); | |
354 | ||
9b998b0c | 355 | /* |
fe8c2806 WD |
356 | * This is the first part of the initialization sequence that is |
357 | * implemented in C, but still running from ROM. | |
358 | * | |
359 | * The main purpose is to provide a (serial) console interface as | |
360 | * soon as possible (so we can see any error messages), and to | |
361 | * initialize the RAM so that we can relocate the monitor code to | |
362 | * RAM. | |
363 | * | |
364 | * Be aware of the restrictions: global data is read-only, BSS is not | |
365 | * initialized, and stack space is limited to a few kB. | |
fe8c2806 WD |
366 | */ |
367 | ||
95d449ad MB |
368 | #ifdef CONFIG_LOGBUFFER |
369 | unsigned long logbuffer_base(void) | |
370 | { | |
6d0f6bcf | 371 | return CONFIG_SYS_SDRAM_BASE + get_effective_memsize() - LOGBUFF_LEN; |
95d449ad MB |
372 | } |
373 | #endif | |
374 | ||
9b998b0c | 375 | void board_init_f(ulong bootflag) |
fe8c2806 | 376 | { |
fe8c2806 WD |
377 | bd_t *bd; |
378 | ulong len, addr, addr_sp; | |
7bc5ee07 | 379 | ulong *s; |
fe8c2806 WD |
380 | gd_t *id; |
381 | init_fnc_t **init_fnc_ptr; | |
9b998b0c | 382 | |
fe8c2806 | 383 | #ifdef CONFIG_PRAM |
fe8c2806 | 384 | ulong reg; |
fe8c2806 WD |
385 | #endif |
386 | ||
387 | /* Pointer is writable since we allocated a register for it */ | |
6d0f6bcf | 388 | gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); |
93f6a677 | 389 | /* compiler optimization barrier needed for GCC >= 3.4 */ |
9b998b0c | 390 | __asm__ __volatile__("":::"memory"); |
fe8c2806 | 391 | |
82826d54 DZ |
392 | #if !defined(CONFIG_CPM2) && !defined(CONFIG_MPC512X) && \ |
393 | !defined(CONFIG_MPC83xx) && !defined(CONFIG_MPC85xx) && \ | |
394 | !defined(CONFIG_MPC86xx) | |
fe8c2806 | 395 | /* Clear initial global data */ |
9b998b0c | 396 | memset((void *) gd, 0, sizeof(gd_t)); |
fe8c2806 WD |
397 | #endif |
398 | ||
9b998b0c WD |
399 | for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) |
400 | if ((*init_fnc_ptr) () != 0) | |
401 | hang(); | |
fe8c2806 | 402 | |
9d256b67 BK |
403 | #ifdef CONFIG_POST |
404 | post_bootmode_init(); | |
20051f2a | 405 | post_run(NULL, POST_ROM | post_bootmode_get(NULL)); |
9d256b67 BK |
406 | #endif |
407 | ||
408 | WATCHDOG_RESET(); | |
409 | ||
fe8c2806 WD |
410 | /* |
411 | * Now that we have DRAM mapped and working, we can | |
412 | * relocate the code and continue running from DRAM. | |
413 | * | |
414 | * Reserve memory at end of RAM for (top down in that order): | |
14f73ca6 | 415 | * - area that won't get touched by U-Boot and Linux (optional) |
8bde7f77 | 416 | * - kernel log buffer |
fe8c2806 WD |
417 | * - protected RAM |
418 | * - LCD framebuffer | |
419 | * - monitor code | |
420 | * - board info struct | |
421 | */ | |
3929fb0a | 422 | len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE; |
fe8c2806 | 423 | |
14f73ca6 SR |
424 | /* |
425 | * Subtract specified amount of memory to hide so that it won't | |
426 | * get "touched" at all by U-Boot. By fixing up gd->ram_size | |
427 | * the Linux kernel should now get passed the now "corrected" | |
428 | * memory size and won't touch it either. This should work | |
429 | * for arch/ppc and arch/powerpc. Only Linux board ports in | |
430 | * arch/powerpc with bootwrapper support, that recalculate the | |
431 | * memory size from the SDRAM controller setup will have to | |
432 | * get fixed. | |
433 | */ | |
6d0f6bcf | 434 | gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE; |
14f73ca6 | 435 | |
6d0f6bcf | 436 | addr = CONFIG_SYS_SDRAM_BASE + get_effective_memsize(); |
fe8c2806 | 437 | |
fc39c2fd KG |
438 | #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) |
439 | /* | |
440 | * We need to make sure the location we intend to put secondary core | |
441 | * boot code is reserved and not used by any part of u-boot | |
c0a14aed | 442 | */ |
eb539412 YS |
443 | if (addr > determine_mp_bootpg(NULL)) { |
444 | addr = determine_mp_bootpg(NULL); | |
9b998b0c | 445 | debug("Reserving MP boot page to %08lx\n", addr); |
fc39c2fd KG |
446 | } |
447 | #endif | |
448 | ||
228f29ac | 449 | #ifdef CONFIG_LOGBUFFER |
3d610186 | 450 | #ifndef CONFIG_ALT_LB_ADDR |
228f29ac WD |
451 | /* reserve kernel log buffer */ |
452 | addr -= (LOGBUFF_RESERVE); | |
9b998b0c WD |
453 | debug("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN, |
454 | addr); | |
228f29ac | 455 | #endif |
3d610186 | 456 | #endif |
228f29ac | 457 | |
fe8c2806 WD |
458 | #ifdef CONFIG_PRAM |
459 | /* | |
460 | * reserve protected RAM | |
461 | */ | |
1272592e | 462 | reg = getenv_ulong("pram", 10, CONFIG_PRAM); |
9b998b0c | 463 | addr -= (reg << 10); /* size is in kB */ |
1272592e | 464 | debug("Reserving %ldk for protected RAM at %08lx\n", reg, addr); |
fe8c2806 WD |
465 | #endif /* CONFIG_PRAM */ |
466 | ||
467 | /* round down to next 4 kB limit */ | |
468 | addr &= ~(4096 - 1); | |
9b998b0c | 469 | debug("Top of RAM usable for U-Boot at: %08lx\n", addr); |
fe8c2806 WD |
470 | |
471 | #ifdef CONFIG_LCD | |
d32a1a4c MK |
472 | #ifdef CONFIG_FB_ADDR |
473 | gd->fb_base = CONFIG_FB_ADDR; | |
474 | #else | |
fe8c2806 | 475 | /* reserve memory for LCD display (always full pages) */ |
9b998b0c | 476 | addr = lcd_setmem(addr); |
fe8c2806 | 477 | gd->fb_base = addr; |
d32a1a4c | 478 | #endif /* CONFIG_FB_ADDR */ |
fe8c2806 WD |
479 | #endif /* CONFIG_LCD */ |
480 | ||
481 | #if defined(CONFIG_VIDEO) && defined(CONFIG_8xx) | |
482 | /* reserve memory for video display (always full pages) */ | |
9b998b0c | 483 | addr = video_setmem(addr); |
fe8c2806 WD |
484 | gd->fb_base = addr; |
485 | #endif /* CONFIG_VIDEO */ | |
486 | ||
487 | /* | |
488 | * reserve memory for U-Boot code, data & bss | |
682011ff | 489 | * round down to next 4 kB limit |
fe8c2806 WD |
490 | */ |
491 | addr -= len; | |
682011ff | 492 | addr &= ~(4096 - 1); |
7d314992 WD |
493 | #ifdef CONFIG_E500 |
494 | /* round down to next 64 kB limit so that IVPR stays aligned */ | |
495 | addr &= ~(65536 - 1); | |
496 | #endif | |
fe8c2806 | 497 | |
9b998b0c | 498 | debug("Reserving %ldk for U-Boot at: %08lx\n", len >> 10, addr); |
fe8c2806 WD |
499 | |
500 | /* | |
501 | * reserve memory for malloc() arena | |
502 | */ | |
503 | addr_sp = addr - TOTAL_MALLOC_LEN; | |
9b998b0c WD |
504 | debug("Reserving %dk for malloc() at: %08lx\n", |
505 | TOTAL_MALLOC_LEN >> 10, addr_sp); | |
fe8c2806 WD |
506 | |
507 | /* | |
508 | * (permanently) allocate a Board Info struct | |
509 | * and a permanent copy of the "global" data | |
510 | */ | |
9b998b0c | 511 | addr_sp -= sizeof(bd_t); |
fe8c2806 | 512 | bd = (bd_t *) addr_sp; |
a1c4864a | 513 | memset(bd, 0, sizeof(bd_t)); |
fe8c2806 | 514 | gd->bd = bd; |
9b998b0c WD |
515 | debug("Reserving %zu Bytes for Board Info at: %08lx\n", |
516 | sizeof(bd_t), addr_sp); | |
517 | addr_sp -= sizeof(gd_t); | |
fe8c2806 | 518 | id = (gd_t *) addr_sp; |
9b998b0c WD |
519 | debug("Reserving %zu Bytes for Global Data at: %08lx\n", |
520 | sizeof(gd_t), addr_sp); | |
fe8c2806 WD |
521 | |
522 | /* | |
523 | * Finally, we set up a new (bigger) stack. | |
524 | * | |
525 | * Leave some safety gap for SP, force alignment on 16 byte boundary | |
526 | * Clear initial stack frame | |
527 | */ | |
528 | addr_sp -= 16; | |
529 | addr_sp &= ~0xF; | |
9b998b0c | 530 | s = (ulong *) addr_sp; |
7de8a716 JT |
531 | *s = 0; /* Terminate back chain */ |
532 | *++s = 0; /* NULL return address */ | |
9b998b0c | 533 | debug("Stack Pointer at: %08lx\n", addr_sp); |
fe8c2806 WD |
534 | |
535 | /* | |
536 | * Save local variables to board info struct | |
537 | */ | |
538 | ||
9b998b0c WD |
539 | bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */ |
540 | bd->bi_memsize = gd->ram_size; /* size in bytes */ | |
fe8c2806 | 541 | |
36116650 | 542 | #ifdef CONFIG_SYS_SRAM_BASE |
9b998b0c WD |
543 | bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */ |
544 | bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */ | |
fe8c2806 WD |
545 | #endif |
546 | ||
42d1f039 | 547 | #if defined(CONFIG_8xx) || defined(CONFIG_8260) || defined(CONFIG_5xx) || \ |
debb7354 | 548 | defined(CONFIG_E500) || defined(CONFIG_MPC86xx) |
6d0f6bcf | 549 | bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */ |
fe8c2806 | 550 | #endif |
cbd8a35c | 551 | #if defined(CONFIG_MPC5xxx) |
6d0f6bcf | 552 | bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */ |
945af8d7 | 553 | #endif |
0f898604 | 554 | #if defined(CONFIG_MPC83xx) |
6d0f6bcf | 555 | bd->bi_immrbar = CONFIG_SYS_IMMR; |
f046ccd1 | 556 | #endif |
983fda83 | 557 | #if defined(CONFIG_MPC8220) |
6d0f6bcf | 558 | bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */ |
1c356135 | 559 | bd->bi_inpfreq = gd->arch.inp_clk; |
9b998b0c | 560 | bd->bi_pcifreq = gd->pci_clk; |
1c356135 SG |
561 | bd->bi_vcofreq = gd->arch.vco_clk; |
562 | bd->bi_pevfreq = gd->arch.pev_clk; | |
563 | bd->bi_flbfreq = gd->arch.flb_clk; | |
983fda83 | 564 | |
dd520bf3 WD |
565 | /* store bootparam to sram (backward compatible), here? */ |
566 | { | |
9b998b0c WD |
567 | u32 *sram = (u32 *) CONFIG_SYS_SRAM_BASE; |
568 | ||
dd520bf3 WD |
569 | *sram++ = gd->ram_size; |
570 | *sram++ = gd->bus_clk; | |
1c356135 | 571 | *sram++ = gd->arch.inp_clk; |
dd520bf3 | 572 | *sram++ = gd->cpu_clk; |
1c356135 SG |
573 | *sram++ = gd->arch.vco_clk; |
574 | *sram++ = gd->arch.flb_clk; | |
9b998b0c | 575 | *sram++ = 0xb8c3ba11; /* boot signature */ |
dd520bf3 | 576 | } |
983fda83 | 577 | #endif |
fe8c2806 | 578 | |
9b998b0c | 579 | WATCHDOG_RESET(); |
fe8c2806 WD |
580 | bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */ |
581 | bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */ | |
9c4c5ae3 | 582 | #if defined(CONFIG_CPM2) |
748cd059 | 583 | bd->bi_cpmfreq = gd->arch.cpm_clk; |
1206c184 | 584 | bd->bi_brgfreq = gd->arch.brg_clk; |
748cd059 SG |
585 | bd->bi_sccfreq = gd->arch.scc_clk; |
586 | bd->bi_vco = gd->arch.vco_out; | |
9c4c5ae3 | 587 | #endif /* CONFIG_CPM2 */ |
281ff9a4 | 588 | #if defined(CONFIG_MPC512X) |
fefb098b | 589 | bd->bi_ipsfreq = gd->arch.ips_clk; |
281ff9a4 | 590 | #endif /* CONFIG_MPC512X */ |
cbd8a35c | 591 | #if defined(CONFIG_MPC5xxx) |
b2877496 | 592 | bd->bi_ipbfreq = gd->arch.ipb_clk; |
945af8d7 | 593 | bd->bi_pcifreq = gd->pci_clk; |
cbd8a35c | 594 | #endif /* CONFIG_MPC5xxx */ |
fe8c2806 WD |
595 | bd->bi_baudrate = gd->baudrate; /* Console Baudrate */ |
596 | ||
6d0f6bcf | 597 | #ifdef CONFIG_SYS_EXTBDINFO |
9b998b0c WD |
598 | strncpy((char *) bd->bi_s_version, "1.2", sizeof(bd->bi_s_version)); |
599 | strncpy((char *) bd->bi_r_version, U_BOOT_VERSION, | |
600 | sizeof(bd->bi_r_version)); | |
fe8c2806 WD |
601 | |
602 | bd->bi_procfreq = gd->cpu_clk; /* Processor Speed, In Hz */ | |
603 | bd->bi_plb_busfreq = gd->bus_clk; | |
343c48bd SR |
604 | #if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \ |
605 | defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ | |
606 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) | |
9b998b0c WD |
607 | bd->bi_pci_busfreq = get_PCI_freq(); |
608 | bd->bi_opbfreq = get_OPB_freq(); | |
9fea65a6 | 609 | #elif defined(CONFIG_XILINX_405) |
9b998b0c | 610 | bd->bi_pci_busfreq = get_PCI_freq(); |
fe8c2806 WD |
611 | #endif |
612 | #endif | |
613 | ||
9b998b0c | 614 | debug("New Stack Pointer is: %08lx\n", addr_sp); |
fe8c2806 | 615 | |
9b998b0c | 616 | WATCHDOG_RESET(); |
fe8c2806 | 617 | |
9b998b0c | 618 | gd->relocaddr = addr; /* Store relocation addr, useful for debug */ |
4b99327a | 619 | |
9b998b0c | 620 | memcpy(id, (void *) gd, sizeof(gd_t)); |
fe8c2806 | 621 | |
9b998b0c | 622 | relocate_code(addr_sp, id, addr); |
fe8c2806 WD |
623 | |
624 | /* NOTREACHED - relocate_code() does not return */ | |
625 | } | |
626 | ||
9b998b0c | 627 | /* |
fe8c2806 WD |
628 | * This is the next part if the initialization sequence: we are now |
629 | * running from RAM and have a "normal" C environment, i. e. global | |
630 | * data can be written, BSS has been cleared, the stack size in not | |
631 | * that critical any more, etc. | |
fe8c2806 | 632 | */ |
9b998b0c | 633 | void board_init_r(gd_t *id, ulong dest_addr) |
fe8c2806 | 634 | { |
fe8c2806 | 635 | bd_t *bd; |
a483a167 | 636 | ulong malloc_start; |
9b998b0c | 637 | |
6d0f6bcf | 638 | #ifndef CONFIG_SYS_NO_FLASH |
fe8c2806 WD |
639 | ulong flash_size; |
640 | #endif | |
641 | ||
642 | gd = id; /* initialize RAM version of global data */ | |
643 | bd = gd->bd; | |
644 | ||
645 | gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ | |
f82b3b63 | 646 | |
d4e8ada0 | 647 | /* The Malloc area is immediately below the monitor copy in DRAM */ |
a483a167 | 648 | malloc_start = dest_addr - TOTAL_MALLOC_LEN; |
13d46ab2 | 649 | |
f9476902 PT |
650 | #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) |
651 | /* | |
67ac13b1 SG |
652 | * The gd->arch.cpu pointer is set to an address in flash before |
653 | * relocation. We need to update it to point to the same CPU entry | |
654 | * in RAM. | |
f9476902 | 655 | */ |
67ac13b1 | 656 | gd->arch.cpu += dest_addr - CONFIG_SYS_MONITOR_BASE; |
123bd96d YS |
657 | |
658 | /* | |
659 | * If we didn't know the cpu mask & # cores, we can save them of | |
660 | * now rather than 'computing' them constantly | |
661 | */ | |
662 | fixup_cpu(); | |
a55bb834 KG |
663 | #endif |
664 | ||
665 | #ifdef CONFIG_SYS_EXTRA_ENV_RELOC | |
666 | /* | |
667 | * Some systems need to relocate the env_addr pointer early because the | |
668 | * location it points to will get invalidated before env_relocate is | |
669 | * called. One example is on systems that might use a L2 or L3 cache | |
670 | * in SRAM mode and initialize that cache from SRAM mode back to being | |
671 | * a cache in cpu_init_r. | |
672 | */ | |
673 | gd->env_addr += dest_addr - CONFIG_SYS_MONITOR_BASE; | |
f9476902 PT |
674 | #endif |
675 | ||
bb105f24 | 676 | serial_initialize(); |
fe8c2806 | 677 | |
9b998b0c | 678 | debug("Now running in RAM - U-Boot at: %08lx\n", dest_addr); |
fe8c2806 | 679 | |
9b998b0c | 680 | WATCHDOG_RESET(); |
fe8c2806 | 681 | |
d025aa4b BB |
682 | /* |
683 | * Setup trap handlers | |
684 | */ | |
9b998b0c | 685 | trap_init(dest_addr); |
d025aa4b | 686 | |
c9315e6b | 687 | #ifdef CONFIG_ADDR_MAP |
ecf5b98c KG |
688 | init_addr_map(); |
689 | #endif | |
690 | ||
c837dcb1 | 691 | #if defined(CONFIG_BOARD_EARLY_INIT_R) |
9b998b0c | 692 | board_early_init_r(); |
c837dcb1 WD |
693 | #endif |
694 | ||
3b57fe0a | 695 | monitor_flash_len = (ulong)&__init_end - dest_addr; |
fe8c2806 | 696 | |
9b998b0c | 697 | WATCHDOG_RESET(); |
fe8c2806 | 698 | |
56f94be3 | 699 | #ifdef CONFIG_LOGBUFFER |
9b998b0c | 700 | logbuff_init_ptrs(); |
56f94be3 | 701 | #endif |
fe8c2806 | 702 | #ifdef CONFIG_POST |
9b998b0c | 703 | post_output_backlog(); |
fe8c2806 WD |
704 | #endif |
705 | ||
706 | WATCHDOG_RESET(); | |
707 | ||
1a2e203b | 708 | #if defined(CONFIG_SYS_DELAYED_ICACHE) |
9b998b0c | 709 | icache_enable(); /* it's time to enable the instruction cache */ |
fe8c2806 WD |
710 | #endif |
711 | ||
9c67352f WD |
712 | #if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500) |
713 | unlock_ram_in_cache(); /* it's time to unlock D-cache in e500 */ | |
42d1f039 WD |
714 | #endif |
715 | ||
76221a6c | 716 | #if defined(CONFIG_PCI) && defined(CONFIG_SYS_EARLY_PCI_INIT) |
fe8c2806 | 717 | /* |
76221a6c AS |
718 | * Do early PCI configuration _before_ the flash gets initialised, |
719 | * because PCU ressources are crucial for flash access on some boards. | |
fe8c2806 | 720 | */ |
9b998b0c | 721 | pci_init(); |
3bac3513 | 722 | #endif |
57d6c589 | 723 | #if defined(CONFIG_WINBOND_83C553) |
fe8c2806 WD |
724 | /* |
725 | * Initialise the ISA bridge | |
726 | */ | |
9b998b0c | 727 | initialise_w83c553f(); |
fe8c2806 WD |
728 | #endif |
729 | ||
9b998b0c | 730 | asm("sync ; isync"); |
fe8c2806 | 731 | |
9b998b0c | 732 | mem_malloc_init(malloc_start, TOTAL_MALLOC_LEN); |
c790b04d | 733 | |
6d0f6bcf | 734 | #if !defined(CONFIG_SYS_NO_FLASH) |
9b998b0c | 735 | puts("Flash: "); |
fe8c2806 | 736 | |
c62491d2 JS |
737 | if (board_flash_wp_on()) { |
738 | printf("Uninitialized - Write Protect On\n"); | |
739 | /* Since WP is on, we can't find real size. Set to 0 */ | |
740 | flash_size = 0; | |
9b998b0c WD |
741 | } else if ((flash_size = flash_init()) > 0) { |
742 | #ifdef CONFIG_SYS_FLASH_CHECKSUM | |
9b998b0c | 743 | print_size(flash_size, ""); |
fe8c2806 WD |
744 | /* |
745 | * Compute and print flash CRC if flashchecksum is set to 'y' | |
746 | * | |
747 | * NOTE: Maybe we should add some WATCHDOG_RESET()? XXX | |
748 | */ | |
ec8a252c | 749 | if (getenv_yesno("flashchecksum") == 1) { |
9b998b0c WD |
750 | printf(" CRC: %08X", |
751 | crc32(0, | |
752 | (const unsigned char *) | |
753 | CONFIG_SYS_FLASH_BASE, flash_size) | |
754 | ); | |
fe8c2806 | 755 | } |
9b998b0c WD |
756 | putc('\n'); |
757 | #else /* !CONFIG_SYS_FLASH_CHECKSUM */ | |
758 | print_size(flash_size, "\n"); | |
759 | #endif /* CONFIG_SYS_FLASH_CHECKSUM */ | |
fe8c2806 | 760 | } else { |
9b998b0c WD |
761 | puts(failed); |
762 | hang(); | |
fe8c2806 WD |
763 | } |
764 | ||
9b998b0c WD |
765 | /* update start of FLASH memory */ |
766 | bd->bi_flashstart = CONFIG_SYS_FLASH_BASE; | |
767 | /* size of FLASH memory (final value) */ | |
768 | bd->bi_flashsize = flash_size; | |
fa230445 | 769 | |
6d0f6bcf | 770 | #if defined(CONFIG_SYS_UPDATE_FLASH_SIZE) |
fa230445 | 771 | /* Make a update of the Memctrl. */ |
9b998b0c | 772 | update_flash_size(flash_size); |
fa230445 HS |
773 | #endif |
774 | ||
775 | ||
9b998b0c | 776 | #if defined(CONFIG_OXC) || defined(CONFIG_RMU) |
7e780369 | 777 | /* flash mapped at end of memory map */ |
14d0a02a | 778 | bd->bi_flashoffset = CONFIG_SYS_TEXT_BASE + flash_size; |
9b998b0c WD |
779 | #elif CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE |
780 | bd->bi_flashoffset = monitor_flash_len; /* reserved area for monitor */ | |
781 | #endif | |
6d0f6bcf | 782 | #endif /* !CONFIG_SYS_NO_FLASH */ |
fe8c2806 | 783 | |
9b998b0c | 784 | WATCHDOG_RESET(); |
fe8c2806 WD |
785 | |
786 | /* initialize higher level parts of CPU like time base and timers */ | |
9b998b0c | 787 | cpu_init_r(); |
fe8c2806 | 788 | |
9b998b0c | 789 | WATCHDOG_RESET(); |
fe8c2806 | 790 | |
fe8c2806 | 791 | #ifdef CONFIG_SPI |
9b998b0c WD |
792 | #if !defined(CONFIG_ENV_IS_IN_EEPROM) |
793 | spi_init_f(); | |
794 | #endif | |
795 | spi_init_r(); | |
fe8c2806 WD |
796 | #endif |
797 | ||
7def6b34 | 798 | #if defined(CONFIG_CMD_NAND) |
9b998b0c WD |
799 | WATCHDOG_RESET(); |
800 | puts("NAND: "); | |
887e2ec9 SR |
801 | nand_init(); /* go init the NAND */ |
802 | #endif | |
803 | ||
a8060359 TL |
804 | #ifdef CONFIG_GENERIC_MMC |
805 | /* | |
806 | * MMC initialization is called before relocating env. | |
807 | * Thus It is required that operations like pin multiplexer | |
808 | * be put in board_init. | |
809 | */ | |
9b998b0c WD |
810 | WATCHDOG_RESET(); |
811 | puts("MMC: "); | |
812 | mmc_initialize(bd); | |
a8060359 TL |
813 | #endif |
814 | ||
fe8c2806 | 815 | /* relocate environment function pointers etc. */ |
9b998b0c | 816 | env_relocate(); |
fe8c2806 | 817 | |
f9a33f1c KG |
818 | /* |
819 | * after non-volatile devices & environment is setup and cpu code have | |
820 | * another round to deal with any initialization that might require | |
821 | * full access to the environment or loading of some image (firmware) | |
822 | * from a non-volatile device | |
823 | */ | |
824 | cpu_secondary_init_r(); | |
825 | ||
fe8c2806 WD |
826 | /* |
827 | * Fill in missing fields of bd_info. | |
8bde7f77 WD |
828 | * We do this here, where we have "normal" access to the |
829 | * environment; we used to do this still running from ROM, | |
cdb74977 | 830 | * where had to use getenv_f(), which can be pretty slow when |
8bde7f77 | 831 | * the environment is in EEPROM. |
fe8c2806 | 832 | */ |
7abf0c58 | 833 | |
6d0f6bcf | 834 | #if defined(CONFIG_SYS_EXTBDINFO) |
7abf0c58 WD |
835 | #if defined(CONFIG_405GP) || defined(CONFIG_405EP) |
836 | #if defined(CONFIG_I2CFAST) | |
837 | /* | |
838 | * set bi_iic_fast for linux taking environment variable | |
839 | * "i2cfast" into account | |
840 | */ | |
841 | { | |
ec8a252c | 842 | if (getenv_yesno("i2cfast") == 1) { |
7abf0c58 WD |
843 | bd->bi_iic_fast[0] = 1; |
844 | bd->bi_iic_fast[1] = 1; | |
7abf0c58 WD |
845 | } |
846 | } | |
9b998b0c WD |
847 | #endif /* CONFIG_I2CFAST */ |
848 | #endif /* CONFIG_405GP, CONFIG_405EP */ | |
849 | #endif /* CONFIG_SYS_EXTBDINFO */ | |
7abf0c58 | 850 | |
9045f33c | 851 | #if defined(CONFIG_SC3) |
ca43ba18 HS |
852 | sc3_read_eeprom(); |
853 | #endif | |
d59feffb | 854 | |
9b998b0c | 855 | #if defined(CONFIG_ID_EEPROM) || defined(CONFIG_SYS_I2C_MAC_OFFSET) |
d59feffb HW |
856 | mac_read_from_eeprom(); |
857 | #endif | |
858 | ||
fe8c2806 WD |
859 | #ifdef CONFIG_HERMES |
860 | if ((gd->board_type >> 16) == 2) | |
861 | bd->bi_ethspeed = gd->board_type & 0xFFFF; | |
862 | else | |
863 | bd->bi_ethspeed = 0xFFFF; | |
864 | #endif | |
865 | ||
02a301cd | 866 | #ifdef CONFIG_CMD_NET |
eb85aa59 MF |
867 | /* kept around for legacy kernels only ... ignore the next section */ |
868 | eth_getenv_enetaddr("ethaddr", bd->bi_enetaddr); | |
e2ffd59b | 869 | #ifdef CONFIG_HAS_ETH1 |
eb85aa59 | 870 | eth_getenv_enetaddr("eth1addr", bd->bi_enet1addr); |
fe8c2806 | 871 | #endif |
e2ffd59b | 872 | #ifdef CONFIG_HAS_ETH2 |
eb85aa59 | 873 | eth_getenv_enetaddr("eth2addr", bd->bi_enet2addr); |
fe8c2806 | 874 | #endif |
e2ffd59b | 875 | #ifdef CONFIG_HAS_ETH3 |
eb85aa59 | 876 | eth_getenv_enetaddr("eth3addr", bd->bi_enet3addr); |
ba56f625 | 877 | #endif |
c68a05fe | 878 | #ifdef CONFIG_HAS_ETH4 |
eb85aa59 | 879 | eth_getenv_enetaddr("eth4addr", bd->bi_enet4addr); |
c68a05fe | 880 | #endif |
c68a05fe | 881 | #ifdef CONFIG_HAS_ETH5 |
eb85aa59 | 882 | eth_getenv_enetaddr("eth5addr", bd->bi_enet5addr); |
c68a05fe | 883 | #endif |
02a301cd | 884 | #endif /* CONFIG_CMD_NET */ |
c68a05fe | 885 | |
9b998b0c | 886 | WATCHDOG_RESET(); |
fe8c2806 | 887 | |
76221a6c | 888 | #if defined(CONFIG_PCI) && !defined(CONFIG_SYS_EARLY_PCI_INIT) |
fe8c2806 WD |
889 | /* |
890 | * Do pci configuration | |
891 | */ | |
9b998b0c | 892 | pci_init(); |
fe8c2806 WD |
893 | #endif |
894 | ||
895 | /** leave this here (after malloc(), environment and PCI are working) **/ | |
52cb4d4f | 896 | /* Initialize stdio devices */ |
9b998b0c | 897 | stdio_init(); |
fe8c2806 | 898 | |
27b207fd | 899 | /* Initialize the jump table for applications */ |
9b998b0c | 900 | jumptable_init(); |
fe8c2806 | 901 | |
500856eb RJ |
902 | #if defined(CONFIG_API) |
903 | /* Initialize API */ | |
9b998b0c | 904 | api_init(); |
500856eb RJ |
905 | #endif |
906 | ||
fe8c2806 | 907 | /* Initialize the console (after the relocation and devices init) */ |
9b998b0c | 908 | console_init_r(); |
fe8c2806 | 909 | |
3a8f28d0 | 910 | #if defined(CONFIG_MISC_INIT_R) |
fe8c2806 | 911 | /* miscellaneous platform dependent initialisations */ |
9b998b0c | 912 | misc_init_r(); |
fe8c2806 WD |
913 | #endif |
914 | ||
915 | #ifdef CONFIG_HERMES | |
916 | if (bd->bi_ethspeed != 0xFFFF) | |
9b998b0c | 917 | hermes_start_lxt980((int) bd->bi_ethspeed); |
fe8c2806 WD |
918 | #endif |
919 | ||
7def6b34 | 920 | #if defined(CONFIG_CMD_KGDB) |
9b998b0c WD |
921 | WATCHDOG_RESET(); |
922 | puts("KGDB: "); | |
923 | kgdb_init(); | |
fe8c2806 WD |
924 | #endif |
925 | ||
9b998b0c | 926 | debug("U-Boot relocated to %08lx\n", dest_addr); |
fe8c2806 WD |
927 | |
928 | /* | |
929 | * Enable Interrupts | |
930 | */ | |
9b998b0c | 931 | interrupt_init(); |
fe8c2806 | 932 | |
566a494f | 933 | #if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT) |
9b998b0c | 934 | status_led_set(STATUS_LED_BOOT, STATUS_LED_BLINKING); |
fe8c2806 WD |
935 | #endif |
936 | ||
9b998b0c | 937 | udelay(20); |
fe8c2806 | 938 | |
fe8c2806 | 939 | /* Initialize from environment */ |
1272592e | 940 | load_addr = getenv_ulong("loadaddr", 16, load_addr); |
fe8c2806 | 941 | |
9b998b0c | 942 | WATCHDOG_RESET(); |
fe8c2806 | 943 | |
7def6b34 | 944 | #if defined(CONFIG_CMD_SCSI) |
9b998b0c WD |
945 | WATCHDOG_RESET(); |
946 | puts("SCSI: "); | |
947 | scsi_init(); | |
fe8c2806 WD |
948 | #endif |
949 | ||
7def6b34 | 950 | #if defined(CONFIG_CMD_DOC) |
9b998b0c WD |
951 | WATCHDOG_RESET(); |
952 | puts("DOC: "); | |
953 | doc_init(); | |
fe8c2806 WD |
954 | #endif |
955 | ||
310cecb8 LCM |
956 | #ifdef CONFIG_BITBANGMII |
957 | bb_miiphy_init(); | |
958 | #endif | |
7def6b34 | 959 | #if defined(CONFIG_CMD_NET) |
9b998b0c WD |
960 | WATCHDOG_RESET(); |
961 | puts("Net: "); | |
962 | eth_initialize(bd); | |
fe8c2806 WD |
963 | #endif |
964 | ||
004eca0c | 965 | #if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) |
9b998b0c WD |
966 | WATCHDOG_RESET(); |
967 | debug("Reset Ethernet PHY\n"); | |
968 | reset_phy(); | |
63ff004c MB |
969 | #endif |
970 | ||
fe8c2806 | 971 | #ifdef CONFIG_POST |
9b998b0c | 972 | post_run(NULL, POST_RAM | post_bootmode_get(0)); |
fe8c2806 WD |
973 | #endif |
974 | ||
7def6b34 JL |
975 | #if defined(CONFIG_CMD_PCMCIA) \ |
976 | && !defined(CONFIG_CMD_IDE) | |
9b998b0c WD |
977 | WATCHDOG_RESET(); |
978 | puts("PCMCIA:"); | |
979 | pcmcia_init(); | |
fe8c2806 WD |
980 | #endif |
981 | ||
7def6b34 | 982 | #if defined(CONFIG_CMD_IDE) |
9b998b0c WD |
983 | WATCHDOG_RESET(); |
984 | #ifdef CONFIG_IDE_8xx_PCCARD | |
985 | puts("PCMCIA:"); | |
986 | #else | |
987 | puts("IDE: "); | |
fe8c2806 | 988 | #endif |
ca43ba18 HS |
989 | #if defined(CONFIG_START_IDE) |
990 | if (board_start_ide()) | |
9b998b0c | 991 | ide_init(); |
ca43ba18 | 992 | #else |
9b998b0c | 993 | ide_init(); |
ca43ba18 | 994 | #endif |
b3aff0cb | 995 | #endif |
fe8c2806 WD |
996 | |
997 | #ifdef CONFIG_LAST_STAGE_INIT | |
9b998b0c | 998 | WATCHDOG_RESET(); |
fe8c2806 WD |
999 | /* |
1000 | * Some parts can be only initialized if all others (like | |
1001 | * Interrupts) are up and running (i.e. the PC-style ISA | |
1002 | * keyboard). | |
1003 | */ | |
9b998b0c | 1004 | last_stage_init(); |
fe8c2806 WD |
1005 | #endif |
1006 | ||
7def6b34 | 1007 | #if defined(CONFIG_CMD_BEDBUG) |
9b998b0c WD |
1008 | WATCHDOG_RESET(); |
1009 | bedbug_init(); | |
fe8c2806 WD |
1010 | #endif |
1011 | ||
228f29ac | 1012 | #if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER) |
fe8c2806 WD |
1013 | /* |
1014 | * Export available size of memory for Linux, | |
1015 | * taking into account the protected RAM at top of memory | |
1016 | */ | |
1017 | { | |
1272592e | 1018 | ulong pram = 0; |
d01b1761 | 1019 | char memsz[32]; |
fe8c2806 | 1020 | |
1272592e SG |
1021 | #ifdef CONFIG_PRAM |
1022 | pram = getenv_ulong("pram", 10, CONFIG_PRAM); | |
228f29ac WD |
1023 | #endif |
1024 | #ifdef CONFIG_LOGBUFFER | |
3d610186 | 1025 | #ifndef CONFIG_ALT_LB_ADDR |
228f29ac | 1026 | /* Also take the logbuffer into account (pram is in kB) */ |
9b998b0c | 1027 | pram += (LOGBUFF_LEN + LOGBUFF_OVERHEAD) / 1024; |
3d610186 | 1028 | #endif |
228f29ac | 1029 | #endif |
d01b1761 SG |
1030 | sprintf(memsz, "%ldk", (bd->bi_memsize / 1024) - pram); |
1031 | setenv("mem", memsz); | |
fe8c2806 WD |
1032 | } |
1033 | #endif | |
1034 | ||
1c43771b | 1035 | #ifdef CONFIG_PS2KBD |
9b998b0c | 1036 | puts("PS/2: "); |
1c43771b WD |
1037 | kbd_init(); |
1038 | #endif | |
1039 | ||
4532cb69 | 1040 | #ifdef CONFIG_MODEM_SUPPORT |
9b998b0c WD |
1041 | { |
1042 | extern int do_mdm_init; | |
1043 | ||
1044 | do_mdm_init = gd->do_mdm_init; | |
1045 | } | |
4532cb69 WD |
1046 | #endif |
1047 | ||
fe8c2806 WD |
1048 | /* Initialization complete - start the monitor */ |
1049 | ||
1050 | /* main_loop() can return to retry autoboot, if so just run it again. */ | |
1051 | for (;;) { | |
9b998b0c WD |
1052 | WATCHDOG_RESET(); |
1053 | main_loop(); | |
fe8c2806 WD |
1054 | } |
1055 | ||
1056 | /* NOTREACHED - no way out of command loop except booting */ | |
1057 | } | |
1058 | ||
9b998b0c | 1059 | void hang(void) |
fe8c2806 | 1060 | { |
9b998b0c | 1061 | puts("### ERROR ### Please RESET the board ###\n"); |
770605e4 | 1062 | bootstage_error(BOOTSTAGE_ID_NEED_RESET); |
9b998b0c WD |
1063 | for (;;) |
1064 | ; | |
fe8c2806 WD |
1065 | } |
1066 | ||
4532cb69 | 1067 | |
9b998b0c | 1068 | #if 0 /* We could use plain global data, but the resulting code is bigger */ |
fe8c2806 WD |
1069 | /* |
1070 | * Pointer to initial global data area | |
1071 | * | |
1072 | * Here we initialize it. | |
1073 | */ | |
1074 | #undef XTRN_DECLARE_GLOBAL_DATA_PTR | |
1075 | #define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */ | |
9b998b0c WD |
1076 | DECLARE_GLOBAL_DATA_PTR = |
1077 | (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); | |
1078 | #endif /* 0 */ | |
fe8c2806 WD |
1079 | |
1080 | /************************************************************************/ |