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fe8c2806 1/*
9b998b0c 2 * (C) Copyright 2000-2011
fe8c2806
WD
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <watchdog.h>
26#include <command.h>
27#include <malloc.h>
52cb4d4f 28#include <stdio_dev.h>
fe8c2806
WD
29#ifdef CONFIG_8xx
30#include <mpc8xx.h>
31#endif
0db5bca8
WD
32#ifdef CONFIG_5xx
33#include <mpc5xx.h>
34#endif
cbd8a35c 35#ifdef CONFIG_MPC5xxx
945af8d7
WD
36#include <mpc5xxx.h>
37#endif
7def6b34 38#if defined(CONFIG_CMD_IDE)
fe8c2806
WD
39#include <ide.h>
40#endif
7def6b34 41#if defined(CONFIG_CMD_SCSI)
fe8c2806
WD
42#include <scsi.h>
43#endif
7def6b34 44#if defined(CONFIG_CMD_KGDB)
fe8c2806
WD
45#include <kgdb.h>
46#endif
47#ifdef CONFIG_STATUS_LED
48#include <status_led.h>
49#endif
50#include <net.h>
272cc70b
AF
51#ifdef CONFIG_GENERIC_MMC
52#include <mmc.h>
53#endif
281e00a3 54#include <serial.h>
6d0f6bcf 55#ifdef CONFIG_SYS_ALLOC_DPRAM
9c4c5ae3 56#if !defined(CONFIG_CPM2)
fe8c2806
WD
57#include <commproc.h>
58#endif
7aa78614 59#endif
fe8c2806
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60#include <version.h>
61#if defined(CONFIG_BAB7xx)
62#include <w83c553f.h>
63#endif
64#include <dtt.h>
65#if defined(CONFIG_POST)
66#include <post.h>
67#endif
56f94be3
WD
68#if defined(CONFIG_LOGBUFFER)
69#include <logbuff.h>
70#endif
9c67352f 71#if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500)
42d1f039
WD
72#include <asm/cache.h>
73#endif
1c43771b
WD
74#ifdef CONFIG_PS2KBD
75#include <keyboard.h>
76#endif
fe8c2806 77
ecf5b98c
KG
78#ifdef CONFIG_ADDR_MAP
79#include <asm/mmu.h>
80#endif
81
fc39c2fd
KG
82#ifdef CONFIG_MP
83#include <asm/mp.h>
84#endif
85
310cecb8
LCM
86#ifdef CONFIG_BITBANGMII
87#include <miiphy.h>
88#endif
89
6d0f6bcf 90#ifdef CONFIG_SYS_UPDATE_FLASH_SIZE
9b998b0c 91extern int update_flash_size(int flash_size);
fa230445
HS
92#endif
93
9045f33c 94#if defined(CONFIG_SC3)
ca43ba18
HS
95extern void sc3_read_eeprom(void);
96#endif
97
7def6b34 98#if defined(CONFIG_CMD_DOC)
9b998b0c 99void doc_init(void);
fe8c2806
WD
100#endif
101#if defined(CONFIG_HARD_I2C) || \
102 defined(CONFIG_SOFT_I2C)
103#include <i2c.h>
104#endif
04a9e118 105#include <spi.h>
d6ac2ed8 106#include <nand.h>
fe8c2806
WD
107
108static char *failed = "*** failed ***\n";
109
544d97e9 110#if defined(CONFIG_OXC) || defined(CONFIG_RMU)
fe8c2806 111extern flash_info_t flash_info[];
17d704eb 112#endif
fe8c2806 113
ca43ba18
HS
114#if defined(CONFIG_START_IDE)
115extern int board_start_ide(void);
116#endif
fe8c2806 117#include <environment.h>
d87080b7 118
bce84c4d 119DECLARE_GLOBAL_DATA_PTR;
fe8c2806 120
6d0f6bcf
JCPV
121#if !defined(CONFIG_SYS_MEM_TOP_HIDE)
122#define CONFIG_SYS_MEM_TOP_HIDE 0
6fb4b640
SR
123#endif
124
3b57fe0a 125extern ulong __init_end;
44c6e659 126extern ulong __bss_end__;
3b57fe0a
WD
127ulong monitor_flash_len;
128
7def6b34 129#if defined(CONFIG_CMD_BEDBUG)
8bde7f77
WD
130#include <bedbug/type.h>
131#endif
132
9b998b0c
WD
133/*
134 * Utilities
fe8c2806
WD
135 */
136
fe8c2806
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137/*
138 * All attempts to come up with a "common" initialization sequence
139 * that works for all boards and architectures failed: some of the
140 * requirements are just _too_ different. To get rid of the resulting
141 * mess of board dependend #ifdef'ed code we now make the whole
142 * initialization sequence configurable to the user.
143 *
144 * The requirements for any new initalization function is simple: it
145 * receives a pointer to the "global data" structure as it's only
146 * argument, and returns an integer return code, where 0 means
147 * "continue" and != 0 means "fatal error, hang the system".
148 */
9b998b0c 149typedef int (init_fnc_t)(void);
fe8c2806 150
9b998b0c
WD
151/*
152 * Init Utilities
153 *
fe8c2806
WD
154 * Some of this code should be moved into the core functions,
155 * but let's get it working (again) first...
156 */
157
9b998b0c 158static int init_baudrate(void)
fe8c2806 159{
1272592e
SG
160 gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);
161 return 0;
fe8c2806
WD
162}
163
164/***********************************************************************/
165
79f240f7
KP
166void __board_add_ram_info(int use_default)
167{
168 /* please define platform specific board_add_ram_info() */
169}
9b998b0c
WD
170
171void board_add_ram_info(int)
172 __attribute__ ((weak, alias("__board_add_ram_info")));
79f240f7 173
c62491d2
JS
174int __board_flash_wp_on(void)
175{
176 /*
177 * Most flashes can't be detected when write protection is enabled,
178 * so provide a way to let U-Boot gracefully ignore write protected
179 * devices.
180 */
181 return 0;
182}
9b998b0c
WD
183
184int board_flash_wp_on(void)
185 __attribute__ ((weak, alias("__board_flash_wp_on")));
d96f41e0 186
f9a33f1c
KG
187void __cpu_secondary_init_r(void)
188{
189}
9b998b0c 190
f9a33f1c 191void cpu_secondary_init_r(void)
9b998b0c 192 __attribute__ ((weak, alias("__cpu_secondary_init_r")));
f9a33f1c 193
9b998b0c 194static int init_func_ram(void)
fe8c2806 195{
fe8c2806
WD
196#ifdef CONFIG_BOARD_TYPES
197 int board_type = gd->board_type;
198#else
199 int board_type = 0; /* use dummy arg */
200#endif
9b998b0c 201 puts("DRAM: ");
fe8c2806 202
9b998b0c
WD
203 gd->ram_size = initdram(board_type);
204
205 if (gd->ram_size > 0) {
206 print_size(gd->ram_size, "");
d96f41e0 207 board_add_ram_info(0);
d96f41e0 208 putc('\n');
9b998b0c 209 return 0;
fe8c2806 210 }
9b998b0c
WD
211 puts(failed);
212 return 1;
fe8c2806
WD
213}
214
215/***********************************************************************/
216
217#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
9b998b0c 218static int init_func_i2c(void)
fe8c2806 219{
9b998b0c
WD
220 puts("I2C: ");
221 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
222 puts("ready\n");
223 return 0;
fe8c2806
WD
224}
225#endif
226
04a9e118 227#if defined(CONFIG_HARD_SPI)
9b998b0c 228static int init_func_spi(void)
04a9e118 229{
9b998b0c
WD
230 puts("SPI: ");
231 spi_init();
232 puts("ready\n");
233 return 0;
04a9e118
BW
234}
235#endif
236
fe8c2806
WD
237/***********************************************************************/
238
239#if defined(CONFIG_WATCHDOG)
9b998b0c 240static int init_func_watchdog_init(void)
fe8c2806 241{
9b998b0c
WD
242 puts(" Watchdog enabled\n");
243 WATCHDOG_RESET();
244 return 0;
fe8c2806 245}
fe8c2806 246
9b998b0c
WD
247#define INIT_FUNC_WATCHDOG_INIT init_func_watchdog_init,
248
249static int init_func_watchdog_reset(void)
fe8c2806 250{
9b998b0c
WD
251 WATCHDOG_RESET();
252 return 0;
fe8c2806 253}
9b998b0c
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254
255#define INIT_FUNC_WATCHDOG_RESET init_func_watchdog_reset,
fe8c2806 256#else
9b998b0c
WD
257#define INIT_FUNC_WATCHDOG_INIT /* undef */
258#define INIT_FUNC_WATCHDOG_RESET /* undef */
fe8c2806
WD
259#endif /* CONFIG_WATCHDOG */
260
9b998b0c
WD
261/*
262 * Initialization sequence
fe8c2806
WD
263 */
264
265init_fnc_t *init_sequence[] = {
0e870980
PA
266#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
267 probecpu,
268#endif
91525c67
AV
269#if defined(CONFIG_BOARD_EARLY_INIT_F)
270 board_early_init_f,
271#endif
66ca92a5 272#if !defined(CONFIG_8xx_CPUCLK_DEFAULT)
fe8c2806 273 get_clocks, /* get CPU and bus clocks (etc.) */
090eb735
MK
274#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \
275 && !defined(CONFIG_TQM885D)
e9132ea9
WD
276 adjust_sdram_tbs_8xx,
277#endif
fe8c2806 278 init_timebase,
c178d3da 279#endif
6d0f6bcf 280#ifdef CONFIG_SYS_ALLOC_DPRAM
9c4c5ae3 281#if !defined(CONFIG_CPM2)
fe8c2806
WD
282 dpram_init,
283#endif
7aa78614 284#endif
fe8c2806
WD
285#if defined(CONFIG_BOARD_POSTCLK_INIT)
286 board_postclk_init,
287#endif
288 env_init,
66ca92a5 289#if defined(CONFIG_8xx_CPUCLK_DEFAULT)
9b998b0c
WD
290 /* get CPU and bus clocks according to the environment variable */
291 get_clocks_866,
292 /* adjust sdram refresh rate according to the new clock */
293 sdram_adjust_866,
c178d3da
WD
294 init_timebase,
295#endif
fe8c2806
WD
296 init_baudrate,
297 serial_init,
298 console_init_f,
299 display_options,
300#if defined(CONFIG_8260)
301 prt_8260_rsr,
302 prt_8260_clks,
303#endif /* CONFIG_8260 */
0f898604 304#if defined(CONFIG_MPC83xx)
9be39a67
DL
305 prt_83xx_rsr,
306#endif
fe8c2806 307 checkcpu,
cbd8a35c 308#if defined(CONFIG_MPC5xxx)
945af8d7 309 prt_mpc5xxx_clks,
cbd8a35c 310#endif /* CONFIG_MPC5xxx */
983fda83
WD
311#if defined(CONFIG_MPC8220)
312 prt_mpc8220_clks,
313#endif
fe8c2806
WD
314 checkboard,
315 INIT_FUNC_WATCHDOG_INIT
c837dcb1 316#if defined(CONFIG_MISC_INIT_F)
fe8c2806
WD
317 misc_init_f,
318#endif
319 INIT_FUNC_WATCHDOG_RESET
320#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
321 init_func_i2c,
322#endif
04a9e118
BW
323#if defined(CONFIG_HARD_SPI)
324 init_func_spi,
325#endif
4532cb69
WD
326#ifdef CONFIG_POST
327 post_init_f,
fe8c2806 328#endif
9b998b0c 329 INIT_FUNC_WATCHDOG_RESET init_func_ram,
6d0f6bcf 330#if defined(CONFIG_SYS_DRAM_TEST)
fe8c2806 331 testdram,
6d0f6bcf 332#endif /* CONFIG_SYS_DRAM_TEST */
fe8c2806 333 INIT_FUNC_WATCHDOG_RESET
9b998b0c 334 NULL, /* Terminate this list */
fe8c2806
WD
335};
336
81d93e5c
KG
337ulong get_effective_memsize(void)
338{
339#ifndef CONFIG_VERY_BIG_RAM
340 return gd->ram_size;
341#else
342 /* limit stack to what we can reasonable map */
343 return ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ?
9b998b0c 344 CONFIG_MAX_MEM_MAPPED : gd->ram_size);
81d93e5c
KG
345#endif
346}
347
9b998b0c 348/*
fe8c2806
WD
349 * This is the first part of the initialization sequence that is
350 * implemented in C, but still running from ROM.
351 *
352 * The main purpose is to provide a (serial) console interface as
353 * soon as possible (so we can see any error messages), and to
354 * initialize the RAM so that we can relocate the monitor code to
355 * RAM.
356 *
357 * Be aware of the restrictions: global data is read-only, BSS is not
358 * initialized, and stack space is limited to a few kB.
fe8c2806
WD
359 */
360
95d449ad
MB
361#ifdef CONFIG_LOGBUFFER
362unsigned long logbuffer_base(void)
363{
6d0f6bcf 364 return CONFIG_SYS_SDRAM_BASE + get_effective_memsize() - LOGBUFF_LEN;
95d449ad
MB
365}
366#endif
367
9b998b0c 368void board_init_f(ulong bootflag)
fe8c2806 369{
fe8c2806
WD
370 bd_t *bd;
371 ulong len, addr, addr_sp;
7bc5ee07 372 ulong *s;
fe8c2806
WD
373 gd_t *id;
374 init_fnc_t **init_fnc_ptr;
9b998b0c 375
fe8c2806 376#ifdef CONFIG_PRAM
fe8c2806 377 ulong reg;
fe8c2806
WD
378#endif
379
380 /* Pointer is writable since we allocated a register for it */
6d0f6bcf 381 gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
93f6a677 382 /* compiler optimization barrier needed for GCC >= 3.4 */
9b998b0c 383 __asm__ __volatile__("":::"memory");
fe8c2806 384
82826d54
DZ
385#if !defined(CONFIG_CPM2) && !defined(CONFIG_MPC512X) && \
386 !defined(CONFIG_MPC83xx) && !defined(CONFIG_MPC85xx) && \
387 !defined(CONFIG_MPC86xx)
fe8c2806 388 /* Clear initial global data */
9b998b0c 389 memset((void *) gd, 0, sizeof(gd_t));
fe8c2806
WD
390#endif
391
9b998b0c
WD
392 for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr)
393 if ((*init_fnc_ptr) () != 0)
394 hang();
fe8c2806 395
9d256b67
BK
396#ifdef CONFIG_POST
397 post_bootmode_init();
398 post_run(NULL, POST_ROM | post_bootmode_get(0));
399#endif
400
401 WATCHDOG_RESET();
402
fe8c2806
WD
403 /*
404 * Now that we have DRAM mapped and working, we can
405 * relocate the code and continue running from DRAM.
406 *
407 * Reserve memory at end of RAM for (top down in that order):
14f73ca6 408 * - area that won't get touched by U-Boot and Linux (optional)
8bde7f77 409 * - kernel log buffer
fe8c2806
WD
410 * - protected RAM
411 * - LCD framebuffer
412 * - monitor code
413 * - board info struct
414 */
44c6e659 415 len = (ulong)&__bss_end__ - CONFIG_SYS_MONITOR_BASE;
fe8c2806 416
14f73ca6
SR
417 /*
418 * Subtract specified amount of memory to hide so that it won't
419 * get "touched" at all by U-Boot. By fixing up gd->ram_size
420 * the Linux kernel should now get passed the now "corrected"
421 * memory size and won't touch it either. This should work
422 * for arch/ppc and arch/powerpc. Only Linux board ports in
423 * arch/powerpc with bootwrapper support, that recalculate the
424 * memory size from the SDRAM controller setup will have to
425 * get fixed.
426 */
6d0f6bcf 427 gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;
14f73ca6 428
6d0f6bcf 429 addr = CONFIG_SYS_SDRAM_BASE + get_effective_memsize();
fe8c2806 430
fc39c2fd
KG
431#if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500))
432 /*
433 * We need to make sure the location we intend to put secondary core
434 * boot code is reserved and not used by any part of u-boot
c0a14aed 435 */
fc39c2fd
KG
436 if (addr > determine_mp_bootpg()) {
437 addr = determine_mp_bootpg();
9b998b0c 438 debug("Reserving MP boot page to %08lx\n", addr);
fc39c2fd
KG
439 }
440#endif
441
228f29ac 442#ifdef CONFIG_LOGBUFFER
3d610186 443#ifndef CONFIG_ALT_LB_ADDR
228f29ac
WD
444 /* reserve kernel log buffer */
445 addr -= (LOGBUFF_RESERVE);
9b998b0c
WD
446 debug("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN,
447 addr);
228f29ac 448#endif
3d610186 449#endif
228f29ac 450
fe8c2806
WD
451#ifdef CONFIG_PRAM
452 /*
453 * reserve protected RAM
454 */
1272592e 455 reg = getenv_ulong("pram", 10, CONFIG_PRAM);
9b998b0c 456 addr -= (reg << 10); /* size is in kB */
1272592e 457 debug("Reserving %ldk for protected RAM at %08lx\n", reg, addr);
fe8c2806
WD
458#endif /* CONFIG_PRAM */
459
460 /* round down to next 4 kB limit */
461 addr &= ~(4096 - 1);
9b998b0c 462 debug("Top of RAM usable for U-Boot at: %08lx\n", addr);
fe8c2806
WD
463
464#ifdef CONFIG_LCD
d32a1a4c
MK
465#ifdef CONFIG_FB_ADDR
466 gd->fb_base = CONFIG_FB_ADDR;
467#else
fe8c2806 468 /* reserve memory for LCD display (always full pages) */
9b998b0c 469 addr = lcd_setmem(addr);
fe8c2806 470 gd->fb_base = addr;
d32a1a4c 471#endif /* CONFIG_FB_ADDR */
fe8c2806
WD
472#endif /* CONFIG_LCD */
473
474#if defined(CONFIG_VIDEO) && defined(CONFIG_8xx)
475 /* reserve memory for video display (always full pages) */
9b998b0c 476 addr = video_setmem(addr);
fe8c2806
WD
477 gd->fb_base = addr;
478#endif /* CONFIG_VIDEO */
479
480 /*
481 * reserve memory for U-Boot code, data & bss
682011ff 482 * round down to next 4 kB limit
fe8c2806
WD
483 */
484 addr -= len;
682011ff 485 addr &= ~(4096 - 1);
7d314992
WD
486#ifdef CONFIG_E500
487 /* round down to next 64 kB limit so that IVPR stays aligned */
488 addr &= ~(65536 - 1);
489#endif
fe8c2806 490
9b998b0c 491 debug("Reserving %ldk for U-Boot at: %08lx\n", len >> 10, addr);
fe8c2806
WD
492
493 /*
494 * reserve memory for malloc() arena
495 */
496 addr_sp = addr - TOTAL_MALLOC_LEN;
9b998b0c
WD
497 debug("Reserving %dk for malloc() at: %08lx\n",
498 TOTAL_MALLOC_LEN >> 10, addr_sp);
fe8c2806
WD
499
500 /*
501 * (permanently) allocate a Board Info struct
502 * and a permanent copy of the "global" data
503 */
9b998b0c 504 addr_sp -= sizeof(bd_t);
fe8c2806 505 bd = (bd_t *) addr_sp;
a1c4864a 506 memset(bd, 0, sizeof(bd_t));
fe8c2806 507 gd->bd = bd;
9b998b0c
WD
508 debug("Reserving %zu Bytes for Board Info at: %08lx\n",
509 sizeof(bd_t), addr_sp);
510 addr_sp -= sizeof(gd_t);
fe8c2806 511 id = (gd_t *) addr_sp;
9b998b0c
WD
512 debug("Reserving %zu Bytes for Global Data at: %08lx\n",
513 sizeof(gd_t), addr_sp);
fe8c2806
WD
514
515 /*
516 * Finally, we set up a new (bigger) stack.
517 *
518 * Leave some safety gap for SP, force alignment on 16 byte boundary
519 * Clear initial stack frame
520 */
521 addr_sp -= 16;
522 addr_sp &= ~0xF;
9b998b0c 523 s = (ulong *) addr_sp;
7bc5ee07
WD
524 *s-- = 0;
525 *s-- = 0;
9b998b0c
WD
526 addr_sp = (ulong) s;
527 debug("Stack Pointer at: %08lx\n", addr_sp);
fe8c2806
WD
528
529 /*
530 * Save local variables to board info struct
531 */
532
9b998b0c
WD
533 bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */
534 bd->bi_memsize = gd->ram_size; /* size in bytes */
fe8c2806 535
36116650 536#ifdef CONFIG_SYS_SRAM_BASE
9b998b0c
WD
537 bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */
538 bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */
fe8c2806
WD
539#endif
540
42d1f039 541#if defined(CONFIG_8xx) || defined(CONFIG_8260) || defined(CONFIG_5xx) || \
debb7354 542 defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
6d0f6bcf 543 bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */
fe8c2806 544#endif
cbd8a35c 545#if defined(CONFIG_MPC5xxx)
6d0f6bcf 546 bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
945af8d7 547#endif
0f898604 548#if defined(CONFIG_MPC83xx)
6d0f6bcf 549 bd->bi_immrbar = CONFIG_SYS_IMMR;
f046ccd1 550#endif
983fda83 551#if defined(CONFIG_MPC8220)
6d0f6bcf 552 bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
9b998b0c
WD
553 bd->bi_inpfreq = gd->inp_clk;
554 bd->bi_pcifreq = gd->pci_clk;
555 bd->bi_vcofreq = gd->vco_clk;
556 bd->bi_pevfreq = gd->pev_clk;
557 bd->bi_flbfreq = gd->flb_clk;
983fda83 558
dd520bf3
WD
559 /* store bootparam to sram (backward compatible), here? */
560 {
9b998b0c
WD
561 u32 *sram = (u32 *) CONFIG_SYS_SRAM_BASE;
562
dd520bf3
WD
563 *sram++ = gd->ram_size;
564 *sram++ = gd->bus_clk;
565 *sram++ = gd->inp_clk;
566 *sram++ = gd->cpu_clk;
567 *sram++ = gd->vco_clk;
568 *sram++ = gd->flb_clk;
9b998b0c 569 *sram++ = 0xb8c3ba11; /* boot signature */
dd520bf3 570 }
983fda83 571#endif
fe8c2806 572
9b998b0c 573 WATCHDOG_RESET();
fe8c2806
WD
574 bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */
575 bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
9c4c5ae3 576#if defined(CONFIG_CPM2)
fe8c2806
WD
577 bd->bi_cpmfreq = gd->cpm_clk;
578 bd->bi_brgfreq = gd->brg_clk;
579 bd->bi_sccfreq = gd->scc_clk;
9b998b0c 580 bd->bi_vco = gd->vco_out;
9c4c5ae3 581#endif /* CONFIG_CPM2 */
281ff9a4 582#if defined(CONFIG_MPC512X)
5d49e0e1 583 bd->bi_ipsfreq = gd->ips_clk;
281ff9a4 584#endif /* CONFIG_MPC512X */
cbd8a35c 585#if defined(CONFIG_MPC5xxx)
945af8d7
WD
586 bd->bi_ipbfreq = gd->ipb_clk;
587 bd->bi_pcifreq = gd->pci_clk;
cbd8a35c 588#endif /* CONFIG_MPC5xxx */
fe8c2806
WD
589 bd->bi_baudrate = gd->baudrate; /* Console Baudrate */
590
6d0f6bcf 591#ifdef CONFIG_SYS_EXTBDINFO
9b998b0c
WD
592 strncpy((char *) bd->bi_s_version, "1.2", sizeof(bd->bi_s_version));
593 strncpy((char *) bd->bi_r_version, U_BOOT_VERSION,
594 sizeof(bd->bi_r_version));
fe8c2806
WD
595
596 bd->bi_procfreq = gd->cpu_clk; /* Processor Speed, In Hz */
597 bd->bi_plb_busfreq = gd->bus_clk;
343c48bd
SR
598#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
599 defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
600 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
9b998b0c
WD
601 bd->bi_pci_busfreq = get_PCI_freq();
602 bd->bi_opbfreq = get_OPB_freq();
9fea65a6 603#elif defined(CONFIG_XILINX_405)
9b998b0c 604 bd->bi_pci_busfreq = get_PCI_freq();
fe8c2806
WD
605#endif
606#endif
607
9b998b0c 608 debug("New Stack Pointer is: %08lx\n", addr_sp);
fe8c2806 609
9b998b0c 610 WATCHDOG_RESET();
fe8c2806 611
9b998b0c 612 gd->relocaddr = addr; /* Store relocation addr, useful for debug */
4b99327a 613
9b998b0c 614 memcpy(id, (void *) gd, sizeof(gd_t));
fe8c2806 615
9b998b0c 616 relocate_code(addr_sp, id, addr);
fe8c2806
WD
617
618 /* NOTREACHED - relocate_code() does not return */
619}
620
9b998b0c 621/*
fe8c2806
WD
622 * This is the next part if the initialization sequence: we are now
623 * running from RAM and have a "normal" C environment, i. e. global
624 * data can be written, BSS has been cleared, the stack size in not
625 * that critical any more, etc.
fe8c2806 626 */
9b998b0c 627void board_init_r(gd_t *id, ulong dest_addr)
fe8c2806 628{
fe8c2806 629 bd_t *bd;
a483a167 630 ulong malloc_start;
9b998b0c 631
6d0f6bcf 632#ifndef CONFIG_SYS_NO_FLASH
fe8c2806
WD
633 ulong flash_size;
634#endif
635
636 gd = id; /* initialize RAM version of global data */
637 bd = gd->bd;
638
639 gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
f82b3b63 640
d4e8ada0 641 /* The Malloc area is immediately below the monitor copy in DRAM */
a483a167 642 malloc_start = dest_addr - TOTAL_MALLOC_LEN;
13d46ab2 643
f9476902
PT
644#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
645 /*
646 * The gd->cpu pointer is set to an address in flash before relocation.
647 * We need to update it to point to the same CPU entry in RAM.
648 */
649 gd->cpu += dest_addr - CONFIG_SYS_MONITOR_BASE;
a55bb834
KG
650#endif
651
652#ifdef CONFIG_SYS_EXTRA_ENV_RELOC
653 /*
654 * Some systems need to relocate the env_addr pointer early because the
655 * location it points to will get invalidated before env_relocate is
656 * called. One example is on systems that might use a L2 or L3 cache
657 * in SRAM mode and initialize that cache from SRAM mode back to being
658 * a cache in cpu_init_r.
659 */
660 gd->env_addr += dest_addr - CONFIG_SYS_MONITOR_BASE;
f9476902
PT
661#endif
662
bb105f24
MB
663#ifdef CONFIG_SERIAL_MULTI
664 serial_initialize();
665#endif
fe8c2806 666
9b998b0c 667 debug("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
fe8c2806 668
9b998b0c 669 WATCHDOG_RESET();
fe8c2806 670
d025aa4b
BB
671 /*
672 * Setup trap handlers
673 */
9b998b0c 674 trap_init(dest_addr);
d025aa4b 675
c9315e6b 676#ifdef CONFIG_ADDR_MAP
ecf5b98c
KG
677 init_addr_map();
678#endif
679
c837dcb1 680#if defined(CONFIG_BOARD_EARLY_INIT_R)
9b998b0c 681 board_early_init_r();
c837dcb1
WD
682#endif
683
3b57fe0a 684 monitor_flash_len = (ulong)&__init_end - dest_addr;
fe8c2806 685
9b998b0c 686 WATCHDOG_RESET();
fe8c2806 687
56f94be3 688#ifdef CONFIG_LOGBUFFER
9b998b0c 689 logbuff_init_ptrs();
56f94be3 690#endif
fe8c2806 691#ifdef CONFIG_POST
9b998b0c 692 post_output_backlog();
fe8c2806
WD
693#endif
694
695 WATCHDOG_RESET();
696
1a2e203b 697#if defined(CONFIG_SYS_DELAYED_ICACHE)
9b998b0c 698 icache_enable(); /* it's time to enable the instruction cache */
fe8c2806
WD
699#endif
700
9c67352f
WD
701#if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500)
702 unlock_ram_in_cache(); /* it's time to unlock D-cache in e500 */
42d1f039
WD
703#endif
704
76221a6c 705#if defined(CONFIG_PCI) && defined(CONFIG_SYS_EARLY_PCI_INIT)
fe8c2806 706 /*
76221a6c
AS
707 * Do early PCI configuration _before_ the flash gets initialised,
708 * because PCU ressources are crucial for flash access on some boards.
fe8c2806 709 */
9b998b0c 710 pci_init();
3bac3513 711#endif
57d6c589 712#if defined(CONFIG_WINBOND_83C553)
fe8c2806
WD
713 /*
714 * Initialise the ISA bridge
715 */
9b998b0c 716 initialise_w83c553f();
fe8c2806
WD
717#endif
718
9b998b0c 719 asm("sync ; isync");
fe8c2806 720
9b998b0c 721 mem_malloc_init(malloc_start, TOTAL_MALLOC_LEN);
c790b04d 722
6d0f6bcf 723#if !defined(CONFIG_SYS_NO_FLASH)
9b998b0c 724 puts("Flash: ");
fe8c2806 725
c62491d2
JS
726 if (board_flash_wp_on()) {
727 printf("Uninitialized - Write Protect On\n");
728 /* Since WP is on, we can't find real size. Set to 0 */
729 flash_size = 0;
9b998b0c
WD
730 } else if ((flash_size = flash_init()) > 0) {
731#ifdef CONFIG_SYS_FLASH_CHECKSUM
aab773a4
SG
732 char *s;
733
9b998b0c 734 print_size(flash_size, "");
fe8c2806
WD
735 /*
736 * Compute and print flash CRC if flashchecksum is set to 'y'
737 *
738 * NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
739 */
9b998b0c 740 s = getenv("flashchecksum");
fe8c2806 741 if (s && (*s == 'y')) {
9b998b0c
WD
742 printf(" CRC: %08X",
743 crc32(0,
744 (const unsigned char *)
745 CONFIG_SYS_FLASH_BASE, flash_size)
746 );
fe8c2806 747 }
9b998b0c
WD
748 putc('\n');
749#else /* !CONFIG_SYS_FLASH_CHECKSUM */
750 print_size(flash_size, "\n");
751#endif /* CONFIG_SYS_FLASH_CHECKSUM */
fe8c2806 752 } else {
9b998b0c
WD
753 puts(failed);
754 hang();
fe8c2806
WD
755 }
756
9b998b0c
WD
757 /* update start of FLASH memory */
758 bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
759 /* size of FLASH memory (final value) */
760 bd->bi_flashsize = flash_size;
fa230445 761
6d0f6bcf 762#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
fa230445 763 /* Make a update of the Memctrl. */
9b998b0c 764 update_flash_size(flash_size);
fa230445
HS
765#endif
766
767
9b998b0c 768#if defined(CONFIG_OXC) || defined(CONFIG_RMU)
7e780369 769 /* flash mapped at end of memory map */
14d0a02a 770 bd->bi_flashoffset = CONFIG_SYS_TEXT_BASE + flash_size;
9b998b0c
WD
771#elif CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE
772 bd->bi_flashoffset = monitor_flash_len; /* reserved area for monitor */
773#endif
6d0f6bcf 774#endif /* !CONFIG_SYS_NO_FLASH */
fe8c2806 775
9b998b0c 776 WATCHDOG_RESET();
fe8c2806
WD
777
778 /* initialize higher level parts of CPU like time base and timers */
9b998b0c 779 cpu_init_r();
fe8c2806 780
9b998b0c 781 WATCHDOG_RESET();
fe8c2806 782
fe8c2806 783#ifdef CONFIG_SPI
9b998b0c
WD
784#if !defined(CONFIG_ENV_IS_IN_EEPROM)
785 spi_init_f();
786#endif
787 spi_init_r();
fe8c2806
WD
788#endif
789
7def6b34 790#if defined(CONFIG_CMD_NAND)
9b998b0c
WD
791 WATCHDOG_RESET();
792 puts("NAND: ");
887e2ec9
SR
793 nand_init(); /* go init the NAND */
794#endif
795
a8060359
TL
796#ifdef CONFIG_GENERIC_MMC
797/*
798 * MMC initialization is called before relocating env.
799 * Thus It is required that operations like pin multiplexer
800 * be put in board_init.
801 */
9b998b0c
WD
802 WATCHDOG_RESET();
803 puts("MMC: ");
804 mmc_initialize(bd);
a8060359
TL
805#endif
806
fe8c2806 807 /* relocate environment function pointers etc. */
9b998b0c 808 env_relocate();
fe8c2806 809
f9a33f1c
KG
810 /*
811 * after non-volatile devices & environment is setup and cpu code have
812 * another round to deal with any initialization that might require
813 * full access to the environment or loading of some image (firmware)
814 * from a non-volatile device
815 */
816 cpu_secondary_init_r();
817
fe8c2806
WD
818 /*
819 * Fill in missing fields of bd_info.
8bde7f77
WD
820 * We do this here, where we have "normal" access to the
821 * environment; we used to do this still running from ROM,
cdb74977 822 * where had to use getenv_f(), which can be pretty slow when
8bde7f77 823 * the environment is in EEPROM.
fe8c2806 824 */
7abf0c58 825
6d0f6bcf 826#if defined(CONFIG_SYS_EXTBDINFO)
7abf0c58
WD
827#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
828#if defined(CONFIG_I2CFAST)
829 /*
830 * set bi_iic_fast for linux taking environment variable
831 * "i2cfast" into account
832 */
833 {
9b998b0c
WD
834 char *s = getenv("i2cfast");
835
7abf0c58
WD
836 if (s && ((*s == 'y') || (*s == 'Y'))) {
837 bd->bi_iic_fast[0] = 1;
838 bd->bi_iic_fast[1] = 1;
7abf0c58
WD
839 }
840 }
9b998b0c
WD
841#endif /* CONFIG_I2CFAST */
842#endif /* CONFIG_405GP, CONFIG_405EP */
843#endif /* CONFIG_SYS_EXTBDINFO */
7abf0c58 844
9045f33c 845#if defined(CONFIG_SC3)
ca43ba18
HS
846 sc3_read_eeprom();
847#endif
d59feffb 848
9b998b0c 849#if defined(CONFIG_ID_EEPROM) || defined(CONFIG_SYS_I2C_MAC_OFFSET)
d59feffb
HW
850 mac_read_from_eeprom();
851#endif
852
fe8c2806
WD
853#ifdef CONFIG_HERMES
854 if ((gd->board_type >> 16) == 2)
855 bd->bi_ethspeed = gd->board_type & 0xFFFF;
856 else
857 bd->bi_ethspeed = 0xFFFF;
858#endif
859
02a301cd 860#ifdef CONFIG_CMD_NET
eb85aa59
MF
861 /* kept around for legacy kernels only ... ignore the next section */
862 eth_getenv_enetaddr("ethaddr", bd->bi_enetaddr);
e2ffd59b 863#ifdef CONFIG_HAS_ETH1
eb85aa59 864 eth_getenv_enetaddr("eth1addr", bd->bi_enet1addr);
fe8c2806 865#endif
e2ffd59b 866#ifdef CONFIG_HAS_ETH2
eb85aa59 867 eth_getenv_enetaddr("eth2addr", bd->bi_enet2addr);
fe8c2806 868#endif
e2ffd59b 869#ifdef CONFIG_HAS_ETH3
eb85aa59 870 eth_getenv_enetaddr("eth3addr", bd->bi_enet3addr);
ba56f625 871#endif
c68a05fe 872#ifdef CONFIG_HAS_ETH4
eb85aa59 873 eth_getenv_enetaddr("eth4addr", bd->bi_enet4addr);
c68a05fe 874#endif
c68a05fe 875#ifdef CONFIG_HAS_ETH5
eb85aa59 876 eth_getenv_enetaddr("eth5addr", bd->bi_enet5addr);
c68a05fe 877#endif
02a301cd 878#endif /* CONFIG_CMD_NET */
c68a05fe 879
fe8c2806 880 /* IP Address */
9b998b0c 881 bd->bi_ip_addr = getenv_IPaddr("ipaddr");
fe8c2806 882
9b998b0c 883 WATCHDOG_RESET();
fe8c2806 884
76221a6c 885#if defined(CONFIG_PCI) && !defined(CONFIG_SYS_EARLY_PCI_INIT)
fe8c2806
WD
886 /*
887 * Do pci configuration
888 */
9b998b0c 889 pci_init();
fe8c2806
WD
890#endif
891
892/** leave this here (after malloc(), environment and PCI are working) **/
52cb4d4f 893 /* Initialize stdio devices */
9b998b0c 894 stdio_init();
fe8c2806 895
27b207fd 896 /* Initialize the jump table for applications */
9b998b0c 897 jumptable_init();
fe8c2806 898
500856eb
RJ
899#if defined(CONFIG_API)
900 /* Initialize API */
9b998b0c 901 api_init();
500856eb
RJ
902#endif
903
fe8c2806 904 /* Initialize the console (after the relocation and devices init) */
9b998b0c 905 console_init_r();
fe8c2806 906
3a8f28d0 907#if defined(CONFIG_MISC_INIT_R)
fe8c2806 908 /* miscellaneous platform dependent initialisations */
9b998b0c 909 misc_init_r();
fe8c2806
WD
910#endif
911
912#ifdef CONFIG_HERMES
913 if (bd->bi_ethspeed != 0xFFFF)
9b998b0c 914 hermes_start_lxt980((int) bd->bi_ethspeed);
fe8c2806
WD
915#endif
916
7def6b34 917#if defined(CONFIG_CMD_KGDB)
9b998b0c
WD
918 WATCHDOG_RESET();
919 puts("KGDB: ");
920 kgdb_init();
fe8c2806
WD
921#endif
922
9b998b0c 923 debug("U-Boot relocated to %08lx\n", dest_addr);
fe8c2806
WD
924
925 /*
926 * Enable Interrupts
927 */
9b998b0c 928 interrupt_init();
fe8c2806 929
566a494f 930#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
9b998b0c 931 status_led_set(STATUS_LED_BOOT, STATUS_LED_BLINKING);
fe8c2806
WD
932#endif
933
9b998b0c 934 udelay(20);
fe8c2806 935
fe8c2806 936 /* Initialize from environment */
1272592e 937 load_addr = getenv_ulong("loadaddr", 16, load_addr);
7def6b34 938#if defined(CONFIG_CMD_NET)
aab773a4
SG
939 {
940 char *s = getenv("bootfile");
941
942 if (s != NULL)
943 copy_filename(BootFile, s, sizeof(BootFile));
fe8c2806 944 }
b3aff0cb 945#endif
fe8c2806 946
9b998b0c 947 WATCHDOG_RESET();
fe8c2806 948
7def6b34 949#if defined(CONFIG_CMD_SCSI)
9b998b0c
WD
950 WATCHDOG_RESET();
951 puts("SCSI: ");
952 scsi_init();
fe8c2806
WD
953#endif
954
7def6b34 955#if defined(CONFIG_CMD_DOC)
9b998b0c
WD
956 WATCHDOG_RESET();
957 puts("DOC: ");
958 doc_init();
fe8c2806
WD
959#endif
960
310cecb8
LCM
961#ifdef CONFIG_BITBANGMII
962 bb_miiphy_init();
963#endif
7def6b34 964#if defined(CONFIG_CMD_NET)
9b998b0c
WD
965 WATCHDOG_RESET();
966 puts("Net: ");
967 eth_initialize(bd);
fe8c2806
WD
968#endif
969
004eca0c 970#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
9b998b0c
WD
971 WATCHDOG_RESET();
972 debug("Reset Ethernet PHY\n");
973 reset_phy();
63ff004c
MB
974#endif
975
fe8c2806 976#ifdef CONFIG_POST
9b998b0c 977 post_run(NULL, POST_RAM | post_bootmode_get(0));
fe8c2806
WD
978#endif
979
7def6b34
JL
980#if defined(CONFIG_CMD_PCMCIA) \
981 && !defined(CONFIG_CMD_IDE)
9b998b0c
WD
982 WATCHDOG_RESET();
983 puts("PCMCIA:");
984 pcmcia_init();
fe8c2806
WD
985#endif
986
7def6b34 987#if defined(CONFIG_CMD_IDE)
9b998b0c
WD
988 WATCHDOG_RESET();
989#ifdef CONFIG_IDE_8xx_PCCARD
990 puts("PCMCIA:");
991#else
992 puts("IDE: ");
fe8c2806 993#endif
ca43ba18
HS
994#if defined(CONFIG_START_IDE)
995 if (board_start_ide())
9b998b0c 996 ide_init();
ca43ba18 997#else
9b998b0c 998 ide_init();
ca43ba18 999#endif
b3aff0cb 1000#endif
fe8c2806
WD
1001
1002#ifdef CONFIG_LAST_STAGE_INIT
9b998b0c 1003 WATCHDOG_RESET();
fe8c2806
WD
1004 /*
1005 * Some parts can be only initialized if all others (like
1006 * Interrupts) are up and running (i.e. the PC-style ISA
1007 * keyboard).
1008 */
9b998b0c 1009 last_stage_init();
fe8c2806
WD
1010#endif
1011
7def6b34 1012#if defined(CONFIG_CMD_BEDBUG)
9b998b0c
WD
1013 WATCHDOG_RESET();
1014 bedbug_init();
fe8c2806
WD
1015#endif
1016
228f29ac 1017#if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER)
fe8c2806
WD
1018 /*
1019 * Export available size of memory for Linux,
1020 * taking into account the protected RAM at top of memory
1021 */
1022 {
1272592e 1023 ulong pram = 0;
d01b1761 1024 char memsz[32];
fe8c2806 1025
1272592e
SG
1026#ifdef CONFIG_PRAM
1027 pram = getenv_ulong("pram", 10, CONFIG_PRAM);
228f29ac
WD
1028#endif
1029#ifdef CONFIG_LOGBUFFER
3d610186 1030#ifndef CONFIG_ALT_LB_ADDR
228f29ac 1031 /* Also take the logbuffer into account (pram is in kB) */
9b998b0c 1032 pram += (LOGBUFF_LEN + LOGBUFF_OVERHEAD) / 1024;
3d610186 1033#endif
228f29ac 1034#endif
d01b1761
SG
1035 sprintf(memsz, "%ldk", (bd->bi_memsize / 1024) - pram);
1036 setenv("mem", memsz);
fe8c2806
WD
1037 }
1038#endif
1039
1c43771b 1040#ifdef CONFIG_PS2KBD
9b998b0c 1041 puts("PS/2: ");
1c43771b
WD
1042 kbd_init();
1043#endif
1044
4532cb69 1045#ifdef CONFIG_MODEM_SUPPORT
9b998b0c
WD
1046 {
1047 extern int do_mdm_init;
1048
1049 do_mdm_init = gd->do_mdm_init;
1050 }
4532cb69
WD
1051#endif
1052
fe8c2806
WD
1053 /* Initialization complete - start the monitor */
1054
1055 /* main_loop() can return to retry autoboot, if so just run it again. */
1056 for (;;) {
9b998b0c
WD
1057 WATCHDOG_RESET();
1058 main_loop();
fe8c2806
WD
1059 }
1060
1061 /* NOTREACHED - no way out of command loop except booting */
1062}
1063
9b998b0c 1064void hang(void)
fe8c2806 1065{
9b998b0c 1066 puts("### ERROR ### Please RESET the board ###\n");
8ade9506 1067 show_boot_error(BOOTSTAGE_ID_NEED_RESET);
9b998b0c
WD
1068 for (;;)
1069 ;
fe8c2806
WD
1070}
1071
4532cb69 1072
9b998b0c 1073#if 0 /* We could use plain global data, but the resulting code is bigger */
fe8c2806
WD
1074/*
1075 * Pointer to initial global data area
1076 *
1077 * Here we initialize it.
1078 */
1079#undef XTRN_DECLARE_GLOBAL_DATA_PTR
1080#define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */
9b998b0c
WD
1081DECLARE_GLOBAL_DATA_PTR =
1082 (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
1083#endif /* 0 */
fe8c2806
WD
1084
1085/************************************************************************/