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Commit | Line | Data |
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affae2bf WD |
1 | /* |
2 | * (C) Copyright 2002 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
affae2bf WD |
6 | */ |
7 | ||
8 | #include <common.h> | |
9b94ac61 | 9 | #include <asm/cache.h> |
138105ef | 10 | #include <watchdog.h> |
0db5bca8 | 11 | |
e39cd81c | 12 | void flush_cache(ulong start_addr, ulong size) |
affae2bf | 13 | { |
0db5bca8 | 14 | #ifndef CONFIG_5xx |
e39cd81c | 15 | ulong addr, start, end; |
affae2bf | 16 | |
e39cd81c DL |
17 | start = start_addr & ~(CONFIG_SYS_CACHELINE_SIZE - 1); |
18 | end = start_addr + size - 1; | |
affae2bf | 19 | |
bced7cce KG |
20 | for (addr = start; (addr <= end) && (addr >= start); |
21 | addr += CONFIG_SYS_CACHELINE_SIZE) { | |
e39cd81c DL |
22 | asm volatile("dcbst 0,%0" : : "r" (addr) : "memory"); |
23 | WATCHDOG_RESET(); | |
affae2bf | 24 | } |
e39cd81c DL |
25 | /* wait for all dcbst to complete on bus */ |
26 | asm volatile("sync" : : : "memory"); | |
27 | ||
bced7cce KG |
28 | for (addr = start; (addr <= end) && (addr >= start); |
29 | addr += CONFIG_SYS_CACHELINE_SIZE) { | |
e39cd81c DL |
30 | asm volatile("icbi 0,%0" : : "r" (addr) : "memory"); |
31 | WATCHDOG_RESET(); | |
32 | } | |
33 | asm volatile("sync" : : : "memory"); | |
34 | /* flush prefetch queue */ | |
35 | asm volatile("isync" : : : "memory"); | |
0db5bca8 | 36 | #endif |
affae2bf | 37 | } |