[thirdparty/linux.git] / arch / powerpc / mm / book3s64 / hash_pgtable.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright 2005, Paul Mackerras, IBM Corporation.
 * Copyright 2009, Benjamin Herrenschmidt, IBM Corporation.
 * Copyright 2015-2016, Aneesh Kumar K.V, IBM Corporation.
 */

#include <linux/sched.h>
#include <linux/mm_types.h>
#include <linux/mm.h>

#include <asm/pgalloc.h>
#include <asm/sections.h>
#include <asm/mmu.h>
#include <asm/tlb.h>

#include <mm/mmu_decl.h>

#define CREATE_TRACE_POINTS
#include <trace/events/thp.h>

#if H_PGTABLE_RANGE > (USER_VSID_RANGE * (TASK_SIZE_USER64 / TASK_CONTEXT_SIZE))
#warning Limited user VSID range means pagetable space is wasted
#endif

#ifdef CONFIG_SPARSEMEM_VMEMMAP
/*
 * vmemmap is the starting address of the virtual address space where
 * struct pages are allocated for all possible PFNs present on the system
 * including holes and bad memory (hence sparse). These virtual struct
 * pages are stored in sequence in this virtual address space irrespective
 * of the fact whether the corresponding PFN is valid or not. This achieves
 * constant relationship between address of struct page and its PFN.
 *
 * During boot or memory hotplug operation when a new memory section is
 * added, physical memory allocation (including hash table bolting) will
 * be performed for the set of struct pages which are part of the memory
 * section. This saves memory by not allocating struct pages for PFNs
 * which are not valid.
 *
 *		----------------------------------------------
 *		| PHYSICAL ALLOCATION OF VIRTUAL STRUCT PAGES|
 *		----------------------------------------------
 *
 *	   f000000000000000                  c000000000000000
 * vmemmap +--------------+                  +--------------+
 *  +      |  page struct | +--------------> |  page struct |
 *  |      +--------------+                  +--------------+
 *  |      |  page struct | +--------------> |  page struct |
 *  |      +--------------+ |                +--------------+
 *  |      |  page struct | +       +------> |  page struct |
 *  |      +--------------+         |        +--------------+
 *  |      |  page struct |         |   +--> |  page struct |
 *  |      +--------------+         |   |    +--------------+
 *  |      |  page struct |         |   |
 *  |      +--------------+         |   |
 *  |      |  page struct |         |   |
 *  |      +--------------+         |   |
 *  |      |  page struct |         |   |
 *  |      +--------------+         |   |
 *  |      |  page struct |         |   |
 *  |      +--------------+         |   |
 *  |      |  page struct | +-------+   |
 *  |      +--------------+             |
 *  |      |  page struct | +-----------+
 *  |      +--------------+
 *  |      |  page struct | No mapping
 *  |      +--------------+
 *  |      |  page struct | No mapping
 *  v      +--------------+
 *
 *		-----------------------------------------
 *		| RELATION BETWEEN STRUCT PAGES AND PFNS|
 *		-----------------------------------------
 *
 * vmemmap +--------------+                 +---------------+
 *  +      |  page struct | +-------------> |      PFN      |
 *  |      +--------------+                 +---------------+
 *  |      |  page struct | +-------------> |      PFN      |
 *  |      +--------------+                 +---------------+
 *  |      |  page struct | +-------------> |      PFN      |
 *  |      +--------------+                 +---------------+
 *  |      |  page struct | +-------------> |      PFN      |
 *  |      +--------------+                 +---------------+
 *  |      |              |
 *  |      +--------------+
 *  |      |              |
 *  |      +--------------+
 *  |      |              |
 *  |      +--------------+                 +---------------+
 *  |      |  page struct | +-------------> |      PFN      |
 *  |      +--------------+                 +---------------+
 *  |      |              |
 *  |      +--------------+
 *  |      |              |
 *  |      +--------------+                 +---------------+
 *  |      |  page struct | +-------------> |      PFN      |
 *  |      +--------------+                 +---------------+
 *  |      |  page struct | +-------------> |      PFN      |
 *  v      +--------------+                 +---------------+
 */
/*
 * On hash-based CPUs, the vmemmap is bolted in the hash table.
 *
 */
int __meminit hash__vmemmap_create_mapping(unsigned long start,
				       unsigned long page_size,
				       unsigned long phys)
{
	int rc;

	if ((start + page_size) >= H_VMEMMAP_END) {
		pr_warn("Outside the supported range\n");
		return -1;
	}

	rc = htab_bolt_mapping(start, start + page_size, phys,
			       pgprot_val(PAGE_KERNEL),
			       mmu_vmemmap_psize, mmu_kernel_ssize);
	if (rc < 0) {
		int rc2 = htab_remove_mapping(start, start + page_size,
					      mmu_vmemmap_psize,
					      mmu_kernel_ssize);
		BUG_ON(rc2 && (rc2 != -ENOENT));
	}
	return rc;
}

#ifdef CONFIG_MEMORY_HOTPLUG
void hash__vmemmap_remove_mapping(unsigned long start,
			      unsigned long page_size)
{
	int rc = htab_remove_mapping(start, start + page_size,
				     mmu_vmemmap_psize,
				     mmu_kernel_ssize);
	BUG_ON((rc < 0) && (rc != -ENOENT));
	WARN_ON(rc == -ENOENT);
}
#endif
#endif /* CONFIG_SPARSEMEM_VMEMMAP */

/*
 * map_kernel_page currently only called by __ioremap
 * map_kernel_page adds an entry to the ioremap page table
 * and adds an entry to the HPT, possibly bolting it
 */
int hash__map_kernel_page(unsigned long ea, unsigned long pa, pgprot_t prot)
{
	pgd_t *pgdp;
	p4d_t *p4dp;
	pud_t *pudp;
	pmd_t *pmdp;
	pte_t *ptep;

	BUILD_BUG_ON(TASK_SIZE_USER64 > H_PGTABLE_RANGE);
	if (slab_is_available()) {
		pgdp = pgd_offset_k(ea);
		p4dp = p4d_offset(pgdp, ea);
		pudp = pud_alloc(&init_mm, p4dp, ea);
		if (!pudp)
			return -ENOMEM;
		pmdp = pmd_alloc(&init_mm, pudp, ea);
		if (!pmdp)
			return -ENOMEM;
		ptep = pte_alloc_kernel(pmdp, ea);
		if (!ptep)
			return -ENOMEM;
		set_pte_at(&init_mm, ea, ptep, pfn_pte(pa >> PAGE_SHIFT, prot));
	} else {
		/*
		 * If the mm subsystem is not fully up, we cannot create a
		 * linux page table entry for this mapping.  Simply bolt an
		 * entry in the hardware page table.
		 *
		 */
		if (htab_bolt_mapping(ea, ea + PAGE_SIZE, pa, pgprot_val(prot),
				      mmu_io_psize, mmu_kernel_ssize)) {
			printk(KERN_ERR "Failed to do bolted mapping IO "
			       "memory at %016lx !\n", pa);
			return -ENOMEM;
		}
	}

	smp_wmb();
	return 0;
}

#ifdef CONFIG_TRANSPARENT_HUGEPAGE

unsigned long hash__pmd_hugepage_update(struct mm_struct *mm, unsigned long addr,
				    pmd_t *pmdp, unsigned long clr,
				    unsigned long set)
{
	__be64 old_be, tmp;
	unsigned long old;

#ifdef CONFIG_DEBUG_VM
	WARN_ON(!hash__pmd_trans_huge(*pmdp) && !pmd_devmap(*pmdp));
	assert_spin_locked(pmd_lockptr(mm, pmdp));
#endif

	__asm__ __volatile__(
	"1:	ldarx	%0,0,%3\n\
		and.	%1,%0,%6\n\
		bne-	1b \n\
		andc	%1,%0,%4 \n\
		or	%1,%1,%7\n\
		stdcx.	%1,0,%3 \n\
		bne-	1b"
	: "=&r" (old_be), "=&r" (tmp), "=m" (*pmdp)
	: "r" (pmdp), "r" (cpu_to_be64(clr)), "m" (*pmdp),
	  "r" (cpu_to_be64(H_PAGE_BUSY)), "r" (cpu_to_be64(set))
	: "cc" );

	old = be64_to_cpu(old_be);

	trace_hugepage_update(addr, old, clr, set);
	if (old & H_PAGE_HASHPTE)
		hpte_do_hugepage_flush(mm, addr, pmdp, old);
	return old;
}

pmd_t hash__pmdp_collapse_flush(struct vm_area_struct *vma, unsigned long address,
			    pmd_t *pmdp)
{
	pmd_t pmd;

	VM_BUG_ON(address & ~HPAGE_PMD_MASK);
	VM_BUG_ON(pmd_trans_huge(*pmdp));
	VM_BUG_ON(pmd_devmap(*pmdp));

	pmd = *pmdp;
	pmd_clear(pmdp);
	/*
	 * Wait for all pending hash_page to finish. This is needed
	 * in case of subpage collapse. When we collapse normal pages
	 * to hugepage, we first clear the pmd, then invalidate all
	 * the PTE entries. The assumption here is that any low level
	 * page fault will see a none pmd and take the slow path that
	 * will wait on mmap_lock. But we could very well be in a
	 * hash_page with local ptep pointer value. Such a hash page
	 * can result in adding new HPTE entries for normal subpages.
	 * That means we could be modifying the page content as we
	 * copy them to a huge page. So wait for parallel hash_page
	 * to finish before invalidating HPTE entries. We can do this
	 * by sending an IPI to all the cpus and executing a dummy
	 * function there.
	 */
	serialize_against_pte_lookup(vma->vm_mm);
	/*
	 * Now invalidate the hpte entries in the range
	 * covered by pmd. This make sure we take a
	 * fault and will find the pmd as none, which will
	 * result in a major fault which takes mmap_lock and
	 * hence wait for collapse to complete. Without this
	 * the __collapse_huge_page_copy can result in copying
	 * the old content.
	 */
	flush_tlb_pmd_range(vma->vm_mm, &pmd, address);
	return pmd;
}

/*
 * We want to put the pgtable in pmd and use pgtable for tracking
 * the base page size hptes
 */
void hash__pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
				  pgtable_t pgtable)
{
	pgtable_t *pgtable_slot;

	assert_spin_locked(pmd_lockptr(mm, pmdp));
	/*
	 * we store the pgtable in the second half of PMD
	 */
	pgtable_slot = (pgtable_t *)pmdp + PTRS_PER_PMD;
	*pgtable_slot = pgtable;
	/*
	 * expose the deposited pgtable to other cpus.
	 * before we set the hugepage PTE at pmd level
	 * hash fault code looks at the deposted pgtable
	 * to store hash index values.
	 */
	smp_wmb();
}

pgtable_t hash__pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp)
{
	pgtable_t pgtable;
	pgtable_t *pgtable_slot;

	assert_spin_locked(pmd_lockptr(mm, pmdp));

	pgtable_slot = (pgtable_t *)pmdp + PTRS_PER_PMD;
	pgtable = *pgtable_slot;
	/*
	 * Once we withdraw, mark the entry NULL.
	 */
	*pgtable_slot = NULL;
	/*
	 * We store HPTE information in the deposited PTE fragment.
	 * zero out the content on withdraw.
	 */
	memset(pgtable, 0, PTE_FRAG_SIZE);
	return pgtable;
}

/*
 * A linux hugepage PMD was changed and the corresponding hash table entries
 * neesd to be flushed.
 */
void hpte_do_hugepage_flush(struct mm_struct *mm, unsigned long addr,
			    pmd_t *pmdp, unsigned long old_pmd)
{
	int ssize;
	unsigned int psize;
	unsigned long vsid;
	unsigned long flags = 0;

	/* get the base page size,vsid and segment size */
#ifdef CONFIG_DEBUG_VM
	psize = get_slice_psize(mm, addr);
	BUG_ON(psize == MMU_PAGE_16M);
#endif
	if (old_pmd & H_PAGE_COMBO)
		psize = MMU_PAGE_4K;
	else
		psize = MMU_PAGE_64K;

	if (!is_kernel_addr(addr)) {
		ssize = user_segment_size(addr);
		vsid = get_user_vsid(&mm->context, addr, ssize);
		WARN_ON(vsid == 0);
	} else {
		vsid = get_kernel_vsid(addr, mmu_kernel_ssize);
		ssize = mmu_kernel_ssize;
	}

	if (mm_is_thread_local(mm))
		flags |= HPTE_LOCAL_UPDATE;

	return flush_hash_hugepage(vsid, addr, pmdp, psize, ssize, flags);
}

pmd_t hash__pmdp_huge_get_and_clear(struct mm_struct *mm,
				unsigned long addr, pmd_t *pmdp)
{
	pmd_t old_pmd;
	pgtable_t pgtable;
	unsigned long old;
	pgtable_t *pgtable_slot;

	old = pmd_hugepage_update(mm, addr, pmdp, ~0UL, 0);
	old_pmd = __pmd(old);
	/*
	 * We have pmd == none and we are holding page_table_lock.
	 * So we can safely go and clear the pgtable hash
	 * index info.
	 */
	pgtable_slot = (pgtable_t *)pmdp + PTRS_PER_PMD;
	pgtable = *pgtable_slot;
	/*
	 * Let's zero out old valid and hash index details
	 * hash fault look at them.
	 */
	memset(pgtable, 0, PTE_FRAG_SIZE);
	return old_pmd;
}

int hash__has_transparent_hugepage(void)
{

	if (!mmu_has_feature(MMU_FTR_16M_PAGE))
		return 0;
	/*
	 * We support THP only if PMD_SIZE is 16MB.
	 */
	if (mmu_psize_defs[MMU_PAGE_16M].shift != PMD_SHIFT)
		return 0;
	/*
	 * We need to make sure that we support 16MB hugepage in a segement
	 * with base page size 64K or 4K. We only enable THP with a PAGE_SIZE
	 * of 64K.
	 */
	/*
	 * If we have 64K HPTE, we will be using that by default
	 */
	if (mmu_psize_defs[MMU_PAGE_64K].shift &&
	    (mmu_psize_defs[MMU_PAGE_64K].penc[MMU_PAGE_16M] == -1))
		return 0;
	/*
	 * Ok we only have 4K HPTE
	 */
	if (mmu_psize_defs[MMU_PAGE_4K].penc[MMU_PAGE_16M] == -1)
		return 0;

	return 1;
}
EXPORT_SYMBOL_GPL(hash__has_transparent_hugepage);

#endif /* CONFIG_TRANSPARENT_HUGEPAGE */

#ifdef CONFIG_STRICT_KERNEL_RWX
static bool hash__change_memory_range(unsigned long start, unsigned long end,
				      unsigned long newpp)
{
	unsigned long idx;
	unsigned int step, shift;

	shift = mmu_psize_defs[mmu_linear_psize].shift;
	step = 1 << shift;

	start = ALIGN_DOWN(start, step);
	end = ALIGN(end, step); // aligns up

	if (start >= end)
		return false;

	pr_debug("Changing page protection on range 0x%lx-0x%lx, to 0x%lx, step 0x%x\n",
		 start, end, newpp, step);

	for (idx = start; idx < end; idx += step)
		/* Not sure if we can do much with the return value */
		mmu_hash_ops.hpte_updateboltedpp(newpp, idx, mmu_linear_psize,
							mmu_kernel_ssize);

	return true;
}

void hash__mark_rodata_ro(void)
{
	unsigned long start, end;

	start = (unsigned long)_stext;
	end = (unsigned long)__init_begin;

	WARN_ON(!hash__change_memory_range(start, end, PP_RXXX));
}

void hash__mark_initmem_nx(void)
{
	unsigned long start, end, pp;

	start = (unsigned long)__init_begin;
	end = (unsigned long)__init_end;

	pp = htab_convert_pte_flags(pgprot_val(PAGE_KERNEL));

	WARN_ON(!hash__change_memory_range(start, end, pp));
}
#endif
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
eee24b5a AK	2	/*
	3	* Copyright 2005, Paul Mackerras, IBM Corporation.
	4	* Copyright 2009, Benjamin Herrenschmidt, IBM Corporation.
	5	* Copyright 2015-2016, Aneesh Kumar K.V, IBM Corporation.
eee24b5a AK	6	*/
	7
	8	#include <linux/sched.h>
589ee628	9	#include <linux/mm_types.h>
cd65d697	10	#include <linux/mm.h>
589ee628	11
eee24b5a	12	#include <asm/pgalloc.h>
cd65d697 BS	13	#include <asm/sections.h>
cd65d697 BS	14	#include <asm/mmu.h>
eee24b5a AK	15	#include <asm/tlb.h>
eee24b5a AK	16
9d9f2ccc	17	#include <mm/mmu_decl.h>
eee24b5a	18
6a1ea362 AK	19	#define CREATE_TRACE_POINTS
	20	#include <trace/events/thp.h>
	21
c2b4d8b7 AK	22	#if H_PGTABLE_RANGE > (USER_VSID_RANGE * (TASK_SIZE_USER64 / TASK_CONTEXT_SIZE))
	23	#warning Limited user VSID range means pagetable space is wasted
	24	#endif
	25
eee24b5a	26	#ifdef CONFIG_SPARSEMEM_VMEMMAP
b0f36c10 AK	27	/*
	28	* vmemmap is the starting address of the virtual address space where
	29	* struct pages are allocated for all possible PFNs present on the system
	30	* including holes and bad memory (hence sparse). These virtual struct
	31	* pages are stored in sequence in this virtual address space irrespective
	32	* of the fact whether the corresponding PFN is valid or not. This achieves
	33	* constant relationship between address of struct page and its PFN.
	34	*
	35	* During boot or memory hotplug operation when a new memory section is
	36	* added, physical memory allocation (including hash table bolting) will
	37	* be performed for the set of struct pages which are part of the memory
	38	* section. This saves memory by not allocating struct pages for PFNs
	39	* which are not valid.
	40	*
	41	* ----------------------------------------------
	42	* \| PHYSICAL ALLOCATION OF VIRTUAL STRUCT PAGES\|
	43	* ----------------------------------------------
	44	*
	45	* f000000000000000 c000000000000000
	46	* vmemmap +--------------+ +--------------+
	47	* + \| page struct \| +--------------> \| page struct \|
	48	* \| +--------------+ +--------------+
	49	* \| \| page struct \| +--------------> \| page struct \|
	50	* \| +--------------+ \| +--------------+
	51	* \| \| page struct \| + +------> \| page struct \|
	52	* \| +--------------+ \| +--------------+
	53	* \| \| page struct \| \| +--> \| page struct \|
	54	* \| +--------------+ \| \| +--------------+
	55	* \| \| page struct \| \| \|
	56	* \| +--------------+ \| \|
	57	* \| \| page struct \| \| \|
	58	* \| +--------------+ \| \|
	59	* \| \| page struct \| \| \|
	60	* \| +--------------+ \| \|
	61	* \| \| page struct \| \| \|
	62	* \| +--------------+ \| \|
	63	* \| \| page struct \| +-------+ \|
	64	* \| +--------------+ \|
	65	* \| \| page struct \| +-----------+
	66	* \| +--------------+
	67	* \| \| page struct \| No mapping
	68	* \| +--------------+
	69	* \| \| page struct \| No mapping
	70	* v +--------------+
	71	*
	72	* -----------------------------------------
	73	* \| RELATION BETWEEN STRUCT PAGES AND PFNS\|
	74	* -----------------------------------------
	75	*
	76	* vmemmap +--------------+ +---------------+
	77	* + \| page struct \| +-------------> \| PFN \|
	78	* \| +--------------+ +---------------+
	79	* \| \| page struct \| +-------------> \| PFN \|
	80	* \| +--------------+ +---------------+
	81	* \| \| page struct \| +-------------> \| PFN \|
	82	* \| +--------------+ +---------------+
	83	* \| \| page struct \| +-------------> \| PFN \|
	84	* \| +--------------+ +---------------+
	85	* \| \| \|
	86	* \| +--------------+
	87	* \| \| \|
	88	* \| +--------------+
	89	* \| \| \|
	90	* \| +--------------+ +---------------+
91	* \| \| page struct \| +-------------> \| PFN \|
92	* \| +--------------+ +---------------+
93	* \| \| \|
94	* \| +--------------+
95	* \| \| \|
96	* \| +--------------+ +---------------+
97	* \| \| page struct \| +-------------> \| PFN \|
98	* \| +--------------+ +---------------+
99	* \| \| page struct \| +-------------> \| PFN \|
100	* v +--------------+ +---------------+
101	*/
eee24b5a AK	102	/*
	103	* On hash-based CPUs, the vmemmap is bolted in the hash table.
	104	*
	105	*/
31a14fae AK	106	int __meminit hash__vmemmap_create_mapping(unsigned long start,
	107	unsigned long page_size,
	108	unsigned long phys)
eee24b5a	109	{
e0909392 AK	110	int rc;
	111
	112	if ((start + page_size) >= H_VMEMMAP_END) {
f341d897	113	pr_warn("Outside the supported range\n");
e0909392 AK	114	return -1;
	115	}
	116
	117	rc = htab_bolt_mapping(start, start + page_size, phys,
	118	pgprot_val(PAGE_KERNEL),
	119	mmu_vmemmap_psize, mmu_kernel_ssize);
eee24b5a AK	120	if (rc < 0) {
	121	int rc2 = htab_remove_mapping(start, start + page_size,
	122	mmu_vmemmap_psize,
	123	mmu_kernel_ssize);
	124	BUG_ON(rc2 && (rc2 != -ENOENT));
	125	}
	126	return rc;
	127	}
	128
	129	#ifdef CONFIG_MEMORY_HOTPLUG
31a14fae AK	130	void hash__vmemmap_remove_mapping(unsigned long start,
31a14fae AK	131	unsigned long page_size)
eee24b5a AK	132	{
	133	int rc = htab_remove_mapping(start, start + page_size,
	134	mmu_vmemmap_psize,
	135	mmu_kernel_ssize);
	136	BUG_ON((rc < 0) && (rc != -ENOENT));
	137	WARN_ON(rc == -ENOENT);
	138	}
	139	#endif
	140	#endif /* CONFIG_SPARSEMEM_VMEMMAP */
	141
	142	/*
	143	* map_kernel_page currently only called by __ioremap
	144	* map_kernel_page adds an entry to the ioremap page table
	145	* and adds an entry to the HPT, possibly bolting it
	146	*/
c766ee72	147	int hash__map_kernel_page(unsigned long ea, unsigned long pa, pgprot_t prot)
eee24b5a AK	148	{
eee24b5a AK	149	pgd_t *pgdp;
2fb47060	150	p4d_t *p4dp;
eee24b5a AK	151	pud_t *pudp;
	152	pmd_t *pmdp;
	153	pte_t *ptep;
	154
dd1842a2	155	BUILD_BUG_ON(TASK_SIZE_USER64 > H_PGTABLE_RANGE);
eee24b5a AK	156	if (slab_is_available()) {
eee24b5a AK	157	pgdp = pgd_offset_k(ea);
2fb47060 MR	158	p4dp = p4d_offset(pgdp, ea);
2fb47060 MR	159	pudp = pud_alloc(&init_mm, p4dp, ea);
eee24b5a AK	160	if (!pudp)
	161	return -ENOMEM;
	162	pmdp = pmd_alloc(&init_mm, pudp, ea);
	163	if (!pmdp)
	164	return -ENOMEM;
	165	ptep = pte_alloc_kernel(pmdp, ea);
	166	if (!ptep)
	167	return -ENOMEM;
c766ee72	168	set_pte_at(&init_mm, ea, ptep, pfn_pte(pa >> PAGE_SHIFT, prot));
eee24b5a AK	169	} else {
	170	/*
	171	* If the mm subsystem is not fully up, we cannot create a
	172	* linux page table entry for this mapping. Simply bolt an
	173	* entry in the hardware page table.
	174	*
	175	*/
c766ee72	176	if (htab_bolt_mapping(ea, ea + PAGE_SIZE, pa, pgprot_val(prot),
eee24b5a AK	177	mmu_io_psize, mmu_kernel_ssize)) {
	178	printk(KERN_ERR "Failed to do bolted mapping IO "
	179	"memory at %016lx !\n", pa);
	180	return -ENOMEM;
	181	}
	182	}
	183
	184	smp_wmb();
	185	return 0;
	186	}
6a1ea362 AK	187
	188	#ifdef CONFIG_TRANSPARENT_HUGEPAGE
	189
3df33f12 AK	190	unsigned long hash__pmd_hugepage_update(struct mm_struct *mm, unsigned long addr,
	191	pmd_t *pmdp, unsigned long clr,
	192	unsigned long set)
6a1ea362 AK	193	{
	194	__be64 old_be, tmp;
	195	unsigned long old;
	196
	197	#ifdef CONFIG_DEBUG_VM
ebd31197	198	WARN_ON(!hash__pmd_trans_huge(pmdp) && !pmd_devmap(pmdp));
af60a4cf	199	assert_spin_locked(pmd_lockptr(mm, pmdp));
6a1ea362 AK	200	#endif
	201
	202	__asm__ __volatile__(
	203	"1: ldarx %0,0,%3\n\
	204	and. %1,%0,%6\n\
	205	bne- 1b \n\
	206	andc %1,%0,%4 \n\
	207	or %1,%1,%7\n\
	208	stdcx. %1,0,%3 \n\
	209	bne- 1b"
	210	: "=&r" (old_be), "=&r" (tmp), "=m" (*pmdp)
	211	: "r" (pmdp), "r" (cpu_to_be64(clr)), "m" (*pmdp),
	212	"r" (cpu_to_be64(H_PAGE_BUSY)), "r" (cpu_to_be64(set))
	213	: "cc" );
	214
	215	old = be64_to_cpu(old_be);
	216
	217	trace_hugepage_update(addr, old, clr, set);
	218	if (old & H_PAGE_HASHPTE)
	219	hpte_do_hugepage_flush(mm, addr, pmdp, old);
	220	return old;
	221	}
	222
3df33f12 AK	223	pmd_t hash__pmdp_collapse_flush(struct vm_area_struct *vma, unsigned long address,
3df33f12 AK	224	pmd_t *pmdp)
6a1ea362 AK	225	{
	226	pmd_t pmd;
	227
	228	VM_BUG_ON(address & ~HPAGE_PMD_MASK);
	229	VM_BUG_ON(pmd_trans_huge(*pmdp));
ebd31197	230	VM_BUG_ON(pmd_devmap(*pmdp));
6a1ea362 AK	231
	232	pmd = *pmdp;
	233	pmd_clear(pmdp);
	234	/*
	235	* Wait for all pending hash_page to finish. This is needed
	236	* in case of subpage collapse. When we collapse normal pages
	237	* to hugepage, we first clear the pmd, then invalidate all
	238	* the PTE entries. The assumption here is that any low level
	239	* page fault will see a none pmd and take the slow path that
c1e8d7c6	240	* will wait on mmap_lock. But we could very well be in a
6a1ea362 AK	241	* hash_page with local ptep pointer value. Such a hash page
	242	* can result in adding new HPTE entries for normal subpages.
	243	* That means we could be modifying the page content as we
	244	* copy them to a huge page. So wait for parallel hash_page
	245	* to finish before invalidating HPTE entries. We can do this
	246	* by sending an IPI to all the cpus and executing a dummy
	247	* function there.
	248	*/
fa4531f7	249	serialize_against_pte_lookup(vma->vm_mm);
6a1ea362 AK	250	/*
	251	* Now invalidate the hpte entries in the range
	252	* covered by pmd. This make sure we take a
	253	* fault and will find the pmd as none, which will
c1e8d7c6	254	* result in a major fault which takes mmap_lock and
6a1ea362 AK	255	* hence wait for collapse to complete. Without this
	256	* the __collapse_huge_page_copy can result in copying
	257	* the old content.
	258	*/
	259	flush_tlb_pmd_range(vma->vm_mm, &pmd, address);
	260	return pmd;
	261	}
	262
6a1ea362 AK	263	/*
	264	* We want to put the pgtable in pmd and use pgtable for tracking
	265	* the base page size hptes
	266	*/
3df33f12 AK	267	void hash__pgtable_trans_huge_deposit(struct mm_struct mm, pmd_t pmdp,
3df33f12 AK	268	pgtable_t pgtable)
6a1ea362 AK	269	{
6a1ea362 AK	270	pgtable_t *pgtable_slot;
af60a4cf AK	271
af60a4cf AK	272	assert_spin_locked(pmd_lockptr(mm, pmdp));
6a1ea362 AK	273	/*
	274	* we store the pgtable in the second half of PMD
	275	*/
	276	pgtable_slot = (pgtable_t *)pmdp + PTRS_PER_PMD;
	277	*pgtable_slot = pgtable;
	278	/*
	279	* expose the deposited pgtable to other cpus.
	280	* before we set the hugepage PTE at pmd level
	281	* hash fault code looks at the deposted pgtable
	282	* to store hash index values.
	283	*/
	284	smp_wmb();
	285	}
	286
3df33f12	287	pgtable_t hash__pgtable_trans_huge_withdraw(struct mm_struct mm, pmd_t pmdp)
6a1ea362 AK	288	{
	289	pgtable_t pgtable;
	290	pgtable_t *pgtable_slot;
	291
af60a4cf AK	292	assert_spin_locked(pmd_lockptr(mm, pmdp));
af60a4cf AK	293
6a1ea362 AK	294	pgtable_slot = (pgtable_t *)pmdp + PTRS_PER_PMD;
	295	pgtable = *pgtable_slot;
	296	/*
	297	* Once we withdraw, mark the entry NULL.
	298	*/
	299	*pgtable_slot = NULL;
	300	/*
	301	* We store HPTE information in the deposited PTE fragment.
	302	* zero out the content on withdraw.
	303	*/
	304	memset(pgtable, 0, PTE_FRAG_SIZE);
	305	return pgtable;
	306	}
	307
6a1ea362 AK	308	/*
	309	* A linux hugepage PMD was changed and the corresponding hash table entries
	310	* neesd to be flushed.
	311	*/
	312	void hpte_do_hugepage_flush(struct mm_struct *mm, unsigned long addr,
	313	pmd_t *pmdp, unsigned long old_pmd)
	314	{
	315	int ssize;
	316	unsigned int psize;
	317	unsigned long vsid;
	318	unsigned long flags = 0;
6a1ea362 AK	319
	320	/* get the base page size,vsid and segment size */
	321	#ifdef CONFIG_DEBUG_VM
	322	psize = get_slice_psize(mm, addr);
	323	BUG_ON(psize == MMU_PAGE_16M);
	324	#endif
	325	if (old_pmd & H_PAGE_COMBO)
	326	psize = MMU_PAGE_4K;
	327	else
	328	psize = MMU_PAGE_64K;
	329
	330	if (!is_kernel_addr(addr)) {
	331	ssize = user_segment_size(addr);
f384796c	332	vsid = get_user_vsid(&mm->context, addr, ssize);
6a1ea362 AK	333	WARN_ON(vsid == 0);
	334	} else {
	335	vsid = get_kernel_vsid(addr, mmu_kernel_ssize);
	336	ssize = mmu_kernel_ssize;
	337	}
	338
b426e4bd	339	if (mm_is_thread_local(mm))
6a1ea362 AK	340	flags \|= HPTE_LOCAL_UPDATE;
	341
	342	return flush_hash_hugepage(vsid, addr, pmdp, psize, ssize, flags);
	343	}
	344
3df33f12 AK	345	pmd_t hash__pmdp_huge_get_and_clear(struct mm_struct *mm,
3df33f12 AK	346	unsigned long addr, pmd_t *pmdp)
6a1ea362 AK	347	{
	348	pmd_t old_pmd;
	349	pgtable_t pgtable;
	350	unsigned long old;
	351	pgtable_t *pgtable_slot;
	352
	353	old = pmd_hugepage_update(mm, addr, pmdp, ~0UL, 0);
	354	old_pmd = __pmd(old);
	355	/*
	356	* We have pmd == none and we are holding page_table_lock.
	357	* So we can safely go and clear the pgtable hash
	358	* index info.
	359	*/
	360	pgtable_slot = (pgtable_t *)pmdp + PTRS_PER_PMD;
	361	pgtable = *pgtable_slot;
	362	/*
	363	* Let's zero out old valid and hash index details
	364	* hash fault look at them.
	365	*/
	366	memset(pgtable, 0, PTE_FRAG_SIZE);
6a1ea362 AK	367	return old_pmd;
	368	}
	369
3df33f12	370	int hash__has_transparent_hugepage(void)
6a1ea362 AK	371	{
	372
	373	if (!mmu_has_feature(MMU_FTR_16M_PAGE))
	374	return 0;
	375	/*
	376	* We support THP only if PMD_SIZE is 16MB.
	377	*/
	378	if (mmu_psize_defs[MMU_PAGE_16M].shift != PMD_SHIFT)
	379	return 0;
	380	/*
	381	* We need to make sure that we support 16MB hugepage in a segement
	382	* with base page size 64K or 4K. We only enable THP with a PAGE_SIZE
	383	* of 64K.
	384	*/
	385	/*
	386	* If we have 64K HPTE, we will be using that by default
	387	*/
	388	if (mmu_psize_defs[MMU_PAGE_64K].shift &&
	389	(mmu_psize_defs[MMU_PAGE_64K].penc[MMU_PAGE_16M] == -1))
	390	return 0;
	391	/*
	392	* Ok we only have 4K HPTE
	393	*/
	394	if (mmu_psize_defs[MMU_PAGE_4K].penc[MMU_PAGE_16M] == -1)
	395	return 0;
	396
	397	return 1;
	398	}
a6f197f8 AK	399	EXPORT_SYMBOL_GPL(hash__has_transparent_hugepage);
a6f197f8 AK	400
6a1ea362	401	#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
cd65d697 BS	402
cd65d697 BS	403	#ifdef CONFIG_STRICT_KERNEL_RWX
fa7f9189 ME	404	static bool hash__change_memory_range(unsigned long start, unsigned long end,
fa7f9189 ME	405	unsigned long newpp)
cd65d697	406	{
cd65d697 BS	407	unsigned long idx;
cd65d697 BS	408	unsigned int step, shift;
cd65d697 BS	409
	410	shift = mmu_psize_defs[mmu_linear_psize].shift;
	411	step = 1 << shift;
	412
fa7f9189 ME	413	start = ALIGN_DOWN(start, step);
fa7f9189 ME	414	end = ALIGN(end, step); // aligns up
cd65d697	415
fa7f9189 ME	416	if (start >= end)
fa7f9189 ME	417	return false;
cd65d697	418
fa7f9189 ME	419	pr_debug("Changing page protection on range 0x%lx-0x%lx, to 0x%lx, step 0x%x\n",
fa7f9189 ME	420	start, end, newpp, step);
cd65d697 BS	421
	422	for (idx = start; idx < end; idx += step)
	423	/* Not sure if we can do much with the return value */
	424	mmu_hash_ops.hpte_updateboltedpp(newpp, idx, mmu_linear_psize,
	425	mmu_kernel_ssize);
	426
fa7f9189 ME	427	return true;
	428	}
	429
	430	void hash__mark_rodata_ro(void)
	431	{
	432	unsigned long start, end;
	433
	434	start = (unsigned long)_stext;
	435	end = (unsigned long)__init_begin;
	436
	437	WARN_ON(!hash__change_memory_range(start, end, PP_RXXX));
cd65d697	438	}
029d9252 ME	439
	440	void hash__mark_initmem_nx(void)
	441	{
	442	unsigned long start, end, pp;
	443
	444	start = (unsigned long)__init_begin;
	445	end = (unsigned long)__init_end;
	446
	447	pp = htab_convert_pte_flags(pgprot_val(PAGE_KERNEL));
	448
	449	WARN_ON(!hash__change_memory_range(start, end, pp));
	450	}
cd65d697	451	#endif