[people/arne_f/kernel.git] / arch / powerpc / platforms / ps3 / spu.c

/*
 *  PS3 Platform spu routines.
 *
 *  Copyright (C) 2006 Sony Computer Entertainment Inc.
 *  Copyright 2006 Sony Corp.
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; version 2 of the License.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/mmzone.h>
#include <linux/io.h>
#include <linux/mm.h>

#include <asm/spu.h>
#include <asm/spu_priv1.h>
#include <asm/lv1call.h>
#include <asm/ps3.h>

#include "../cell/spufs/spufs.h"
#include "platform.h"

/* spu_management_ops */

/**
 * enum spe_type - Type of spe to create.
 * @spe_type_logical: Standard logical spe.
 *
 * For use with lv1_construct_logical_spe().  The current HV does not support
 * any types other than those listed.
 */

enum spe_type {
	SPE_TYPE_LOGICAL = 0,
};

/**
 * struct spe_shadow - logical spe shadow register area.
 *
 * Read-only shadow of spe registers.
 */

struct spe_shadow {
	u8 padding_0140[0x0140];
	u64 int_status_class0_RW;       /* 0x0140 */
	u64 int_status_class1_RW;       /* 0x0148 */
	u64 int_status_class2_RW;       /* 0x0150 */
	u8 padding_0158[0x0610-0x0158];
	u64 mfc_dsisr_RW;               /* 0x0610 */
	u8 padding_0618[0x0620-0x0618];
	u64 mfc_dar_RW;                 /* 0x0620 */
	u8 padding_0628[0x0800-0x0628];
	u64 mfc_dsipr_R;                /* 0x0800 */
	u8 padding_0808[0x0810-0x0808];
	u64 mfc_lscrr_R;                /* 0x0810 */
	u8 padding_0818[0x0c00-0x0818];
	u64 mfc_cer_R;                  /* 0x0c00 */
	u8 padding_0c08[0x0f00-0x0c08];
	u64 spe_execution_status;       /* 0x0f00 */
	u8 padding_0f08[0x1000-0x0f08];
};

/**
 * enum spe_ex_state - Logical spe execution state.
 * @spe_ex_state_unexecutable: Uninitialized.
 * @spe_ex_state_executable: Enabled, not ready.
 * @spe_ex_state_executed: Ready for use.
 *
 * The execution state (status) of the logical spe as reported in
 * struct spe_shadow:spe_execution_status.
 */

enum spe_ex_state {
	SPE_EX_STATE_UNEXECUTABLE = 0,
	SPE_EX_STATE_EXECUTABLE = 2,
	SPE_EX_STATE_EXECUTED = 3,
};

/**
 * struct priv1_cache - Cached values of priv1 registers.
 * @masks[]: Array of cached spe interrupt masks, indexed by class.
 * @sr1: Cached mfc_sr1 register.
 * @tclass_id: Cached mfc_tclass_id register.
 */

struct priv1_cache {
	u64 masks[3];
	u64 sr1;
	u64 tclass_id;
};

/**
 * struct spu_pdata - Platform state variables.
 * @spe_id: HV spe id returned by lv1_construct_logical_spe().
 * @resource_id: HV spe resource id returned by
 * 	ps3_repository_read_spe_resource_id().
 * @priv2_addr: lpar address of spe priv2 area returned by
 * 	lv1_construct_logical_spe().
 * @shadow_addr: lpar address of spe register shadow area returned by
 * 	lv1_construct_logical_spe().
 * @shadow: Virtual (ioremap) address of spe register shadow area.
 * @cache: Cached values of priv1 registers.
 */

struct spu_pdata {
	u64 spe_id;
	u64 resource_id;
	u64 priv2_addr;
	u64 shadow_addr;
	struct spe_shadow __iomem *shadow;
	struct priv1_cache cache;
};

static struct spu_pdata *spu_pdata(struct spu *spu)
{
	return spu->pdata;
}

#define dump_areas(_a, _b, _c, _d, _e) \
	_dump_areas(_a, _b, _c, _d, _e, __func__, __LINE__)
static void _dump_areas(unsigned int spe_id, unsigned long priv2,
	unsigned long problem, unsigned long ls, unsigned long shadow,
	const char* func, int line)
{
	pr_debug("%s:%d: spe_id:  %xh (%u)\n", func, line, spe_id, spe_id);
	pr_debug("%s:%d: priv2:   %lxh\n", func, line, priv2);
	pr_debug("%s:%d: problem: %lxh\n", func, line, problem);
	pr_debug("%s:%d: ls:      %lxh\n", func, line, ls);
	pr_debug("%s:%d: shadow:  %lxh\n", func, line, shadow);
}

inline u64 ps3_get_spe_id(void *arg)
{
	return spu_pdata(arg)->spe_id;
}
EXPORT_SYMBOL_GPL(ps3_get_spe_id);

static unsigned long get_vas_id(void)
{
	u64 id;

	lv1_get_logical_ppe_id(&id);
	lv1_get_virtual_address_space_id_of_ppe(id, &id);

	return id;
}

static int __init construct_spu(struct spu *spu)
{
	int result;
	u64 unused;
	u64 problem_phys;
	u64 local_store_phys;

	result = lv1_construct_logical_spe(PAGE_SHIFT, PAGE_SHIFT, PAGE_SHIFT,
		PAGE_SHIFT, PAGE_SHIFT, get_vas_id(), SPE_TYPE_LOGICAL,
		&spu_pdata(spu)->priv2_addr, &problem_phys,
		&local_store_phys, &unused,
		&spu_pdata(spu)->shadow_addr,
		&spu_pdata(spu)->spe_id);
	spu->problem_phys = problem_phys;
	spu->local_store_phys = local_store_phys;

	if (result) {
		pr_debug("%s:%d: lv1_construct_logical_spe failed: %s\n",
			__func__, __LINE__, ps3_result(result));
		return result;
	}

	return result;
}

static void spu_unmap(struct spu *spu)
{
	iounmap(spu->priv2);
	iounmap(spu->problem);
	iounmap((__force u8 __iomem *)spu->local_store);
	iounmap(spu_pdata(spu)->shadow);
}

/**
 * setup_areas - Map the spu regions into the address space.
 *
 * The current HV requires the spu shadow regs to be mapped with the
 * PTE page protection bits set as read-only (PP=3).  This implementation
 * uses the low level __ioremap() to bypass the page protection settings
 * inforced by ioremap_flags() to get the needed PTE bits set for the
 * shadow regs.
 */

static int __init setup_areas(struct spu *spu)
{
	struct table {char* name; unsigned long addr; unsigned long size;};
	static const unsigned long shadow_flags = _PAGE_NO_CACHE | 3;

	spu_pdata(spu)->shadow = __ioremap(spu_pdata(spu)->shadow_addr,
					   sizeof(struct spe_shadow),
					   shadow_flags);
	if (!spu_pdata(spu)->shadow) {
		pr_debug("%s:%d: ioremap shadow failed\n", __func__, __LINE__);
		goto fail_ioremap;
	}

	spu->local_store = (__force void *)ioremap_flags(spu->local_store_phys,
		LS_SIZE, _PAGE_NO_CACHE);

	if (!spu->local_store) {
		pr_debug("%s:%d: ioremap local_store failed\n",
			__func__, __LINE__);
		goto fail_ioremap;
	}

	spu->problem = ioremap(spu->problem_phys,
		sizeof(struct spu_problem));

	if (!spu->problem) {
		pr_debug("%s:%d: ioremap problem failed\n", __func__, __LINE__);
		goto fail_ioremap;
	}

	spu->priv2 = ioremap(spu_pdata(spu)->priv2_addr,
		sizeof(struct spu_priv2));

	if (!spu->priv2) {
		pr_debug("%s:%d: ioremap priv2 failed\n", __func__, __LINE__);
		goto fail_ioremap;
	}

	dump_areas(spu_pdata(spu)->spe_id, spu_pdata(spu)->priv2_addr,
		spu->problem_phys, spu->local_store_phys,
		spu_pdata(spu)->shadow_addr);
	dump_areas(spu_pdata(spu)->spe_id, (unsigned long)spu->priv2,
		(unsigned long)spu->problem, (unsigned long)spu->local_store,
		(unsigned long)spu_pdata(spu)->shadow);

	return 0;

fail_ioremap:
	spu_unmap(spu);

	return -ENOMEM;
}

static int __init setup_interrupts(struct spu *spu)
{
	int result;

	result = ps3_spe_irq_setup(PS3_BINDING_CPU_ANY, spu_pdata(spu)->spe_id,
		0, &spu->irqs[0]);

	if (result)
		goto fail_alloc_0;

	result = ps3_spe_irq_setup(PS3_BINDING_CPU_ANY, spu_pdata(spu)->spe_id,
		1, &spu->irqs[1]);

	if (result)
		goto fail_alloc_1;

	result = ps3_spe_irq_setup(PS3_BINDING_CPU_ANY, spu_pdata(spu)->spe_id,
		2, &spu->irqs[2]);

	if (result)
		goto fail_alloc_2;

	return result;

fail_alloc_2:
	ps3_spe_irq_destroy(spu->irqs[1]);
fail_alloc_1:
	ps3_spe_irq_destroy(spu->irqs[0]);
fail_alloc_0:
	spu->irqs[0] = spu->irqs[1] = spu->irqs[2] = NO_IRQ;
	return result;
}

static int __init enable_spu(struct spu *spu)
{
	int result;

	result = lv1_enable_logical_spe(spu_pdata(spu)->spe_id,
		spu_pdata(spu)->resource_id);

	if (result) {
		pr_debug("%s:%d: lv1_enable_logical_spe failed: %s\n",
			__func__, __LINE__, ps3_result(result));
		goto fail_enable;
	}

	result = setup_areas(spu);

	if (result)
		goto fail_areas;

	result = setup_interrupts(spu);

	if (result)
		goto fail_interrupts;

	return 0;

fail_interrupts:
	spu_unmap(spu);
fail_areas:
	lv1_disable_logical_spe(spu_pdata(spu)->spe_id, 0);
fail_enable:
	return result;
}

static int ps3_destroy_spu(struct spu *spu)
{
	int result;

	pr_debug("%s:%d spu_%d\n", __func__, __LINE__, spu->number);

	result = lv1_disable_logical_spe(spu_pdata(spu)->spe_id, 0);
	BUG_ON(result);

	ps3_spe_irq_destroy(spu->irqs[2]);
	ps3_spe_irq_destroy(spu->irqs[1]);
	ps3_spe_irq_destroy(spu->irqs[0]);

	spu->irqs[0] = spu->irqs[1] = spu->irqs[2] = NO_IRQ;

	spu_unmap(spu);

	result = lv1_destruct_logical_spe(spu_pdata(spu)->spe_id);
	BUG_ON(result);

	kfree(spu->pdata);
	spu->pdata = NULL;

	return 0;
}

static int __init ps3_create_spu(struct spu *spu, void *data)
{
	int result;

	pr_debug("%s:%d spu_%d\n", __func__, __LINE__, spu->number);

	spu->pdata = kzalloc(sizeof(struct spu_pdata),
		GFP_KERNEL);

	if (!spu->pdata) {
		result = -ENOMEM;
		goto fail_malloc;
	}

	spu_pdata(spu)->resource_id = (unsigned long)data;

	/* Init cached reg values to HV defaults. */

	spu_pdata(spu)->cache.sr1 = 0x33;

	result = construct_spu(spu);

	if (result)
		goto fail_construct;

	/* For now, just go ahead and enable it. */

	result = enable_spu(spu);

	if (result)
		goto fail_enable;

	/* Make sure the spu is in SPE_EX_STATE_EXECUTED. */

	/* need something better here!!! */
	while (in_be64(&spu_pdata(spu)->shadow->spe_execution_status)
		!= SPE_EX_STATE_EXECUTED)
		(void)0;

	return result;

fail_enable:
fail_construct:
	ps3_destroy_spu(spu);
fail_malloc:
	return result;
}

static int __init ps3_enumerate_spus(int (*fn)(void *data))
{
	int result;
	unsigned int num_resource_id;
	unsigned int i;

	result = ps3_repository_read_num_spu_resource_id(&num_resource_id);

	pr_debug("%s:%d: num_resource_id %u\n", __func__, __LINE__,
		num_resource_id);

	/*
	 * For now, just create logical spus equal to the number
	 * of physical spus reserved for the partition.
	 */

	for (i = 0; i < num_resource_id; i++) {
		enum ps3_spu_resource_type resource_type;
		unsigned int resource_id;

		result = ps3_repository_read_spu_resource_id(i,
			&resource_type, &resource_id);

		if (result)
			break;

		if (resource_type == PS3_SPU_RESOURCE_TYPE_EXCLUSIVE) {
			result = fn((void*)(unsigned long)resource_id);

			if (result)
				break;
		}
	}

	if (result) {
		printk(KERN_WARNING "%s:%d: Error initializing spus\n",
			__func__, __LINE__);
		return result;
	}

	return num_resource_id;
}

static int ps3_init_affinity(void)
{
	return 0;
}

/**
 * ps3_enable_spu - Enable SPU run control.
 *
 * An outstanding enhancement for the PS3 would be to add a guard to check
 * for incorrect access to the spu problem state when the spu context is
 * disabled.  This check could be implemented with a flag added to the spu
 * context that would inhibit mapping problem state pages, and a routine
 * to unmap spu problem state pages.  When the spu is enabled with
 * ps3_enable_spu() the flag would be set allowing pages to be mapped,
 * and when the spu is disabled with ps3_disable_spu() the flag would be
 * cleared and the mapped problem state pages would be unmapped.
 */

static void ps3_enable_spu(struct spu_context *ctx)
{
}

static void ps3_disable_spu(struct spu_context *ctx)
{
	ctx->ops->runcntl_stop(ctx);
}

const struct spu_management_ops spu_management_ps3_ops = {
	.enumerate_spus = ps3_enumerate_spus,
	.create_spu = ps3_create_spu,
	.destroy_spu = ps3_destroy_spu,
	.enable_spu = ps3_enable_spu,
	.disable_spu = ps3_disable_spu,
	.init_affinity = ps3_init_affinity,
};

/* spu_priv1_ops */

static void int_mask_and(struct spu *spu, int class, u64 mask)
{
	u64 old_mask;

	/* are these serialized by caller??? */
	old_mask = spu_int_mask_get(spu, class);
	spu_int_mask_set(spu, class, old_mask & mask);
}

static void int_mask_or(struct spu *spu, int class, u64 mask)
{
	u64 old_mask;

	old_mask = spu_int_mask_get(spu, class);
	spu_int_mask_set(spu, class, old_mask | mask);
}

static void int_mask_set(struct spu *spu, int class, u64 mask)
{
	spu_pdata(spu)->cache.masks[class] = mask;
	lv1_set_spe_interrupt_mask(spu_pdata(spu)->spe_id, class,
		spu_pdata(spu)->cache.masks[class]);
}

static u64 int_mask_get(struct spu *spu, int class)
{
	return spu_pdata(spu)->cache.masks[class];
}

static void int_stat_clear(struct spu *spu, int class, u64 stat)
{
	/* Note that MFC_DSISR will be cleared when class1[MF] is set. */

	lv1_clear_spe_interrupt_status(spu_pdata(spu)->spe_id, class,
		stat, 0);
}

static u64 int_stat_get(struct spu *spu, int class)
{
	u64 stat;

	lv1_get_spe_interrupt_status(spu_pdata(spu)->spe_id, class, &stat);
	return stat;
}

static void cpu_affinity_set(struct spu *spu, int cpu)
{
	/* No support. */
}

static u64 mfc_dar_get(struct spu *spu)
{
	return in_be64(&spu_pdata(spu)->shadow->mfc_dar_RW);
}

static void mfc_dsisr_set(struct spu *spu, u64 dsisr)
{
	/* Nothing to do, cleared in int_stat_clear(). */
}

static u64 mfc_dsisr_get(struct spu *spu)
{
	return in_be64(&spu_pdata(spu)->shadow->mfc_dsisr_RW);
}

static void mfc_sdr_setup(struct spu *spu)
{
	/* Nothing to do. */
}

static void mfc_sr1_set(struct spu *spu, u64 sr1)
{
	/* Check bits allowed by HV. */

	static const u64 allowed = ~(MFC_STATE1_LOCAL_STORAGE_DECODE_MASK
		| MFC_STATE1_PROBLEM_STATE_MASK);

	BUG_ON((sr1 & allowed) != (spu_pdata(spu)->cache.sr1 & allowed));

	spu_pdata(spu)->cache.sr1 = sr1;
	lv1_set_spe_privilege_state_area_1_register(
		spu_pdata(spu)->spe_id,
		offsetof(struct spu_priv1, mfc_sr1_RW),
		spu_pdata(spu)->cache.sr1);
}

static u64 mfc_sr1_get(struct spu *spu)
{
	return spu_pdata(spu)->cache.sr1;
}

static void mfc_tclass_id_set(struct spu *spu, u64 tclass_id)
{
	spu_pdata(spu)->cache.tclass_id = tclass_id;
	lv1_set_spe_privilege_state_area_1_register(
		spu_pdata(spu)->spe_id,
		offsetof(struct spu_priv1, mfc_tclass_id_RW),
		spu_pdata(spu)->cache.tclass_id);
}

static u64 mfc_tclass_id_get(struct spu *spu)
{
	return spu_pdata(spu)->cache.tclass_id;
}

static void tlb_invalidate(struct spu *spu)
{
	/* Nothing to do. */
}

static void resource_allocation_groupID_set(struct spu *spu, u64 id)
{
	/* No support. */
}

static u64 resource_allocation_groupID_get(struct spu *spu)
{
	return 0; /* No support. */
}

static void resource_allocation_enable_set(struct spu *spu, u64 enable)
{
	/* No support. */
}

static u64 resource_allocation_enable_get(struct spu *spu)
{
	return 0; /* No support. */
}

const struct spu_priv1_ops spu_priv1_ps3_ops = {
	.int_mask_and = int_mask_and,
	.int_mask_or = int_mask_or,
	.int_mask_set = int_mask_set,
	.int_mask_get = int_mask_get,
	.int_stat_clear = int_stat_clear,
	.int_stat_get = int_stat_get,
	.cpu_affinity_set = cpu_affinity_set,
	.mfc_dar_get = mfc_dar_get,
	.mfc_dsisr_set = mfc_dsisr_set,
	.mfc_dsisr_get = mfc_dsisr_get,
	.mfc_sdr_setup = mfc_sdr_setup,
	.mfc_sr1_set = mfc_sr1_set,
	.mfc_sr1_get = mfc_sr1_get,
	.mfc_tclass_id_set = mfc_tclass_id_set,
	.mfc_tclass_id_get = mfc_tclass_id_get,
	.tlb_invalidate = tlb_invalidate,
	.resource_allocation_groupID_set = resource_allocation_groupID_set,
	.resource_allocation_groupID_get = resource_allocation_groupID_get,
	.resource_allocation_enable_set = resource_allocation_enable_set,
	.resource_allocation_enable_get = resource_allocation_enable_get,
};

void ps3_spu_set_platform(void)
{
	spu_priv1_ops = &spu_priv1_ps3_ops;
	spu_management_ops = &spu_management_ps3_ops;
}
Commit	Line	Data
de91a534 GL	1	/*
	2	* PS3 Platform spu routines.
	3	*
	4	* Copyright (C) 2006 Sony Computer Entertainment Inc.
	5	* Copyright 2006 Sony Corp.
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; version 2 of the License.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20
	21	#include <linux/kernel.h>
	22	#include <linux/init.h>
5a0e3ad6	23	#include <linux/slab.h>
de91a534 GL	24	#include <linux/mmzone.h>
	25	#include <linux/io.h>
	26	#include <linux/mm.h>
	27
	28	#include <asm/spu.h>
	29	#include <asm/spu_priv1.h>
de91a534	30	#include <asm/lv1call.h>
23afcb4e	31	#include <asm/ps3.h>
de91a534	32
c25620d7	33	#include "../cell/spufs/spufs.h"
2a08ea69 GL	34	#include "platform.h"
2a08ea69 GL	35
de91a534 GL	36	/* spu_management_ops */
	37
	38	/**
	39	* enum spe_type - Type of spe to create.
	40	* @spe_type_logical: Standard logical spe.
	41	*
	42	* For use with lv1_construct_logical_spe(). The current HV does not support
	43	* any types other than those listed.
	44	*/
	45
	46	enum spe_type {
	47	SPE_TYPE_LOGICAL = 0,
	48	};
	49
	50	/**
	51	* struct spe_shadow - logical spe shadow register area.
	52	*
	53	* Read-only shadow of spe registers.
	54	*/
	55
	56	struct spe_shadow {
a8229a9e	57	u8 padding_0140[0x0140];
de91a534 GL	58	u64 int_status_class0_RW; /* 0x0140 */
	59	u64 int_status_class1_RW; /* 0x0148 */
	60	u64 int_status_class2_RW; /* 0x0150 */
	61	u8 padding_0158[0x0610-0x0158];
	62	u64 mfc_dsisr_RW; /* 0x0610 */
	63	u8 padding_0618[0x0620-0x0618];
	64	u64 mfc_dar_RW; /* 0x0620 */
	65	u8 padding_0628[0x0800-0x0628];
	66	u64 mfc_dsipr_R; /* 0x0800 */
	67	u8 padding_0808[0x0810-0x0808];
	68	u64 mfc_lscrr_R; /* 0x0810 */
	69	u8 padding_0818[0x0c00-0x0818];
	70	u64 mfc_cer_R; /* 0x0c00 */
	71	u8 padding_0c08[0x0f00-0x0c08];
	72	u64 spe_execution_status; /* 0x0f00 */
	73	u8 padding_0f08[0x1000-0x0f08];
a8229a9e	74	};
de91a534 GL	75
	76	/**
	77	* enum spe_ex_state - Logical spe execution state.
	78	* @spe_ex_state_unexecutable: Uninitialized.
	79	* @spe_ex_state_executable: Enabled, not ready.
	80	* @spe_ex_state_executed: Ready for use.
	81	*
	82	* The execution state (status) of the logical spe as reported in
	83	* struct spe_shadow:spe_execution_status.
	84	*/
	85
	86	enum spe_ex_state {
	87	SPE_EX_STATE_UNEXECUTABLE = 0,
	88	SPE_EX_STATE_EXECUTABLE = 2,
	89	SPE_EX_STATE_EXECUTED = 3,
	90	};
	91
	92	/**
	93	* struct priv1_cache - Cached values of priv1 registers.
	94	* @masks[]: Array of cached spe interrupt masks, indexed by class.
	95	* @sr1: Cached mfc_sr1 register.
	96	* @tclass_id: Cached mfc_tclass_id register.
	97	*/
	98
	99	struct priv1_cache {
	100	u64 masks[3];
	101	u64 sr1;
	102	u64 tclass_id;
	103	};
	104
	105	/**
	106	* struct spu_pdata - Platform state variables.
	107	* @spe_id: HV spe id returned by lv1_construct_logical_spe().
	108	* @resource_id: HV spe resource id returned by
	109	* ps3_repository_read_spe_resource_id().
	110	* @priv2_addr: lpar address of spe priv2 area returned by
	111	* lv1_construct_logical_spe().
	112	* @shadow_addr: lpar address of spe register shadow area returned by
	113	* lv1_construct_logical_spe().
	114	* @shadow: Virtual (ioremap) address of spe register shadow area.
	115	* @cache: Cached values of priv1 registers.
	116	*/
	117
	118	struct spu_pdata {
	119	u64 spe_id;
	120	u64 resource_id;
	121	u64 priv2_addr;
	122	u64 shadow_addr;
	123	struct spe_shadow __iomem *shadow;
	124	struct priv1_cache cache;
	125	};
	126
	127	static struct spu_pdata spu_pdata(struct spu spu)
	128	{
	129	return spu->pdata;
	130	}
	131
	132	#define dump_areas(_a, _b, _c, _d, _e) \
	133	_dump_areas(_a, _b, _c, _d, _e, __func__, __LINE__)
	134	static void _dump_areas(unsigned int spe_id, unsigned long priv2,
	135	unsigned long problem, unsigned long ls, unsigned long shadow,
	136	const char* func, int line)
	137	{
	138	pr_debug("%s:%d: spe_id: %xh (%u)\n", func, line, spe_id, spe_id);
139	pr_debug("%s:%d: priv2: %lxh\n", func, line, priv2);
140	pr_debug("%s:%d: problem: %lxh\n", func, line, problem);
141	pr_debug("%s:%d: ls: %lxh\n", func, line, ls);
142	pr_debug("%s:%d: shadow: %lxh\n", func, line, shadow);
143	}
144
23afcb4e TY	145	inline u64 ps3_get_spe_id(void *arg)
	146	{
	147	return spu_pdata(arg)->spe_id;
	148	}
	149	EXPORT_SYMBOL_GPL(ps3_get_spe_id);
	150
de91a534 GL	151	static unsigned long get_vas_id(void)
de91a534 GL	152	{
b17b3df1	153	u64 id;
de91a534 GL	154
	155	lv1_get_logical_ppe_id(&id);
	156	lv1_get_virtual_address_space_id_of_ppe(id, &id);
	157
	158	return id;
	159	}
	160
	161	static int __init construct_spu(struct spu *spu)
	162	{
	163	int result;
b17b3df1 SR	164	u64 unused;
	165	u64 problem_phys;
	166	u64 local_store_phys;
de91a534 GL	167
	168	result = lv1_construct_logical_spe(PAGE_SHIFT, PAGE_SHIFT, PAGE_SHIFT,
	169	PAGE_SHIFT, PAGE_SHIFT, get_vas_id(), SPE_TYPE_LOGICAL,
b17b3df1 SR	170	&spu_pdata(spu)->priv2_addr, &problem_phys,
b17b3df1 SR	171	&local_store_phys, &unused,
de91a534 GL	172	&spu_pdata(spu)->shadow_addr,
de91a534 GL	173	&spu_pdata(spu)->spe_id);
b17b3df1 SR	174	spu->problem_phys = problem_phys;
b17b3df1 SR	175	spu->local_store_phys = local_store_phys;
de91a534 GL	176
	177	if (result) {
	178	pr_debug("%s:%d: lv1_construct_logical_spe failed: %s\n",
	179	__func__, __LINE__, ps3_result(result));
	180	return result;
	181	}
	182
	183	return result;
	184	}
	185
de91a534 GL	186	static void spu_unmap(struct spu *spu)
	187	{
	188	iounmap(spu->priv2);
	189	iounmap(spu->problem);
	190	iounmap((__force u8 __iomem *)spu->local_store);
	191	iounmap(spu_pdata(spu)->shadow);
	192	}
	193
b4702779 MM	194	/**
	195	* setup_areas - Map the spu regions into the address space.
	196	*
	197	* The current HV requires the spu shadow regs to be mapped with the
	198	* PTE page protection bits set as read-only (PP=3). This implementation
	199	* uses the low level __ioremap() to bypass the page protection settings
	200	* inforced by ioremap_flags() to get the needed PTE bits set for the
	201	* shadow regs.
	202	*/
	203
de91a534 GL	204	static int __init setup_areas(struct spu *spu)
	205	{
	206	struct table {char* name; unsigned long addr; unsigned long size;};
b4702779	207	static const unsigned long shadow_flags = _PAGE_NO_CACHE \| 3;
de91a534	208
b4702779 MM	209	spu_pdata(spu)->shadow = __ioremap(spu_pdata(spu)->shadow_addr,
	210	sizeof(struct spe_shadow),
	211	shadow_flags);
de91a534 GL	212	if (!spu_pdata(spu)->shadow) {
	213	pr_debug("%s:%d: ioremap shadow failed\n", __func__, __LINE__);
	214	goto fail_ioremap;
	215	}
	216
53f7c545 GL	217	spu->local_store = (__force void *)ioremap_flags(spu->local_store_phys,
	218	LS_SIZE, _PAGE_NO_CACHE);
	219
de91a534 GL	220	if (!spu->local_store) {
	221	pr_debug("%s:%d: ioremap local_store failed\n",
	222	__func__, __LINE__);
	223	goto fail_ioremap;
	224	}
	225
	226	spu->problem = ioremap(spu->problem_phys,
	227	sizeof(struct spu_problem));
53f7c545	228
de91a534 GL	229	if (!spu->problem) {
	230	pr_debug("%s:%d: ioremap problem failed\n", __func__, __LINE__);
	231	goto fail_ioremap;
	232	}
	233
	234	spu->priv2 = ioremap(spu_pdata(spu)->priv2_addr,
	235	sizeof(struct spu_priv2));
53f7c545	236
de91a534 GL	237	if (!spu->priv2) {
	238	pr_debug("%s:%d: ioremap priv2 failed\n", __func__, __LINE__);
	239	goto fail_ioremap;
	240	}
	241
	242	dump_areas(spu_pdata(spu)->spe_id, spu_pdata(spu)->priv2_addr,
	243	spu->problem_phys, spu->local_store_phys,
	244	spu_pdata(spu)->shadow_addr);
	245	dump_areas(spu_pdata(spu)->spe_id, (unsigned long)spu->priv2,
	246	(unsigned long)spu->problem, (unsigned long)spu->local_store,
	247	(unsigned long)spu_pdata(spu)->shadow);
	248
	249	return 0;
	250
	251	fail_ioremap:
	252	spu_unmap(spu);
44430e0d BH	253
44430e0d BH	254	return -ENOMEM;
de91a534 GL	255	}
	256
	257	static int __init setup_interrupts(struct spu *spu)
	258	{
	259	int result;
	260
dc4f60c2	261	result = ps3_spe_irq_setup(PS3_BINDING_CPU_ANY, spu_pdata(spu)->spe_id,
861be32c	262	0, &spu->irqs[0]);
de91a534 GL	263
	264	if (result)
	265	goto fail_alloc_0;
	266
dc4f60c2	267	result = ps3_spe_irq_setup(PS3_BINDING_CPU_ANY, spu_pdata(spu)->spe_id,
861be32c	268	1, &spu->irqs[1]);
de91a534 GL	269
	270	if (result)
	271	goto fail_alloc_1;
	272
dc4f60c2	273	result = ps3_spe_irq_setup(PS3_BINDING_CPU_ANY, spu_pdata(spu)->spe_id,
861be32c	274	2, &spu->irqs[2]);
de91a534 GL	275
	276	if (result)
	277	goto fail_alloc_2;
	278
	279	return result;
	280
	281	fail_alloc_2:
dc4f60c2	282	ps3_spe_irq_destroy(spu->irqs[1]);
de91a534	283	fail_alloc_1:
dc4f60c2	284	ps3_spe_irq_destroy(spu->irqs[0]);
de91a534 GL	285	fail_alloc_0:
	286	spu->irqs[0] = spu->irqs[1] = spu->irqs[2] = NO_IRQ;
	287	return result;
	288	}
	289
	290	static int __init enable_spu(struct spu *spu)
	291	{
	292	int result;
	293
	294	result = lv1_enable_logical_spe(spu_pdata(spu)->spe_id,
	295	spu_pdata(spu)->resource_id);
	296
	297	if (result) {
	298	pr_debug("%s:%d: lv1_enable_logical_spe failed: %s\n",
	299	__func__, __LINE__, ps3_result(result));
	300	goto fail_enable;
	301	}
	302
	303	result = setup_areas(spu);
	304
	305	if (result)
	306	goto fail_areas;
	307
	308	result = setup_interrupts(spu);
	309
	310	if (result)
	311	goto fail_interrupts;
	312
	313	return 0;
	314
	315	fail_interrupts:
	316	spu_unmap(spu);
	317	fail_areas:
	318	lv1_disable_logical_spe(spu_pdata(spu)->spe_id, 0);
	319	fail_enable:
	320	return result;
	321	}
	322
	323	static int ps3_destroy_spu(struct spu *spu)
	324	{
	325	int result;
	326
	327	pr_debug("%s:%d spu_%d\n", __func__, __LINE__, spu->number);
	328
	329	result = lv1_disable_logical_spe(spu_pdata(spu)->spe_id, 0);
	330	BUG_ON(result);
	331
dc4f60c2 GL	332	ps3_spe_irq_destroy(spu->irqs[2]);
	333	ps3_spe_irq_destroy(spu->irqs[1]);
	334	ps3_spe_irq_destroy(spu->irqs[0]);
de91a534 GL	335
	336	spu->irqs[0] = spu->irqs[1] = spu->irqs[2] = NO_IRQ;
	337
	338	spu_unmap(spu);
	339
	340	result = lv1_destruct_logical_spe(spu_pdata(spu)->spe_id);
	341	BUG_ON(result);
	342
	343	kfree(spu->pdata);
	344	spu->pdata = NULL;
	345
	346	return 0;
	347	}
	348
	349	static int __init ps3_create_spu(struct spu spu, void data)
	350	{
	351	int result;
	352
	353	pr_debug("%s:%d spu_%d\n", __func__, __LINE__, spu->number);
	354
	355	spu->pdata = kzalloc(sizeof(struct spu_pdata),
	356	GFP_KERNEL);
	357
	358	if (!spu->pdata) {
	359	result = -ENOMEM;
	360	goto fail_malloc;
	361	}
	362
	363	spu_pdata(spu)->resource_id = (unsigned long)data;
	364
	365	/* Init cached reg values to HV defaults. */
	366
	367	spu_pdata(spu)->cache.sr1 = 0x33;
	368
	369	result = construct_spu(spu);
	370
	371	if (result)
	372	goto fail_construct;
	373
	374	/* For now, just go ahead and enable it. */
	375
	376	result = enable_spu(spu);
	377
	378	if (result)
	379	goto fail_enable;
	380
	381	/* Make sure the spu is in SPE_EX_STATE_EXECUTED. */
	382
	383	/* need something better here!!! */
	384	while (in_be64(&spu_pdata(spu)->shadow->spe_execution_status)
	385	!= SPE_EX_STATE_EXECUTED)
	386	(void)0;
	387
	388	return result;
	389
	390	fail_enable:
	391	fail_construct:
	392	ps3_destroy_spu(spu);
	393	fail_malloc:
	394	return result;
	395	}
	396
	397	static int __init ps3_enumerate_spus(int (fn)(void data))
	398	{
399	int result;
400	unsigned int num_resource_id;
401	unsigned int i;
402
403	result = ps3_repository_read_num_spu_resource_id(&num_resource_id);
404
405	pr_debug("%s:%d: num_resource_id %u\n", __func__, __LINE__,
406	num_resource_id);
407
408	/*
409	* For now, just create logical spus equal to the number
410	* of physical spus reserved for the partition.
411	*/
412
413	for (i = 0; i < num_resource_id; i++) {
414	enum ps3_spu_resource_type resource_type;
415	unsigned int resource_id;
416
417	result = ps3_repository_read_spu_resource_id(i,
418	&resource_type, &resource_id);
419
420	if (result)
421	break;
422
423	if (resource_type == PS3_SPU_RESOURCE_TYPE_EXCLUSIVE) {
424	result = fn((void*)(unsigned long)resource_id);
425
426	if (result)
427	break;
428	}
429	}
430
bce94513	431	if (result) {
de91a534 GL	432	printk(KERN_WARNING "%s:%d: Error initializing spus\n",
de91a534 GL	433	__func__, __LINE__);
bce94513 GU	434	return result;
bce94513 GU	435	}
de91a534	436
bce94513	437	return num_resource_id;
de91a534 GL	438	}
de91a534 GL	439
f5996449 AD	440	static int ps3_init_affinity(void)
	441	{
	442	return 0;
	443	}
	444
c25620d7 MN	445	/**
	446	* ps3_enable_spu - Enable SPU run control.
	447	*
	448	* An outstanding enhancement for the PS3 would be to add a guard to check
	449	* for incorrect access to the spu problem state when the spu context is
	450	* disabled. This check could be implemented with a flag added to the spu
	451	* context that would inhibit mapping problem state pages, and a routine
	452	* to unmap spu problem state pages. When the spu is enabled with
	453	* ps3_enable_spu() the flag would be set allowing pages to be mapped,
	454	* and when the spu is disabled with ps3_disable_spu() the flag would be
	455	* cleared and the mapped problem state pages would be unmapped.
	456	*/
	457
	458	static void ps3_enable_spu(struct spu_context *ctx)
	459	{
	460	}
	461
	462	static void ps3_disable_spu(struct spu_context *ctx)
	463	{
	464	ctx->ops->runcntl_stop(ctx);
	465	}
	466
de91a534 GL	467	const struct spu_management_ops spu_management_ps3_ops = {
	468	.enumerate_spus = ps3_enumerate_spus,
	469	.create_spu = ps3_create_spu,
	470	.destroy_spu = ps3_destroy_spu,
c25620d7 MN	471	.enable_spu = ps3_enable_spu,
c25620d7 MN	472	.disable_spu = ps3_disable_spu,
f5996449	473	.init_affinity = ps3_init_affinity,
de91a534 GL	474	};
	475
	476	/* spu_priv1_ops */
	477
	478	static void int_mask_and(struct spu *spu, int class, u64 mask)
	479	{
	480	u64 old_mask;
	481
	482	/* are these serialized by caller??? */
	483	old_mask = spu_int_mask_get(spu, class);
	484	spu_int_mask_set(spu, class, old_mask & mask);
	485	}
	486
	487	static void int_mask_or(struct spu *spu, int class, u64 mask)
	488	{
	489	u64 old_mask;
	490
	491	old_mask = spu_int_mask_get(spu, class);
	492	spu_int_mask_set(spu, class, old_mask \| mask);
	493	}
	494
	495	static void int_mask_set(struct spu *spu, int class, u64 mask)
	496	{
	497	spu_pdata(spu)->cache.masks[class] = mask;
	498	lv1_set_spe_interrupt_mask(spu_pdata(spu)->spe_id, class,
	499	spu_pdata(spu)->cache.masks[class]);
	500	}
	501
	502	static u64 int_mask_get(struct spu *spu, int class)
	503	{
	504	return spu_pdata(spu)->cache.masks[class];
	505	}
	506
	507	static void int_stat_clear(struct spu *spu, int class, u64 stat)
	508	{
	509	/* Note that MFC_DSISR will be cleared when class1[MF] is set. */
	510
	511	lv1_clear_spe_interrupt_status(spu_pdata(spu)->spe_id, class,
	512	stat, 0);
	513	}
	514
	515	static u64 int_stat_get(struct spu *spu, int class)
	516	{
	517	u64 stat;
	518
	519	lv1_get_spe_interrupt_status(spu_pdata(spu)->spe_id, class, &stat);
	520	return stat;
	521	}
	522
	523	static void cpu_affinity_set(struct spu *spu, int cpu)
	524	{
	525	/* No support. */
	526	}
	527
	528	static u64 mfc_dar_get(struct spu *spu)
	529	{
	530	return in_be64(&spu_pdata(spu)->shadow->mfc_dar_RW);
	531	}
	532
	533	static void mfc_dsisr_set(struct spu *spu, u64 dsisr)
	534	{
	535	/* Nothing to do, cleared in int_stat_clear(). */
	536	}
	537
538	static u64 mfc_dsisr_get(struct spu *spu)
539	{
540	return in_be64(&spu_pdata(spu)->shadow->mfc_dsisr_RW);
541	}
542
543	static void mfc_sdr_setup(struct spu *spu)
544	{
545	/* Nothing to do. */
546	}
547
548	static void mfc_sr1_set(struct spu *spu, u64 sr1)
549	{
550	/* Check bits allowed by HV. */
551
552	static const u64 allowed = ~(MFC_STATE1_LOCAL_STORAGE_DECODE_MASK
553	\| MFC_STATE1_PROBLEM_STATE_MASK);
554
555	BUG_ON((sr1 & allowed) != (spu_pdata(spu)->cache.sr1 & allowed));
556
557	spu_pdata(spu)->cache.sr1 = sr1;
558	lv1_set_spe_privilege_state_area_1_register(
559	spu_pdata(spu)->spe_id,
560	offsetof(struct spu_priv1, mfc_sr1_RW),
561	spu_pdata(spu)->cache.sr1);
562	}
563
564	static u64 mfc_sr1_get(struct spu *spu)
565	{
566	return spu_pdata(spu)->cache.sr1;
567	}
568
569	static void mfc_tclass_id_set(struct spu *spu, u64 tclass_id)
570	{
571	spu_pdata(spu)->cache.tclass_id = tclass_id;
572	lv1_set_spe_privilege_state_area_1_register(
573	spu_pdata(spu)->spe_id,
574	offsetof(struct spu_priv1, mfc_tclass_id_RW),
575	spu_pdata(spu)->cache.tclass_id);
576	}
577
578	static u64 mfc_tclass_id_get(struct spu *spu)
579	{
580	return spu_pdata(spu)->cache.tclass_id;
581	}
582
583	static void tlb_invalidate(struct spu *spu)
584	{
585	/* Nothing to do. */
586	}
587
588	static void resource_allocation_groupID_set(struct spu *spu, u64 id)
589	{
590	/* No support. */
591	}
592
593	static u64 resource_allocation_groupID_get(struct spu *spu)
594	{
595	return 0; /* No support. */
596	}
597
598	static void resource_allocation_enable_set(struct spu *spu, u64 enable)
599	{
600	/* No support. */
601	}
602
603	static u64 resource_allocation_enable_get(struct spu *spu)
604	{
605	return 0; /* No support. */
606	}
607
608	const struct spu_priv1_ops spu_priv1_ps3_ops = {
609	.int_mask_and = int_mask_and,
610	.int_mask_or = int_mask_or,
611	.int_mask_set = int_mask_set,
612	.int_mask_get = int_mask_get,
613	.int_stat_clear = int_stat_clear,
614	.int_stat_get = int_stat_get,
615	.cpu_affinity_set = cpu_affinity_set,
616	.mfc_dar_get = mfc_dar_get,
617	.mfc_dsisr_set = mfc_dsisr_set,
618	.mfc_dsisr_get = mfc_dsisr_get,
619	.mfc_sdr_setup = mfc_sdr_setup,
620	.mfc_sr1_set = mfc_sr1_set,
621	.mfc_sr1_get = mfc_sr1_get,
622	.mfc_tclass_id_set = mfc_tclass_id_set,
623	.mfc_tclass_id_get = mfc_tclass_id_get,
624	.tlb_invalidate = tlb_invalidate,
625	.resource_allocation_groupID_set = resource_allocation_groupID_set,
626	.resource_allocation_groupID_get = resource_allocation_groupID_get,
627	.resource_allocation_enable_set = resource_allocation_enable_set,
628	.resource_allocation_enable_get = resource_allocation_enable_get,
629	};
630
631	void ps3_spu_set_platform(void)
632	{
633	spu_priv1_ops = &spu_priv1_ps3_ops;
634	spu_management_ops = &spu_management_ps3_ops;
635	}