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1da177e4 LT |
1 | /* |
2 | * eeh.c | |
3c8c90ab LV |
3 | * Copyright IBM Corporation 2001, 2005, 2006 |
4 | * Copyright Dave Engebretsen & Todd Inglett 2001 | |
5 | * Copyright Linas Vepstas 2005, 2006 | |
69376502 | 6 | * |
1da177e4 LT |
7 | * This program is free software; you can redistribute it and/or modify |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
69376502 | 11 | * |
1da177e4 LT |
12 | * This program is distributed in the hope that it will be useful, |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
69376502 | 16 | * |
1da177e4 LT |
17 | * You should have received a copy of the GNU General Public License |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
3c8c90ab LV |
20 | * |
21 | * Please address comments and feedback to Linas Vepstas <linas@austin.ibm.com> | |
1da177e4 LT |
22 | */ |
23 | ||
6dee3fb9 | 24 | #include <linux/delay.h> |
1da177e4 LT |
25 | #include <linux/init.h> |
26 | #include <linux/list.h> | |
1da177e4 LT |
27 | #include <linux/pci.h> |
28 | #include <linux/proc_fs.h> | |
29 | #include <linux/rbtree.h> | |
30 | #include <linux/seq_file.h> | |
31 | #include <linux/spinlock.h> | |
acaa6176 SR |
32 | #include <linux/of.h> |
33 | ||
69376502 | 34 | #include <asm/atomic.h> |
1da177e4 | 35 | #include <asm/eeh.h> |
172ca926 | 36 | #include <asm/eeh_event.h> |
1da177e4 LT |
37 | #include <asm/io.h> |
38 | #include <asm/machdep.h> | |
172ca926 | 39 | #include <asm/ppc-pci.h> |
1da177e4 | 40 | #include <asm/rtas.h> |
1da177e4 | 41 | |
1da177e4 LT |
42 | |
43 | /** Overview: | |
44 | * EEH, or "Extended Error Handling" is a PCI bridge technology for | |
45 | * dealing with PCI bus errors that can't be dealt with within the | |
46 | * usual PCI framework, except by check-stopping the CPU. Systems | |
47 | * that are designed for high-availability/reliability cannot afford | |
48 | * to crash due to a "mere" PCI error, thus the need for EEH. | |
49 | * An EEH-capable bridge operates by converting a detected error | |
50 | * into a "slot freeze", taking the PCI adapter off-line, making | |
51 | * the slot behave, from the OS'es point of view, as if the slot | |
52 | * were "empty": all reads return 0xff's and all writes are silently | |
53 | * ignored. EEH slot isolation events can be triggered by parity | |
54 | * errors on the address or data busses (e.g. during posted writes), | |
69376502 LV |
55 | * which in turn might be caused by low voltage on the bus, dust, |
56 | * vibration, humidity, radioactivity or plain-old failed hardware. | |
1da177e4 LT |
57 | * |
58 | * Note, however, that one of the leading causes of EEH slot | |
59 | * freeze events are buggy device drivers, buggy device microcode, | |
60 | * or buggy device hardware. This is because any attempt by the | |
61 | * device to bus-master data to a memory address that is not | |
62 | * assigned to the device will trigger a slot freeze. (The idea | |
63 | * is to prevent devices-gone-wild from corrupting system memory). | |
64 | * Buggy hardware/drivers will have a miserable time co-existing | |
65 | * with EEH. | |
66 | * | |
67 | * Ideally, a PCI device driver, when suspecting that an isolation | |
25985edc | 68 | * event has occurred (e.g. by reading 0xff's), will then ask EEH |
1da177e4 LT |
69 | * whether this is the case, and then take appropriate steps to |
70 | * reset the PCI slot, the PCI device, and then resume operations. | |
71 | * However, until that day, the checking is done here, with the | |
72 | * eeh_check_failure() routine embedded in the MMIO macros. If | |
73 | * the slot is found to be isolated, an "EEH Event" is synthesized | |
74 | * and sent out for processing. | |
75 | */ | |
76 | ||
5c1344e9 | 77 | /* If a device driver keeps reading an MMIO register in an interrupt |
f36c5227 MM |
78 | * handler after a slot isolation event, it might be broken. |
79 | * This sets the threshold for how many read attempts we allow | |
80 | * before printing an error message. | |
1da177e4 | 81 | */ |
2fd30be8 | 82 | #define EEH_MAX_FAILS 2100000 |
1da177e4 | 83 | |
17213c3b | 84 | /* Time to wait for a PCI slot to report status, in milliseconds */ |
9c547768 LV |
85 | #define PCI_BUS_RESET_WAIT_MSEC (60*1000) |
86 | ||
1da177e4 LT |
87 | /* RTAS tokens */ |
88 | static int ibm_set_eeh_option; | |
89 | static int ibm_set_slot_reset; | |
90 | static int ibm_read_slot_reset_state; | |
91 | static int ibm_read_slot_reset_state2; | |
92 | static int ibm_slot_error_detail; | |
25e591f6 | 93 | static int ibm_get_config_addr_info; |
147d6a37 | 94 | static int ibm_get_config_addr_info2; |
21e464dd | 95 | static int ibm_configure_bridge; |
1da177e4 | 96 | |
1e28a7dd DW |
97 | int eeh_subsystem_enabled; |
98 | EXPORT_SYMBOL(eeh_subsystem_enabled); | |
1da177e4 | 99 | |
fd761fd8 | 100 | /* Lock to avoid races due to multiple reports of an error */ |
3d372628 | 101 | static DEFINE_RAW_SPINLOCK(confirm_error_lock); |
fd761fd8 | 102 | |
17213c3b LV |
103 | /* Buffer for reporting slot-error-detail rtas calls. Its here |
104 | * in BSS, and not dynamically alloced, so that it ends up in | |
105 | * RMO where RTAS can access it. | |
106 | */ | |
1da177e4 LT |
107 | static unsigned char slot_errbuf[RTAS_ERROR_LOG_MAX]; |
108 | static DEFINE_SPINLOCK(slot_errbuf_lock); | |
109 | static int eeh_error_buf_size; | |
110 | ||
17213c3b LV |
111 | /* Buffer for reporting pci register dumps. Its here in BSS, and |
112 | * not dynamically alloced, so that it ends up in RMO where RTAS | |
113 | * can access it. | |
114 | */ | |
d99bb1db LV |
115 | #define EEH_PCI_REGS_LOG_LEN 4096 |
116 | static unsigned char pci_regs_buf[EEH_PCI_REGS_LOG_LEN]; | |
117 | ||
1da177e4 | 118 | /* System monitoring statistics */ |
257ffc64 LV |
119 | static unsigned long no_device; |
120 | static unsigned long no_dn; | |
121 | static unsigned long no_cfg_addr; | |
122 | static unsigned long ignored_check; | |
123 | static unsigned long total_mmio_ffs; | |
124 | static unsigned long false_positives; | |
257ffc64 | 125 | static unsigned long slot_resets; |
1da177e4 | 126 | |
7684b40c LV |
127 | #define IS_BRIDGE(class_code) (((class_code)<<16) == PCI_BASE_CLASS_BRIDGE) |
128 | ||
1da177e4 | 129 | /* --------------------------------------------------------------- */ |
5d5a0936 | 130 | /* Below lies the EEH event infrastructure */ |
1da177e4 | 131 | |
d99bb1db LV |
132 | static void rtas_slot_error_detail(struct pci_dn *pdn, int severity, |
133 | char *driver_log, size_t loglen) | |
df7242b1 | 134 | { |
fcb7543e | 135 | int config_addr; |
df7242b1 LV |
136 | unsigned long flags; |
137 | int rc; | |
138 | ||
139 | /* Log the error with the rtas logger */ | |
140 | spin_lock_irqsave(&slot_errbuf_lock, flags); | |
141 | memset(slot_errbuf, 0, eeh_error_buf_size); | |
142 | ||
fcb7543e LV |
143 | /* Use PE configuration address, if present */ |
144 | config_addr = pdn->eeh_config_addr; | |
145 | if (pdn->eeh_pe_config_addr) | |
146 | config_addr = pdn->eeh_pe_config_addr; | |
147 | ||
df7242b1 | 148 | rc = rtas_call(ibm_slot_error_detail, |
fcb7543e | 149 | 8, 1, NULL, config_addr, |
df7242b1 | 150 | BUID_HI(pdn->phb->buid), |
d99bb1db LV |
151 | BUID_LO(pdn->phb->buid), |
152 | virt_to_phys(driver_log), loglen, | |
df7242b1 LV |
153 | virt_to_phys(slot_errbuf), |
154 | eeh_error_buf_size, | |
155 | severity); | |
156 | ||
157 | if (rc == 0) | |
158 | log_error(slot_errbuf, ERR_TYPE_RTAS_LOG, 0); | |
159 | spin_unlock_irqrestore(&slot_errbuf_lock, flags); | |
160 | } | |
161 | ||
d99bb1db LV |
162 | /** |
163 | * gather_pci_data - copy assorted PCI config space registers to buff | |
164 | * @pdn: device to report data for | |
165 | * @buf: point to buffer in which to log | |
166 | * @len: amount of room in buffer | |
167 | * | |
168 | * This routine captures assorted PCI configuration space data, | |
169 | * and puts them into a buffer for RTAS error logging. | |
170 | */ | |
171 | static size_t gather_pci_data(struct pci_dn *pdn, char * buf, size_t len) | |
172 | { | |
0b9369f4 | 173 | struct pci_dev *dev = pdn->pcidev; |
d99bb1db | 174 | u32 cfg; |
fcf9892b | 175 | int cap, i; |
d99bb1db LV |
176 | int n = 0; |
177 | ||
fcf9892b LV |
178 | n += scnprintf(buf+n, len-n, "%s\n", pdn->node->full_name); |
179 | printk(KERN_WARNING "EEH: of node=%s\n", pdn->node->full_name); | |
180 | ||
d99bb1db | 181 | rtas_read_config(pdn, PCI_VENDOR_ID, 4, &cfg); |
fcf9892b LV |
182 | n += scnprintf(buf+n, len-n, "dev/vend:%08x\n", cfg); |
183 | printk(KERN_WARNING "EEH: PCI device/vendor: %08x\n", cfg); | |
184 | ||
d99bb1db LV |
185 | rtas_read_config(pdn, PCI_COMMAND, 4, &cfg); |
186 | n += scnprintf(buf+n, len-n, "cmd/stat:%x\n", cfg); | |
fcf9892b LV |
187 | printk(KERN_WARNING "EEH: PCI cmd/status register: %08x\n", cfg); |
188 | ||
b37ceefe LV |
189 | if (!dev) { |
190 | printk(KERN_WARNING "EEH: no PCI device for this of node\n"); | |
191 | return n; | |
192 | } | |
193 | ||
0b9369f4 LV |
194 | /* Gather bridge-specific registers */ |
195 | if (dev->class >> 16 == PCI_BASE_CLASS_BRIDGE) { | |
196 | rtas_read_config(pdn, PCI_SEC_STATUS, 2, &cfg); | |
197 | n += scnprintf(buf+n, len-n, "sec stat:%x\n", cfg); | |
198 | printk(KERN_WARNING "EEH: Bridge secondary status: %04x\n", cfg); | |
199 | ||
200 | rtas_read_config(pdn, PCI_BRIDGE_CONTROL, 2, &cfg); | |
201 | n += scnprintf(buf+n, len-n, "brdg ctl:%x\n", cfg); | |
202 | printk(KERN_WARNING "EEH: Bridge control: %04x\n", cfg); | |
203 | } | |
204 | ||
fcf9892b | 205 | /* Dump out the PCI-X command and status regs */ |
b37ceefe | 206 | cap = pci_find_capability(dev, PCI_CAP_ID_PCIX); |
fcf9892b LV |
207 | if (cap) { |
208 | rtas_read_config(pdn, cap, 4, &cfg); | |
209 | n += scnprintf(buf+n, len-n, "pcix-cmd:%x\n", cfg); | |
210 | printk(KERN_WARNING "EEH: PCI-X cmd: %08x\n", cfg); | |
211 | ||
212 | rtas_read_config(pdn, cap+4, 4, &cfg); | |
213 | n += scnprintf(buf+n, len-n, "pcix-stat:%x\n", cfg); | |
214 | printk(KERN_WARNING "EEH: PCI-X status: %08x\n", cfg); | |
215 | } | |
216 | ||
217 | /* If PCI-E capable, dump PCI-E cap 10, and the AER */ | |
b37ceefe | 218 | cap = pci_find_capability(dev, PCI_CAP_ID_EXP); |
fcf9892b LV |
219 | if (cap) { |
220 | n += scnprintf(buf+n, len-n, "pci-e cap10:\n"); | |
221 | printk(KERN_WARNING | |
222 | "EEH: PCI-E capabilities and status follow:\n"); | |
223 | ||
224 | for (i=0; i<=8; i++) { | |
225 | rtas_read_config(pdn, cap+4*i, 4, &cfg); | |
226 | n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg); | |
227 | printk(KERN_WARNING "EEH: PCI-E %02x: %08x\n", i, cfg); | |
228 | } | |
229 | ||
b37ceefe | 230 | cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); |
fcf9892b LV |
231 | if (cap) { |
232 | n += scnprintf(buf+n, len-n, "pci-e AER:\n"); | |
233 | printk(KERN_WARNING | |
234 | "EEH: PCI-E AER capability register set follows:\n"); | |
235 | ||
236 | for (i=0; i<14; i++) { | |
237 | rtas_read_config(pdn, cap+4*i, 4, &cfg); | |
238 | n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg); | |
239 | printk(KERN_WARNING "EEH: PCI-E AER %02x: %08x\n", i, cfg); | |
240 | } | |
241 | } | |
242 | } | |
0b9369f4 LV |
243 | |
244 | /* Gather status on devices under the bridge */ | |
245 | if (dev->class >> 16 == PCI_BASE_CLASS_BRIDGE) { | |
acaa6176 SR |
246 | struct device_node *dn; |
247 | ||
248 | for_each_child_of_node(pdn->node, dn) { | |
0b9369f4 LV |
249 | pdn = PCI_DN(dn); |
250 | if (pdn) | |
251 | n += gather_pci_data(pdn, buf+n, len-n); | |
0b9369f4 LV |
252 | } |
253 | } | |
254 | ||
d99bb1db LV |
255 | return n; |
256 | } | |
257 | ||
258 | void eeh_slot_error_detail(struct pci_dn *pdn, int severity) | |
259 | { | |
260 | size_t loglen = 0; | |
17213c3b | 261 | pci_regs_buf[0] = 0; |
d99bb1db LV |
262 | |
263 | rtas_pci_enable(pdn, EEH_THAW_MMIO); | |
264 | loglen = gather_pci_data(pdn, pci_regs_buf, EEH_PCI_REGS_LOG_LEN); | |
265 | ||
266 | rtas_slot_error_detail(pdn, severity, pci_regs_buf, loglen); | |
267 | } | |
268 | ||
1da177e4 LT |
269 | /** |
270 | * read_slot_reset_state - Read the reset state of a device node's slot | |
271 | * @dn: device node to read | |
272 | * @rets: array to return results in | |
273 | */ | |
69376502 | 274 | static int read_slot_reset_state(struct pci_dn *pdn, int rets[]) |
1da177e4 LT |
275 | { |
276 | int token, outputs; | |
fcb7543e | 277 | int config_addr; |
1da177e4 LT |
278 | |
279 | if (ibm_read_slot_reset_state2 != RTAS_UNKNOWN_SERVICE) { | |
280 | token = ibm_read_slot_reset_state2; | |
281 | outputs = 4; | |
282 | } else { | |
283 | token = ibm_read_slot_reset_state; | |
69376502 | 284 | rets[2] = 0; /* fake PE Unavailable info */ |
1da177e4 LT |
285 | outputs = 3; |
286 | } | |
287 | ||
fcb7543e LV |
288 | /* Use PE configuration address, if present */ |
289 | config_addr = pdn->eeh_config_addr; | |
290 | if (pdn->eeh_pe_config_addr) | |
291 | config_addr = pdn->eeh_pe_config_addr; | |
292 | ||
293 | return rtas_call(token, 3, outputs, rets, config_addr, | |
1635317f | 294 | BUID_HI(pdn->phb->buid), BUID_LO(pdn->phb->buid)); |
1da177e4 LT |
295 | } |
296 | ||
9c547768 LV |
297 | /** |
298 | * eeh_wait_for_slot_status - returns error status of slot | |
299 | * @pdn pci device node | |
300 | * @max_wait_msecs maximum number to millisecs to wait | |
301 | * | |
302 | * Return negative value if a permanent error, else return | |
303 | * Partition Endpoint (PE) status value. | |
304 | * | |
305 | * If @max_wait_msecs is positive, then this routine will | |
306 | * sleep until a valid status can be obtained, or until | |
307 | * the max allowed wait time is exceeded, in which case | |
308 | * a -2 is returned. | |
309 | */ | |
310 | int | |
311 | eeh_wait_for_slot_status(struct pci_dn *pdn, int max_wait_msecs) | |
312 | { | |
313 | int rc; | |
314 | int rets[3]; | |
315 | int mwait; | |
316 | ||
317 | while (1) { | |
318 | rc = read_slot_reset_state(pdn, rets); | |
319 | if (rc) return rc; | |
320 | if (rets[1] == 0) return -1; /* EEH is not supported */ | |
321 | ||
322 | if (rets[0] != 5) return rets[0]; /* return actual status */ | |
323 | ||
324 | if (rets[2] == 0) return -1; /* permanently unavailable */ | |
325 | ||
2c84b407 | 326 | if (max_wait_msecs <= 0) break; |
9c547768 LV |
327 | |
328 | mwait = rets[2]; | |
329 | if (mwait <= 0) { | |
330 | printk (KERN_WARNING | |
331 | "EEH: Firmware returned bad wait value=%d\n", mwait); | |
332 | mwait = 1000; | |
333 | } else if (mwait > 300*1000) { | |
334 | printk (KERN_WARNING | |
335 | "EEH: Firmware is taking too long, time=%d\n", mwait); | |
336 | mwait = 300*1000; | |
337 | } | |
338 | max_wait_msecs -= mwait; | |
339 | msleep (mwait); | |
340 | } | |
341 | ||
342 | printk(KERN_WARNING "EEH: Timed out waiting for slot status\n"); | |
343 | return -2; | |
344 | } | |
345 | ||
1da177e4 LT |
346 | /** |
347 | * eeh_token_to_phys - convert EEH address token to phys address | |
69376502 | 348 | * @token i/o token, should be address in the form 0xA.... |
1da177e4 LT |
349 | */ |
350 | static inline unsigned long eeh_token_to_phys(unsigned long token) | |
351 | { | |
352 | pte_t *ptep; | |
353 | unsigned long pa; | |
354 | ||
20cee16c | 355 | ptep = find_linux_pte(init_mm.pgd, token); |
1da177e4 LT |
356 | if (!ptep) |
357 | return token; | |
358 | pa = pte_pfn(*ptep) << PAGE_SHIFT; | |
359 | ||
360 | return pa | (token & (PAGE_SIZE-1)); | |
361 | } | |
362 | ||
fd761fd8 LV |
363 | /** |
364 | * Return the "partitionable endpoint" (pe) under which this device lies | |
365 | */ | |
9fb40eb8 | 366 | struct device_node * find_device_pe(struct device_node *dn) |
fd761fd8 LV |
367 | { |
368 | while ((dn->parent) && PCI_DN(dn->parent) && | |
369 | (PCI_DN(dn->parent)->eeh_mode & EEH_MODE_SUPPORTED)) { | |
370 | dn = dn->parent; | |
371 | } | |
372 | return dn; | |
373 | } | |
374 | ||
acaa6176 | 375 | /** Mark all devices that are children of this device as failed. |
fd761fd8 LV |
376 | * Mark the device driver too, so that it can see the failure |
377 | * immediately; this is critical, since some drivers poll | |
378 | * status registers in interrupts ... If a driver is polling, | |
379 | * and the slot is frozen, then the driver can deadlock in | |
380 | * an interrupt context, which is bad. | |
381 | */ | |
382 | ||
acaa6176 | 383 | static void __eeh_mark_slot(struct device_node *parent, int mode_flag) |
fd761fd8 | 384 | { |
acaa6176 SR |
385 | struct device_node *dn; |
386 | ||
387 | for_each_child_of_node(parent, dn) { | |
d9564ad1 | 388 | if (PCI_DN(dn)) { |
77bd7415 LV |
389 | /* Mark the pci device driver too */ |
390 | struct pci_dev *dev = PCI_DN(dn)->pcidev; | |
ea183a95 OJ |
391 | |
392 | PCI_DN(dn)->eeh_mode |= mode_flag; | |
393 | ||
77bd7415 LV |
394 | if (dev && dev->driver) |
395 | dev->error_state = pci_channel_io_frozen; | |
396 | ||
acaa6176 | 397 | __eeh_mark_slot(dn, mode_flag); |
d9564ad1 | 398 | } |
fd761fd8 LV |
399 | } |
400 | } | |
401 | ||
d9564ad1 LV |
402 | void eeh_mark_slot (struct device_node *dn, int mode_flag) |
403 | { | |
022d51b1 | 404 | struct pci_dev *dev; |
d9564ad1 | 405 | dn = find_device_pe (dn); |
3914ac7b LV |
406 | |
407 | /* Back up one, since config addrs might be shared */ | |
4980d5eb | 408 | if (!pcibios_find_pci_bus(dn) && PCI_DN(dn->parent)) |
3914ac7b LV |
409 | dn = dn->parent; |
410 | ||
d9564ad1 | 411 | PCI_DN(dn)->eeh_mode |= mode_flag; |
022d51b1 LV |
412 | |
413 | /* Mark the pci device too */ | |
414 | dev = PCI_DN(dn)->pcidev; | |
415 | if (dev) | |
416 | dev->error_state = pci_channel_io_frozen; | |
417 | ||
acaa6176 | 418 | __eeh_mark_slot(dn, mode_flag); |
d9564ad1 LV |
419 | } |
420 | ||
acaa6176 | 421 | static void __eeh_clear_slot(struct device_node *parent, int mode_flag) |
fd761fd8 | 422 | { |
acaa6176 SR |
423 | struct device_node *dn; |
424 | ||
425 | for_each_child_of_node(parent, dn) { | |
d9564ad1 LV |
426 | if (PCI_DN(dn)) { |
427 | PCI_DN(dn)->eeh_mode &= ~mode_flag; | |
428 | PCI_DN(dn)->eeh_check_count = 0; | |
acaa6176 | 429 | __eeh_clear_slot(dn, mode_flag); |
d9564ad1 | 430 | } |
fd761fd8 LV |
431 | } |
432 | } | |
433 | ||
d9564ad1 | 434 | void eeh_clear_slot (struct device_node *dn, int mode_flag) |
fd761fd8 LV |
435 | { |
436 | unsigned long flags; | |
3d372628 | 437 | raw_spin_lock_irqsave(&confirm_error_lock, flags); |
3914ac7b | 438 | |
d9564ad1 | 439 | dn = find_device_pe (dn); |
3914ac7b LV |
440 | |
441 | /* Back up one, since config addrs might be shared */ | |
4980d5eb | 442 | if (!pcibios_find_pci_bus(dn) && PCI_DN(dn->parent)) |
3914ac7b LV |
443 | dn = dn->parent; |
444 | ||
d9564ad1 LV |
445 | PCI_DN(dn)->eeh_mode &= ~mode_flag; |
446 | PCI_DN(dn)->eeh_check_count = 0; | |
acaa6176 | 447 | __eeh_clear_slot(dn, mode_flag); |
3d372628 | 448 | raw_spin_unlock_irqrestore(&confirm_error_lock, flags); |
fd761fd8 LV |
449 | } |
450 | ||
1da177e4 LT |
451 | /** |
452 | * eeh_dn_check_failure - check if all 1's data is due to EEH slot freeze | |
453 | * @dn device node | |
454 | * @dev pci device, if known | |
455 | * | |
456 | * Check for an EEH failure for the given device node. Call this | |
457 | * routine if the result of a read was all 0xff's and you want to | |
458 | * find out if this is due to an EEH slot freeze. This routine | |
459 | * will query firmware for the EEH status. | |
460 | * | |
461 | * Returns 0 if there has not been an EEH error; otherwise returns | |
69376502 | 462 | * a non-zero value and queues up a slot isolation event notification. |
1da177e4 LT |
463 | * |
464 | * It is safe to call this routine in an interrupt context. | |
465 | */ | |
466 | int eeh_dn_check_failure(struct device_node *dn, struct pci_dev *dev) | |
467 | { | |
468 | int ret; | |
469 | int rets[3]; | |
470 | unsigned long flags; | |
1635317f | 471 | struct pci_dn *pdn; |
fd761fd8 | 472 | int rc = 0; |
f36c5227 | 473 | const char *location; |
1da177e4 | 474 | |
257ffc64 | 475 | total_mmio_ffs++; |
1da177e4 LT |
476 | |
477 | if (!eeh_subsystem_enabled) | |
478 | return 0; | |
479 | ||
177bc936 | 480 | if (!dn) { |
257ffc64 | 481 | no_dn++; |
1da177e4 | 482 | return 0; |
177bc936 | 483 | } |
307d46e8 | 484 | dn = find_device_pe(dn); |
69376502 | 485 | pdn = PCI_DN(dn); |
1da177e4 LT |
486 | |
487 | /* Access to IO BARs might get this far and still not want checking. */ | |
f8632c82 | 488 | if (!(pdn->eeh_mode & EEH_MODE_SUPPORTED) || |
1635317f | 489 | pdn->eeh_mode & EEH_MODE_NOCHECK) { |
257ffc64 | 490 | ignored_check++; |
57b066ff | 491 | pr_debug("EEH: Ignored check (%x) for %s %s\n", |
8d3d50bf | 492 | pdn->eeh_mode, eeh_pci_name(dev), dn->full_name); |
1da177e4 LT |
493 | return 0; |
494 | } | |
495 | ||
fcb7543e | 496 | if (!pdn->eeh_config_addr && !pdn->eeh_pe_config_addr) { |
257ffc64 | 497 | no_cfg_addr++; |
1da177e4 LT |
498 | return 0; |
499 | } | |
500 | ||
fd761fd8 LV |
501 | /* If we already have a pending isolation event for this |
502 | * slot, we know it's bad already, we don't need to check. | |
503 | * Do this checking under a lock; as multiple PCI devices | |
504 | * in one slot might report errors simultaneously, and we | |
505 | * only want one error recovery routine running. | |
1da177e4 | 506 | */ |
3d372628 | 507 | raw_spin_lock_irqsave(&confirm_error_lock, flags); |
fd761fd8 | 508 | rc = 1; |
1635317f | 509 | if (pdn->eeh_mode & EEH_MODE_ISOLATED) { |
5c1344e9 | 510 | pdn->eeh_check_count ++; |
f36c5227 MM |
511 | if (pdn->eeh_check_count % EEH_MAX_FAILS == 0) { |
512 | location = of_get_property(dn, "ibm,loc-code", NULL); | |
513 | printk (KERN_ERR "EEH: %d reads ignored for recovering device at " | |
514 | "location=%s driver=%s pci addr=%s\n", | |
515 | pdn->eeh_check_count, location, | |
8d3d50bf | 516 | dev->driver->name, eeh_pci_name(dev)); |
f36c5227 MM |
517 | printk (KERN_ERR "EEH: Might be infinite loop in %s driver\n", |
518 | dev->driver->name); | |
5c1344e9 | 519 | dump_stack(); |
1da177e4 | 520 | } |
fd761fd8 | 521 | goto dn_unlock; |
1da177e4 LT |
522 | } |
523 | ||
524 | /* | |
525 | * Now test for an EEH failure. This is VERY expensive. | |
526 | * Note that the eeh_config_addr may be a parent device | |
527 | * in the case of a device behind a bridge, or it may be | |
528 | * function zero of a multi-function device. | |
529 | * In any case they must share a common PHB. | |
530 | */ | |
69376502 | 531 | ret = read_slot_reset_state(pdn, rets); |
76e6faf7 LV |
532 | |
533 | /* If the call to firmware failed, punt */ | |
534 | if (ret != 0) { | |
535 | printk(KERN_WARNING "EEH: read_slot_reset_state() failed; rc=%d dn=%s\n", | |
536 | ret, dn->full_name); | |
257ffc64 | 537 | false_positives++; |
858955bd | 538 | pdn->eeh_false_positives ++; |
fd761fd8 LV |
539 | rc = 0; |
540 | goto dn_unlock; | |
76e6faf7 LV |
541 | } |
542 | ||
39d16e29 LV |
543 | /* Note that config-io to empty slots may fail; |
544 | * they are empty when they don't have children. */ | |
c9b65a7d | 545 | if ((rets[0] == 5) && (rets[2] == 0) && (dn->child == NULL)) { |
39d16e29 | 546 | false_positives++; |
858955bd | 547 | pdn->eeh_false_positives ++; |
39d16e29 LV |
548 | rc = 0; |
549 | goto dn_unlock; | |
550 | } | |
551 | ||
76e6faf7 LV |
552 | /* If EEH is not supported on this device, punt. */ |
553 | if (rets[1] != 1) { | |
554 | printk(KERN_WARNING "EEH: event on unsupported device, rc=%d dn=%s\n", | |
555 | ret, dn->full_name); | |
257ffc64 | 556 | false_positives++; |
858955bd | 557 | pdn->eeh_false_positives ++; |
fd761fd8 LV |
558 | rc = 0; |
559 | goto dn_unlock; | |
76e6faf7 LV |
560 | } |
561 | ||
562 | /* If not the kind of error we know about, punt. */ | |
90375f53 | 563 | if (rets[0] != 1 && rets[0] != 2 && rets[0] != 4 && rets[0] != 5) { |
257ffc64 | 564 | false_positives++; |
858955bd | 565 | pdn->eeh_false_positives ++; |
fd761fd8 LV |
566 | rc = 0; |
567 | goto dn_unlock; | |
76e6faf7 LV |
568 | } |
569 | ||
257ffc64 | 570 | slot_resets++; |
fd761fd8 LV |
571 | |
572 | /* Avoid repeated reports of this failure, including problems | |
573 | * with other functions on this device, and functions under | |
574 | * bridges. */ | |
d9564ad1 | 575 | eeh_mark_slot (dn, EEH_MODE_ISOLATED); |
3d372628 | 576 | raw_spin_unlock_irqrestore(&confirm_error_lock, flags); |
1da177e4 | 577 | |
d0ab95ca | 578 | eeh_send_failure_event (dn, dev); |
77bd7415 | 579 | |
1da177e4 LT |
580 | /* Most EEH events are due to device driver bugs. Having |
581 | * a stack trace will help the device-driver authors figure | |
582 | * out what happened. So print that out. */ | |
90375f53 | 583 | dump_stack(); |
fd761fd8 LV |
584 | return 1; |
585 | ||
586 | dn_unlock: | |
3d372628 | 587 | raw_spin_unlock_irqrestore(&confirm_error_lock, flags); |
fd761fd8 | 588 | return rc; |
1da177e4 LT |
589 | } |
590 | ||
fd761fd8 | 591 | EXPORT_SYMBOL_GPL(eeh_dn_check_failure); |
1da177e4 LT |
592 | |
593 | /** | |
594 | * eeh_check_failure - check if all 1's data is due to EEH slot freeze | |
595 | * @token i/o token, should be address in the form 0xA.... | |
596 | * @val value, should be all 1's (XXX why do we need this arg??) | |
597 | * | |
1da177e4 LT |
598 | * Check for an EEH failure at the given token address. Call this |
599 | * routine if the result of a read was all 0xff's and you want to | |
600 | * find out if this is due to an EEH slot freeze event. This routine | |
601 | * will query firmware for the EEH status. | |
602 | * | |
603 | * Note this routine is safe to call in an interrupt context. | |
604 | */ | |
605 | unsigned long eeh_check_failure(const volatile void __iomem *token, unsigned long val) | |
606 | { | |
607 | unsigned long addr; | |
608 | struct pci_dev *dev; | |
609 | struct device_node *dn; | |
610 | ||
611 | /* Finding the phys addr + pci device; this is pretty quick. */ | |
612 | addr = eeh_token_to_phys((unsigned long __force) token); | |
613 | dev = pci_get_device_by_addr(addr); | |
177bc936 | 614 | if (!dev) { |
257ffc64 | 615 | no_device++; |
1da177e4 | 616 | return val; |
177bc936 | 617 | } |
1da177e4 LT |
618 | |
619 | dn = pci_device_to_OF_node(dev); | |
620 | eeh_dn_check_failure (dn, dev); | |
621 | ||
622 | pci_dev_put(dev); | |
623 | return val; | |
624 | } | |
625 | ||
626 | EXPORT_SYMBOL(eeh_check_failure); | |
627 | ||
6dee3fb9 LV |
628 | /* ------------------------------------------------------------- */ |
629 | /* The code below deals with error recovery */ | |
630 | ||
47b5c838 LV |
631 | /** |
632 | * rtas_pci_enable - enable MMIO or DMA transfers for this slot | |
633 | * @pdn pci device node | |
634 | */ | |
635 | ||
636 | int | |
637 | rtas_pci_enable(struct pci_dn *pdn, int function) | |
638 | { | |
639 | int config_addr; | |
640 | int rc; | |
641 | ||
642 | /* Use PE configuration address, if present */ | |
643 | config_addr = pdn->eeh_config_addr; | |
644 | if (pdn->eeh_pe_config_addr) | |
645 | config_addr = pdn->eeh_pe_config_addr; | |
646 | ||
647 | rc = rtas_call(ibm_set_eeh_option, 4, 1, NULL, | |
648 | config_addr, | |
649 | BUID_HI(pdn->phb->buid), | |
650 | BUID_LO(pdn->phb->buid), | |
651 | function); | |
652 | ||
653 | if (rc) | |
fa1be476 | 654 | printk(KERN_WARNING "EEH: Unexpected state change %d, err=%d dn=%s\n", |
47b5c838 LV |
655 | function, rc, pdn->node->full_name); |
656 | ||
fa1be476 LV |
657 | rc = eeh_wait_for_slot_status (pdn, PCI_BUS_RESET_WAIT_MSEC); |
658 | if ((rc == 4) && (function == EEH_THAW_MMIO)) | |
659 | return 0; | |
660 | ||
47b5c838 LV |
661 | return rc; |
662 | } | |
663 | ||
cb5b5624 LV |
664 | /** |
665 | * rtas_pci_slot_reset - raises/lowers the pci #RST line | |
666 | * @pdn pci device node | |
667 | * @state: 1/0 to raise/lower the #RST | |
6dee3fb9 LV |
668 | * |
669 | * Clear the EEH-frozen condition on a slot. This routine | |
670 | * asserts the PCI #RST line if the 'state' argument is '1', | |
671 | * and drops the #RST line if 'state is '0'. This routine is | |
672 | * safe to call in an interrupt context. | |
673 | * | |
674 | */ | |
675 | ||
676 | static void | |
677 | rtas_pci_slot_reset(struct pci_dn *pdn, int state) | |
678 | { | |
25e591f6 | 679 | int config_addr; |
6dee3fb9 LV |
680 | int rc; |
681 | ||
682 | BUG_ON (pdn==NULL); | |
683 | ||
684 | if (!pdn->phb) { | |
685 | printk (KERN_WARNING "EEH: in slot reset, device node %s has no phb\n", | |
686 | pdn->node->full_name); | |
687 | return; | |
688 | } | |
689 | ||
25e591f6 LV |
690 | /* Use PE configuration address, if present */ |
691 | config_addr = pdn->eeh_config_addr; | |
692 | if (pdn->eeh_pe_config_addr) | |
693 | config_addr = pdn->eeh_pe_config_addr; | |
694 | ||
6dee3fb9 | 695 | rc = rtas_call(ibm_set_slot_reset,4,1, NULL, |
25e591f6 | 696 | config_addr, |
6dee3fb9 LV |
697 | BUID_HI(pdn->phb->buid), |
698 | BUID_LO(pdn->phb->buid), | |
699 | state); | |
e1029263 LV |
700 | if (rc) |
701 | printk (KERN_WARNING "EEH: Unable to reset the failed slot," | |
702 | " (%d) #RST=%d dn=%s\n", | |
6dee3fb9 | 703 | rc, state, pdn->node->full_name); |
6dee3fb9 LV |
704 | } |
705 | ||
00c2ae35 BK |
706 | /** |
707 | * pcibios_set_pcie_slot_reset - Set PCI-E reset state | |
708 | * @dev: pci device struct | |
709 | * @state: reset state to enter | |
710 | * | |
711 | * Return value: | |
712 | * 0 if success | |
713 | **/ | |
714 | int pcibios_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) | |
715 | { | |
716 | struct device_node *dn = pci_device_to_OF_node(dev); | |
717 | struct pci_dn *pdn = PCI_DN(dn); | |
718 | ||
719 | switch (state) { | |
720 | case pcie_deassert_reset: | |
721 | rtas_pci_slot_reset(pdn, 0); | |
722 | break; | |
723 | case pcie_hot_reset: | |
724 | rtas_pci_slot_reset(pdn, 1); | |
725 | break; | |
726 | case pcie_warm_reset: | |
727 | rtas_pci_slot_reset(pdn, 3); | |
728 | break; | |
729 | default: | |
730 | return -EINVAL; | |
731 | }; | |
732 | ||
733 | return 0; | |
734 | } | |
735 | ||
cb5b5624 LV |
736 | /** |
737 | * rtas_set_slot_reset -- assert the pci #RST line for 1/4 second | |
738 | * @pdn: pci device node to be reset. | |
b6495c0c LV |
739 | * |
740 | * Return 0 if success, else a non-zero value. | |
6dee3fb9 LV |
741 | */ |
742 | ||
e1029263 | 743 | static void __rtas_set_slot_reset(struct pci_dn *pdn) |
6dee3fb9 | 744 | { |
6e19314c MM |
745 | struct pci_dev *dev = pdn->pcidev; |
746 | ||
747 | /* Determine type of EEH reset required by device, | |
748 | * default hot reset or fundamental reset | |
749 | */ | |
ce47c1c4 | 750 | if (dev && dev->needs_freset) |
6e19314c MM |
751 | rtas_pci_slot_reset(pdn, 3); |
752 | else | |
753 | rtas_pci_slot_reset(pdn, 1); | |
6dee3fb9 LV |
754 | |
755 | /* The PCI bus requires that the reset be held high for at least | |
756 | * a 100 milliseconds. We wait a bit longer 'just in case'. */ | |
757 | ||
758 | #define PCI_BUS_RST_HOLD_TIME_MSEC 250 | |
759 | msleep (PCI_BUS_RST_HOLD_TIME_MSEC); | |
d9564ad1 LV |
760 | |
761 | /* We might get hit with another EEH freeze as soon as the | |
762 | * pci slot reset line is dropped. Make sure we don't miss | |
763 | * these, and clear the flag now. */ | |
764 | eeh_clear_slot (pdn->node, EEH_MODE_ISOLATED); | |
765 | ||
6dee3fb9 LV |
766 | rtas_pci_slot_reset (pdn, 0); |
767 | ||
768 | /* After a PCI slot has been reset, the PCI Express spec requires | |
769 | * a 1.5 second idle time for the bus to stabilize, before starting | |
770 | * up traffic. */ | |
771 | #define PCI_BUS_SETTLE_TIME_MSEC 1800 | |
772 | msleep (PCI_BUS_SETTLE_TIME_MSEC); | |
e1029263 LV |
773 | } |
774 | ||
775 | int rtas_set_slot_reset(struct pci_dn *pdn) | |
776 | { | |
777 | int i, rc; | |
778 | ||
9c547768 LV |
779 | /* Take three shots at resetting the bus */ |
780 | for (i=0; i<3; i++) { | |
781 | __rtas_set_slot_reset(pdn); | |
6dee3fb9 | 782 | |
9c547768 | 783 | rc = eeh_wait_for_slot_status(pdn, PCI_BUS_RESET_WAIT_MSEC); |
b6495c0c LV |
784 | if (rc == 0) |
785 | return 0; | |
e1029263 | 786 | |
e1029263 | 787 | if (rc < 0) { |
12588da7 LV |
788 | printk(KERN_ERR "EEH: unrecoverable slot failure %s\n", |
789 | pdn->node->full_name); | |
b6495c0c | 790 | return -1; |
e1029263 | 791 | } |
12588da7 LV |
792 | printk(KERN_ERR "EEH: bus reset %d failed on slot %s, rc=%d\n", |
793 | i+1, pdn->node->full_name, rc); | |
6dee3fb9 | 794 | } |
b6495c0c | 795 | |
9c547768 | 796 | return -1; |
6dee3fb9 LV |
797 | } |
798 | ||
8b553f32 LV |
799 | /* ------------------------------------------------------- */ |
800 | /** Save and restore of PCI BARs | |
801 | * | |
802 | * Although firmware will set up BARs during boot, it doesn't | |
803 | * set up device BAR's after a device reset, although it will, | |
804 | * if requested, set up bridge configuration. Thus, we need to | |
805 | * configure the PCI devices ourselves. | |
806 | */ | |
807 | ||
808 | /** | |
809 | * __restore_bars - Restore the Base Address Registers | |
cb5b5624 LV |
810 | * @pdn: pci device node |
811 | * | |
8b553f32 LV |
812 | * Loads the PCI configuration space base address registers, |
813 | * the expansion ROM base address, the latency timer, and etc. | |
814 | * from the saved values in the device node. | |
815 | */ | |
816 | static inline void __restore_bars (struct pci_dn *pdn) | |
817 | { | |
818 | int i; | |
cde274c0 | 819 | u32 cmd; |
8b553f32 LV |
820 | |
821 | if (NULL==pdn->phb) return; | |
822 | for (i=4; i<10; i++) { | |
823 | rtas_write_config(pdn, i*4, 4, pdn->config_space[i]); | |
824 | } | |
825 | ||
826 | /* 12 == Expansion ROM Address */ | |
827 | rtas_write_config(pdn, 12*4, 4, pdn->config_space[12]); | |
828 | ||
829 | #define BYTE_SWAP(OFF) (8*((OFF)/4)+3-(OFF)) | |
830 | #define SAVED_BYTE(OFF) (((u8 *)(pdn->config_space))[BYTE_SWAP(OFF)]) | |
831 | ||
832 | rtas_write_config (pdn, PCI_CACHE_LINE_SIZE, 1, | |
833 | SAVED_BYTE(PCI_CACHE_LINE_SIZE)); | |
834 | ||
835 | rtas_write_config (pdn, PCI_LATENCY_TIMER, 1, | |
836 | SAVED_BYTE(PCI_LATENCY_TIMER)); | |
837 | ||
838 | /* max latency, min grant, interrupt pin and line */ | |
839 | rtas_write_config(pdn, 15*4, 4, pdn->config_space[15]); | |
cde274c0 MM |
840 | |
841 | /* Restore PERR & SERR bits, some devices require it, | |
842 | don't touch the other command bits */ | |
843 | rtas_read_config(pdn, PCI_COMMAND, 4, &cmd); | |
844 | if (pdn->config_space[1] & PCI_COMMAND_PARITY) | |
845 | cmd |= PCI_COMMAND_PARITY; | |
846 | else | |
847 | cmd &= ~PCI_COMMAND_PARITY; | |
848 | if (pdn->config_space[1] & PCI_COMMAND_SERR) | |
849 | cmd |= PCI_COMMAND_SERR; | |
850 | else | |
851 | cmd &= ~PCI_COMMAND_SERR; | |
852 | rtas_write_config(pdn, PCI_COMMAND, 4, cmd); | |
8b553f32 LV |
853 | } |
854 | ||
855 | /** | |
856 | * eeh_restore_bars - restore the PCI config space info | |
857 | * | |
858 | * This routine performs a recursive walk to the children | |
859 | * of this device as well. | |
860 | */ | |
861 | void eeh_restore_bars(struct pci_dn *pdn) | |
862 | { | |
863 | struct device_node *dn; | |
864 | if (!pdn) | |
865 | return; | |
866 | ||
7684b40c | 867 | if ((pdn->eeh_mode & EEH_MODE_SUPPORTED) && !IS_BRIDGE(pdn->class_code)) |
8b553f32 LV |
868 | __restore_bars (pdn); |
869 | ||
acaa6176 | 870 | for_each_child_of_node(pdn->node, dn) |
8b553f32 | 871 | eeh_restore_bars (PCI_DN(dn)); |
8b553f32 LV |
872 | } |
873 | ||
874 | /** | |
875 | * eeh_save_bars - save device bars | |
876 | * | |
877 | * Save the values of the device bars. Unlike the restore | |
878 | * routine, this routine is *not* recursive. This is because | |
31116f0b | 879 | * PCI devices are added individually; but, for the restore, |
8b553f32 LV |
880 | * an entire slot is reset at a time. |
881 | */ | |
7684b40c | 882 | static void eeh_save_bars(struct pci_dn *pdn) |
8b553f32 LV |
883 | { |
884 | int i; | |
885 | ||
7684b40c | 886 | if (!pdn ) |
8b553f32 LV |
887 | return; |
888 | ||
889 | for (i = 0; i < 16; i++) | |
7684b40c | 890 | rtas_read_config(pdn, i * 4, 4, &pdn->config_space[i]); |
8b553f32 LV |
891 | } |
892 | ||
893 | void | |
894 | rtas_configure_bridge(struct pci_dn *pdn) | |
895 | { | |
fcb7543e | 896 | int config_addr; |
8b553f32 LV |
897 | int rc; |
898 | ||
fcb7543e LV |
899 | /* Use PE configuration address, if present */ |
900 | config_addr = pdn->eeh_config_addr; | |
901 | if (pdn->eeh_pe_config_addr) | |
902 | config_addr = pdn->eeh_pe_config_addr; | |
903 | ||
21e464dd | 904 | rc = rtas_call(ibm_configure_bridge,3,1, NULL, |
fcb7543e | 905 | config_addr, |
8b553f32 LV |
906 | BUID_HI(pdn->phb->buid), |
907 | BUID_LO(pdn->phb->buid)); | |
908 | if (rc) { | |
909 | printk (KERN_WARNING "EEH: Unable to configure device bridge (%d) for %s\n", | |
910 | rc, pdn->node->full_name); | |
911 | } | |
912 | } | |
913 | ||
172ca926 LV |
914 | /* ------------------------------------------------------------- */ |
915 | /* The code below deals with enabling EEH for devices during the | |
916 | * early boot sequence. EEH must be enabled before any PCI probing | |
917 | * can be done. | |
918 | */ | |
919 | ||
920 | #define EEH_ENABLE 1 | |
921 | ||
1da177e4 LT |
922 | struct eeh_early_enable_info { |
923 | unsigned int buid_hi; | |
924 | unsigned int buid_lo; | |
925 | }; | |
926 | ||
147d6a37 LV |
927 | static int get_pe_addr (int config_addr, |
928 | struct eeh_early_enable_info *info) | |
929 | { | |
930 | unsigned int rets[3]; | |
931 | int ret; | |
932 | ||
933 | /* Use latest config-addr token on power6 */ | |
934 | if (ibm_get_config_addr_info2 != RTAS_UNKNOWN_SERVICE) { | |
935 | /* Make sure we have a PE in hand */ | |
936 | ret = rtas_call (ibm_get_config_addr_info2, 4, 2, rets, | |
937 | config_addr, info->buid_hi, info->buid_lo, 1); | |
938 | if (ret || (rets[0]==0)) | |
939 | return 0; | |
940 | ||
941 | ret = rtas_call (ibm_get_config_addr_info2, 4, 2, rets, | |
942 | config_addr, info->buid_hi, info->buid_lo, 0); | |
943 | if (ret) | |
944 | return 0; | |
945 | return rets[0]; | |
946 | } | |
947 | ||
948 | /* Use older config-addr token on power5 */ | |
949 | if (ibm_get_config_addr_info != RTAS_UNKNOWN_SERVICE) { | |
950 | ret = rtas_call (ibm_get_config_addr_info, 4, 2, rets, | |
951 | config_addr, info->buid_hi, info->buid_lo, 0); | |
952 | if (ret) | |
953 | return 0; | |
954 | return rets[0]; | |
955 | } | |
956 | return 0; | |
957 | } | |
958 | ||
1da177e4 LT |
959 | /* Enable eeh for the given device node. */ |
960 | static void *early_enable_eeh(struct device_node *dn, void *data) | |
961 | { | |
25c4a46f | 962 | unsigned int rets[3]; |
1da177e4 LT |
963 | struct eeh_early_enable_info *info = data; |
964 | int ret; | |
e2eb6392 SR |
965 | const u32 *class_code = of_get_property(dn, "class-code", NULL); |
966 | const u32 *vendor_id = of_get_property(dn, "vendor-id", NULL); | |
967 | const u32 *device_id = of_get_property(dn, "device-id", NULL); | |
954a46e2 | 968 | const u32 *regs; |
1da177e4 | 969 | int enable; |
69376502 | 970 | struct pci_dn *pdn = PCI_DN(dn); |
1da177e4 | 971 | |
0f17574a | 972 | pdn->class_code = 0; |
1635317f | 973 | pdn->eeh_mode = 0; |
5c1344e9 LV |
974 | pdn->eeh_check_count = 0; |
975 | pdn->eeh_freeze_count = 0; | |
858955bd | 976 | pdn->eeh_false_positives = 0; |
1da177e4 | 977 | |
c6d4d5a8 NL |
978 | if (!of_device_is_available(dn)) |
979 | return NULL; | |
1da177e4 LT |
980 | |
981 | /* Ignore bad nodes. */ | |
982 | if (!class_code || !vendor_id || !device_id) | |
983 | return NULL; | |
984 | ||
985 | /* There is nothing to check on PCI to ISA bridges */ | |
986 | if (dn->type && !strcmp(dn->type, "isa")) { | |
1635317f | 987 | pdn->eeh_mode |= EEH_MODE_NOCHECK; |
1da177e4 LT |
988 | return NULL; |
989 | } | |
0f17574a | 990 | pdn->class_code = *class_code; |
1da177e4 | 991 | |
1da177e4 LT |
992 | /* Ok... see if this device supports EEH. Some do, some don't, |
993 | * and the only way to find out is to check each and every one. */ | |
e2eb6392 | 994 | regs = of_get_property(dn, "reg", NULL); |
1da177e4 LT |
995 | if (regs) { |
996 | /* First register entry is addr (00BBSS00) */ | |
997 | /* Try to enable eeh */ | |
998 | ret = rtas_call(ibm_set_eeh_option, 4, 1, NULL, | |
172ca926 LV |
999 | regs[0], info->buid_hi, info->buid_lo, |
1000 | EEH_ENABLE); | |
1001 | ||
25c4a46f | 1002 | enable = 0; |
1da177e4 | 1003 | if (ret == 0) { |
1635317f | 1004 | pdn->eeh_config_addr = regs[0]; |
25e591f6 LV |
1005 | |
1006 | /* If the newer, better, ibm,get-config-addr-info is supported, | |
1007 | * then use that instead. */ | |
147d6a37 | 1008 | pdn->eeh_pe_config_addr = get_pe_addr(pdn->eeh_config_addr, info); |
25c4a46f LV |
1009 | |
1010 | /* Some older systems (Power4) allow the | |
1011 | * ibm,set-eeh-option call to succeed even on nodes | |
1012 | * where EEH is not supported. Verify support | |
1013 | * explicitly. */ | |
1014 | ret = read_slot_reset_state(pdn, rets); | |
1015 | if ((ret == 0) && (rets[1] == 1)) | |
1016 | enable = 1; | |
1017 | } | |
1018 | ||
1019 | if (enable) { | |
1020 | eeh_subsystem_enabled = 1; | |
1021 | pdn->eeh_mode |= EEH_MODE_SUPPORTED; | |
1022 | ||
57b066ff BH |
1023 | pr_debug("EEH: %s: eeh enabled, config=%x pe_config=%x\n", |
1024 | dn->full_name, pdn->eeh_config_addr, | |
1025 | pdn->eeh_pe_config_addr); | |
1da177e4 LT |
1026 | } else { |
1027 | ||
1028 | /* This device doesn't support EEH, but it may have an | |
1029 | * EEH parent, in which case we mark it as supported. */ | |
69376502 | 1030 | if (dn->parent && PCI_DN(dn->parent) |
1635317f | 1031 | && (PCI_DN(dn->parent)->eeh_mode & EEH_MODE_SUPPORTED)) { |
1da177e4 | 1032 | /* Parent supports EEH. */ |
1635317f PM |
1033 | pdn->eeh_mode |= EEH_MODE_SUPPORTED; |
1034 | pdn->eeh_config_addr = PCI_DN(dn->parent)->eeh_config_addr; | |
1da177e4 LT |
1035 | return NULL; |
1036 | } | |
1037 | } | |
1038 | } else { | |
1039 | printk(KERN_WARNING "EEH: %s: unable to get reg property.\n", | |
1040 | dn->full_name); | |
1041 | } | |
1042 | ||
7684b40c | 1043 | eeh_save_bars(pdn); |
69376502 | 1044 | return NULL; |
1da177e4 LT |
1045 | } |
1046 | ||
1047 | /* | |
1048 | * Initialize EEH by trying to enable it for all of the adapters in the system. | |
1049 | * As a side effect we can determine here if eeh is supported at all. | |
1050 | * Note that we leave EEH on so failed config cycles won't cause a machine | |
1051 | * check. If a user turns off EEH for a particular adapter they are really | |
1052 | * telling Linux to ignore errors. Some hardware (e.g. POWER5) won't | |
1053 | * grant access to a slot if EEH isn't enabled, and so we always enable | |
1054 | * EEH for all slots/all devices. | |
1055 | * | |
1056 | * The eeh-force-off option disables EEH checking globally, for all slots. | |
1057 | * Even if force-off is set, the EEH hardware is still enabled, so that | |
1058 | * newer systems can boot. | |
1059 | */ | |
1060 | void __init eeh_init(void) | |
1061 | { | |
1062 | struct device_node *phb, *np; | |
1063 | struct eeh_early_enable_info info; | |
1064 | ||
3d372628 | 1065 | raw_spin_lock_init(&confirm_error_lock); |
df7242b1 LV |
1066 | spin_lock_init(&slot_errbuf_lock); |
1067 | ||
1da177e4 LT |
1068 | np = of_find_node_by_path("/rtas"); |
1069 | if (np == NULL) | |
1070 | return; | |
1071 | ||
1072 | ibm_set_eeh_option = rtas_token("ibm,set-eeh-option"); | |
1073 | ibm_set_slot_reset = rtas_token("ibm,set-slot-reset"); | |
1074 | ibm_read_slot_reset_state2 = rtas_token("ibm,read-slot-reset-state2"); | |
1075 | ibm_read_slot_reset_state = rtas_token("ibm,read-slot-reset-state"); | |
1076 | ibm_slot_error_detail = rtas_token("ibm,slot-error-detail"); | |
25e591f6 | 1077 | ibm_get_config_addr_info = rtas_token("ibm,get-config-addr-info"); |
147d6a37 | 1078 | ibm_get_config_addr_info2 = rtas_token("ibm,get-config-addr-info2"); |
21e464dd | 1079 | ibm_configure_bridge = rtas_token ("ibm,configure-bridge"); |
1da177e4 LT |
1080 | |
1081 | if (ibm_set_eeh_option == RTAS_UNKNOWN_SERVICE) | |
1082 | return; | |
1083 | ||
1084 | eeh_error_buf_size = rtas_token("rtas-error-log-max"); | |
1085 | if (eeh_error_buf_size == RTAS_UNKNOWN_SERVICE) { | |
1086 | eeh_error_buf_size = 1024; | |
1087 | } | |
1088 | if (eeh_error_buf_size > RTAS_ERROR_LOG_MAX) { | |
1089 | printk(KERN_WARNING "EEH: rtas-error-log-max is bigger than allocated " | |
1090 | "buffer ! (%d vs %d)", eeh_error_buf_size, RTAS_ERROR_LOG_MAX); | |
1091 | eeh_error_buf_size = RTAS_ERROR_LOG_MAX; | |
1092 | } | |
1093 | ||
1094 | /* Enable EEH for all adapters. Note that eeh requires buid's */ | |
1095 | for (phb = of_find_node_by_name(NULL, "pci"); phb; | |
1096 | phb = of_find_node_by_name(phb, "pci")) { | |
1097 | unsigned long buid; | |
1098 | ||
1099 | buid = get_phb_buid(phb); | |
69376502 | 1100 | if (buid == 0 || PCI_DN(phb) == NULL) |
1da177e4 LT |
1101 | continue; |
1102 | ||
1103 | info.buid_lo = BUID_LO(buid); | |
1104 | info.buid_hi = BUID_HI(buid); | |
1105 | traverse_pci_devices(phb, early_enable_eeh, &info); | |
1106 | } | |
1107 | ||
1108 | if (eeh_subsystem_enabled) | |
1109 | printk(KERN_INFO "EEH: PCI Enhanced I/O Error Handling Enabled\n"); | |
1110 | else | |
1111 | printk(KERN_WARNING "EEH: No capable adapters found\n"); | |
1112 | } | |
1113 | ||
1114 | /** | |
1115 | * eeh_add_device_early - enable EEH for the indicated device_node | |
1116 | * @dn: device node for which to set up EEH | |
1117 | * | |
1118 | * This routine must be used to perform EEH initialization for PCI | |
1119 | * devices that were added after system boot (e.g. hotplug, dlpar). | |
1120 | * This routine must be called before any i/o is performed to the | |
1121 | * adapter (inluding any config-space i/o). | |
1122 | * Whether this actually enables EEH or not for this device depends | |
1123 | * on the CEC architecture, type of the device, on earlier boot | |
1124 | * command-line arguments & etc. | |
1125 | */ | |
794e085e | 1126 | static void eeh_add_device_early(struct device_node *dn) |
1da177e4 LT |
1127 | { |
1128 | struct pci_controller *phb; | |
1129 | struct eeh_early_enable_info info; | |
1130 | ||
69376502 | 1131 | if (!dn || !PCI_DN(dn)) |
1da177e4 | 1132 | return; |
1635317f | 1133 | phb = PCI_DN(dn)->phb; |
f751f841 LV |
1134 | |
1135 | /* USB Bus children of PCI devices will not have BUID's */ | |
1136 | if (NULL == phb || 0 == phb->buid) | |
1da177e4 | 1137 | return; |
1da177e4 LT |
1138 | |
1139 | info.buid_hi = BUID_HI(phb->buid); | |
1140 | info.buid_lo = BUID_LO(phb->buid); | |
1141 | early_enable_eeh(dn, &info); | |
1142 | } | |
1da177e4 | 1143 | |
e2a296ee LV |
1144 | void eeh_add_device_tree_early(struct device_node *dn) |
1145 | { | |
1146 | struct device_node *sib; | |
acaa6176 SR |
1147 | |
1148 | for_each_child_of_node(dn, sib) | |
e2a296ee LV |
1149 | eeh_add_device_tree_early(sib); |
1150 | eeh_add_device_early(dn); | |
1151 | } | |
1152 | EXPORT_SYMBOL_GPL(eeh_add_device_tree_early); | |
1153 | ||
1da177e4 LT |
1154 | /** |
1155 | * eeh_add_device_late - perform EEH initialization for the indicated pci device | |
1156 | * @dev: pci device for which to set up EEH | |
1157 | * | |
1158 | * This routine must be used to complete EEH initialization for PCI | |
1159 | * devices that were added after system boot (e.g. hotplug, dlpar). | |
1160 | */ | |
794e085e | 1161 | static void eeh_add_device_late(struct pci_dev *dev) |
1da177e4 | 1162 | { |
56b0fca3 | 1163 | struct device_node *dn; |
8b553f32 | 1164 | struct pci_dn *pdn; |
56b0fca3 | 1165 | |
1da177e4 LT |
1166 | if (!dev || !eeh_subsystem_enabled) |
1167 | return; | |
1168 | ||
57b066ff | 1169 | pr_debug("EEH: Adding device %s\n", pci_name(dev)); |
1da177e4 | 1170 | |
56b0fca3 | 1171 | dn = pci_device_to_OF_node(dev); |
8b553f32 | 1172 | pdn = PCI_DN(dn); |
57b066ff BH |
1173 | if (pdn->pcidev == dev) { |
1174 | pr_debug("EEH: Already referenced !\n"); | |
1175 | return; | |
1176 | } | |
1177 | WARN_ON(pdn->pcidev); | |
1178 | ||
1179 | pci_dev_get (dev); | |
8b553f32 | 1180 | pdn->pcidev = dev; |
56b0fca3 | 1181 | |
e1d04c97 LV |
1182 | pci_addr_cache_insert_device(dev); |
1183 | eeh_sysfs_add_device(dev); | |
1da177e4 | 1184 | } |
794e085e NF |
1185 | |
1186 | void eeh_add_device_tree_late(struct pci_bus *bus) | |
1187 | { | |
1188 | struct pci_dev *dev; | |
1189 | ||
1190 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
1191 | eeh_add_device_late(dev); | |
1192 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { | |
1193 | struct pci_bus *subbus = dev->subordinate; | |
1194 | if (subbus) | |
1195 | eeh_add_device_tree_late(subbus); | |
1196 | } | |
1197 | } | |
1198 | } | |
1199 | EXPORT_SYMBOL_GPL(eeh_add_device_tree_late); | |
1da177e4 LT |
1200 | |
1201 | /** | |
1202 | * eeh_remove_device - undo EEH setup for the indicated pci device | |
1203 | * @dev: pci device to be removed | |
1204 | * | |
794e085e NF |
1205 | * This routine should be called when a device is removed from |
1206 | * a running system (e.g. by hotplug or dlpar). It unregisters | |
1207 | * the PCI device from the EEH subsystem. I/O errors affecting | |
1208 | * this device will no longer be detected after this call; thus, | |
1209 | * i/o errors affecting this slot may leave this device unusable. | |
1da177e4 | 1210 | */ |
794e085e | 1211 | static void eeh_remove_device(struct pci_dev *dev) |
1da177e4 | 1212 | { |
56b0fca3 | 1213 | struct device_node *dn; |
1da177e4 LT |
1214 | if (!dev || !eeh_subsystem_enabled) |
1215 | return; | |
1216 | ||
1217 | /* Unregister the device with the EEH/PCI address search system */ | |
57b066ff | 1218 | pr_debug("EEH: Removing device %s\n", pci_name(dev)); |
56b0fca3 LV |
1219 | |
1220 | dn = pci_device_to_OF_node(dev); | |
57b066ff BH |
1221 | if (PCI_DN(dn)->pcidev == NULL) { |
1222 | pr_debug("EEH: Not referenced !\n"); | |
1223 | return; | |
b055a9e1 | 1224 | } |
57b066ff BH |
1225 | PCI_DN(dn)->pcidev = NULL; |
1226 | pci_dev_put (dev); | |
1227 | ||
1228 | pci_addr_cache_remove_device(dev); | |
1229 | eeh_sysfs_remove_device(dev); | |
1da177e4 | 1230 | } |
1da177e4 | 1231 | |
e2a296ee LV |
1232 | void eeh_remove_bus_device(struct pci_dev *dev) |
1233 | { | |
794e085e NF |
1234 | struct pci_bus *bus = dev->subordinate; |
1235 | struct pci_dev *child, *tmp; | |
1236 | ||
e2a296ee | 1237 | eeh_remove_device(dev); |
794e085e NF |
1238 | |
1239 | if (bus && dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { | |
1240 | list_for_each_entry_safe(child, tmp, &bus->devices, bus_list) | |
1241 | eeh_remove_bus_device(child); | |
e2a296ee LV |
1242 | } |
1243 | } | |
1244 | EXPORT_SYMBOL_GPL(eeh_remove_bus_device); | |
1245 | ||
1da177e4 LT |
1246 | static int proc_eeh_show(struct seq_file *m, void *v) |
1247 | { | |
1da177e4 LT |
1248 | if (0 == eeh_subsystem_enabled) { |
1249 | seq_printf(m, "EEH Subsystem is globally disabled\n"); | |
257ffc64 | 1250 | seq_printf(m, "eeh_total_mmio_ffs=%ld\n", total_mmio_ffs); |
1da177e4 LT |
1251 | } else { |
1252 | seq_printf(m, "EEH Subsystem is enabled\n"); | |
177bc936 LV |
1253 | seq_printf(m, |
1254 | "no device=%ld\n" | |
1255 | "no device node=%ld\n" | |
1256 | "no config address=%ld\n" | |
1257 | "check not wanted=%ld\n" | |
1258 | "eeh_total_mmio_ffs=%ld\n" | |
1259 | "eeh_false_positives=%ld\n" | |
177bc936 | 1260 | "eeh_slot_resets=%ld\n", |
257ffc64 LV |
1261 | no_device, no_dn, no_cfg_addr, |
1262 | ignored_check, total_mmio_ffs, | |
42253a68 | 1263 | false_positives, |
257ffc64 | 1264 | slot_resets); |
1da177e4 LT |
1265 | } |
1266 | ||
1267 | return 0; | |
1268 | } | |
1269 | ||
1270 | static int proc_eeh_open(struct inode *inode, struct file *file) | |
1271 | { | |
1272 | return single_open(file, proc_eeh_show, NULL); | |
1273 | } | |
1274 | ||
5dfe4c96 | 1275 | static const struct file_operations proc_eeh_operations = { |
1da177e4 LT |
1276 | .open = proc_eeh_open, |
1277 | .read = seq_read, | |
1278 | .llseek = seq_lseek, | |
1279 | .release = single_release, | |
1280 | }; | |
1281 | ||
1282 | static int __init eeh_init_proc(void) | |
1283 | { | |
66747138 DL |
1284 | if (machine_is(pseries)) |
1285 | proc_create("ppc64/eeh", 0, NULL, &proc_eeh_operations); | |
1da177e4 LT |
1286 | return 0; |
1287 | } | |
1288 | __initcall(eeh_init_proc); |