[thirdparty/kernel/linux.git] / arch / s390 / include / asm / pci_clp.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_S390_PCI_CLP_H
#define _ASM_S390_PCI_CLP_H

#include <asm/clp.h>

/*
 * Call Logical Processor - Command Codes
 */
#define CLP_LIST_PCI		0x0002
#define CLP_QUERY_PCI_FN	0x0003
#define CLP_QUERY_PCI_FNGRP	0x0004
#define CLP_SET_PCI_FN		0x0005

/* PCI function handle list entry */
struct clp_fh_list_entry {
	u16 device_id;
	u16 vendor_id;
	u32 config_state :  1;
	u32		 : 31;
	u32 fid;		/* PCI function id */
	u32 fh;			/* PCI function handle */
} __packed;

#define CLP_RC_SETPCIFN_FH	0x0101	/* Invalid PCI fn handle */
#define CLP_RC_SETPCIFN_FHOP	0x0102	/* Fn handle not valid for op */
#define CLP_RC_SETPCIFN_DMAAS	0x0103	/* Invalid DMA addr space */
#define CLP_RC_SETPCIFN_RES	0x0104	/* Insufficient resources */
#define CLP_RC_SETPCIFN_ALRDY	0x0105	/* Fn already in requested state */
#define CLP_RC_SETPCIFN_ERR	0x0106	/* Fn in permanent error state */
#define CLP_RC_SETPCIFN_RECPND	0x0107	/* Error recovery pending */
#define CLP_RC_SETPCIFN_BUSY	0x0108	/* Fn busy */
#define CLP_RC_LISTPCI_BADRT	0x010a	/* Resume token not recognized */
#define CLP_RC_QUERYPCIFG_PFGID	0x010b	/* Unrecognized PFGID */

/* request or response block header length */
#define LIST_PCI_HDR_LEN	32

/* Number of function handles fitting in response block */
#define CLP_FH_LIST_NR_ENTRIES				\
	((CLP_BLK_SIZE - 2 * LIST_PCI_HDR_LEN)		\
		/ sizeof(struct clp_fh_list_entry))

#define CLP_SET_ENABLE_PCI_FN	0	/* Yes, 0 enables it */
#define CLP_SET_DISABLE_PCI_FN	1	/* Yes, 1 disables it */

#define CLP_UTIL_STR_LEN	64
#define CLP_PFIP_NR_SEGMENTS	4

extern bool zpci_unique_uid;

/* List PCI functions request */
struct clp_req_list_pci {
	struct clp_req_hdr hdr;
	u64 resume_token;
	u64 reserved2;
} __packed;

/* List PCI functions response */
struct clp_rsp_list_pci {
	struct clp_rsp_hdr hdr;
	u64 resume_token;
	u32 reserved2;
	u16 max_fn;
	u8			: 7;
	u8 uid_checking		: 1;
	u8 entry_size;
	struct clp_fh_list_entry fh_list[CLP_FH_LIST_NR_ENTRIES];
} __packed;

/* Query PCI function request */
struct clp_req_query_pci {
	struct clp_req_hdr hdr;
	u32 fh;				/* function handle */
	u32 reserved2;
	u64 reserved3;
} __packed;

/* Query PCI function response */
struct clp_rsp_query_pci {
	struct clp_rsp_hdr hdr;
	u16 vfn;			/* virtual fn number */
	u16			:  7;
	u16 util_str_avail	:  1;	/* utility string available? */
	u16 pfgid		:  8;	/* pci function group id */
	u32 fid;			/* pci function id */
	u8 bar_size[PCI_BAR_COUNT];
	u16 pchid;
	__le32 bar[PCI_BAR_COUNT];
	u8 pfip[CLP_PFIP_NR_SEGMENTS];	/* pci function internal path */
	u32			: 16;
	u8 fmb_len;
	u8 pft;				/* pci function type */
	u64 sdma;			/* start dma as */
	u64 edma;			/* end dma as */
	u32 reserved[11];
	u32 uid;			/* user defined id */
	u8 util_str[CLP_UTIL_STR_LEN];	/* utility string */
} __packed;

/* Query PCI function group request */
struct clp_req_query_pci_grp {
	struct clp_req_hdr hdr;
	u32 reserved2		: 24;
	u32 pfgid		:  8;	/* function group id */
	u32 reserved3;
	u64 reserved4;
} __packed;

/* Query PCI function group response */
struct clp_rsp_query_pci_grp {
	struct clp_rsp_hdr hdr;
	u16			:  4;
	u16 noi			: 12;	/* number of interrupts */
	u8 version;
	u8			:  6;
	u8 frame		:  1;
	u8 refresh		:  1;	/* TLB refresh mode */
	u16 reserved2;
	u16 mui;
	u64 reserved3;
	u64 dasm;			/* dma address space mask */
	u64 msia;			/* MSI address */
	u64 reserved4;
	u64 reserved5;
} __packed;

/* Set PCI function request */
struct clp_req_set_pci {
	struct clp_req_hdr hdr;
	u32 fh;				/* function handle */
	u16 reserved2;
	u8 oc;				/* operation controls */
	u8 ndas;			/* number of dma spaces */
	u64 reserved3;
} __packed;

/* Set PCI function response */
struct clp_rsp_set_pci {
	struct clp_rsp_hdr hdr;
	u32 fh;				/* function handle */
	u32 reserved3;
	u64 reserved4;
} __packed;

/* Combined request/response block structures used by clp insn */
struct clp_req_rsp_list_pci {
	struct clp_req_list_pci request;
	struct clp_rsp_list_pci response;
} __packed;

struct clp_req_rsp_set_pci {
	struct clp_req_set_pci request;
	struct clp_rsp_set_pci response;
} __packed;

struct clp_req_rsp_query_pci {
	struct clp_req_query_pci request;
	struct clp_rsp_query_pci response;
} __packed;

struct clp_req_rsp_query_pci_grp {
	struct clp_req_query_pci_grp request;
	struct clp_rsp_query_pci_grp response;
} __packed;

#endif
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
a755a45d JG	2	#ifndef _ASM_S390_PCI_CLP_H
	3	#define _ASM_S390_PCI_CLP_H
	4
	5	#include <asm/clp.h>
	6
	7	/*
	8	* Call Logical Processor - Command Codes
	9	*/
	10	#define CLP_LIST_PCI 0x0002
	11	#define CLP_QUERY_PCI_FN 0x0003
	12	#define CLP_QUERY_PCI_FNGRP 0x0004
	13	#define CLP_SET_PCI_FN 0x0005
	14
	15	/* PCI function handle list entry */
	16	struct clp_fh_list_entry {
	17	u16 device_id;
	18	u16 vendor_id;
	19	u32 config_state : 1;
	20	u32 : 31;
	21	u32 fid; /* PCI function id */
	22	u32 fh; /* PCI function handle */
	23	} __packed;
	24
	25	#define CLP_RC_SETPCIFN_FH 0x0101 /* Invalid PCI fn handle */
	26	#define CLP_RC_SETPCIFN_FHOP 0x0102 /* Fn handle not valid for op */
	27	#define CLP_RC_SETPCIFN_DMAAS 0x0103 /* Invalid DMA addr space */
	28	#define CLP_RC_SETPCIFN_RES 0x0104 /* Insufficient resources */
	29	#define CLP_RC_SETPCIFN_ALRDY 0x0105 /* Fn already in requested state */
	30	#define CLP_RC_SETPCIFN_ERR 0x0106 /* Fn in permanent error state */
	31	#define CLP_RC_SETPCIFN_RECPND 0x0107 /* Error recovery pending */
	32	#define CLP_RC_SETPCIFN_BUSY 0x0108 /* Fn busy */
	33	#define CLP_RC_LISTPCI_BADRT 0x010a /* Resume token not recognized */
	34	#define CLP_RC_QUERYPCIFG_PFGID 0x010b /* Unrecognized PFGID */
	35
	36	/* request or response block header length */
	37	#define LIST_PCI_HDR_LEN 32
	38
	39	/* Number of function handles fitting in response block */
	40	#define CLP_FH_LIST_NR_ENTRIES \
	41	((CLP_BLK_SIZE - 2 * LIST_PCI_HDR_LEN) \
	42	/ sizeof(struct clp_fh_list_entry))
	43
	44	#define CLP_SET_ENABLE_PCI_FN 0 /* Yes, 0 enables it */
	45	#define CLP_SET_DISABLE_PCI_FN 1 /* Yes, 1 disables it */
	46
	47	#define CLP_UTIL_STR_LEN 64
ac4995b9	48	#define CLP_PFIP_NR_SEGMENTS 4
a755a45d	49
5c5afd02 SO	50	extern bool zpci_unique_uid;
5c5afd02 SO	51
a755a45d JG	52	/* List PCI functions request */
	53	struct clp_req_list_pci {
	54	struct clp_req_hdr hdr;
a755a45d JG	55	u64 resume_token;
	56	u64 reserved2;
	57	} __packed;
	58
	59	/* List PCI functions response */
	60	struct clp_rsp_list_pci {
	61	struct clp_rsp_hdr hdr;
a755a45d JG	62	u64 resume_token;
	63	u32 reserved2;
	64	u16 max_fn;
5c5afd02 SO	65	u8 : 7;
5c5afd02 SO	66	u8 uid_checking : 1;
a755a45d JG	67	u8 entry_size;
	68	struct clp_fh_list_entry fh_list[CLP_FH_LIST_NR_ENTRIES];
	69	} __packed;
	70
	71	/* Query PCI function request */
	72	struct clp_req_query_pci {
	73	struct clp_req_hdr hdr;
a755a45d JG	74	u32 fh; /* function handle */
	75	u32 reserved2;
	76	u64 reserved3;
	77	} __packed;
	78
	79	/* Query PCI function response */
	80	struct clp_rsp_query_pci {
	81	struct clp_rsp_hdr hdr;
a755a45d JG	82	u16 vfn; /* virtual fn number */
	83	u16 : 7;
	84	u16 util_str_avail : 1; /* utility string available? */
	85	u16 pfgid : 8; /* pci function group id */
	86	u32 fid; /* pci function id */
	87	u8 bar_size[PCI_BAR_COUNT];
	88	u16 pchid;
5064cd35	89	__le32 bar[PCI_BAR_COUNT];
ac4995b9	90	u8 pfip[CLP_PFIP_NR_SEGMENTS]; /* pci function internal path */
0b7589ec SO	91	u32 : 16;
0b7589ec SO	92	u8 fmb_len;
ac4995b9	93	u8 pft; /* pci function type */
a755a45d JG	94	u64 sdma; /* start dma as */
a755a45d JG	95	u64 edma; /* end dma as */
ac4995b9 SO	96	u32 reserved[11];
ac4995b9 SO	97	u32 uid; /* user defined id */
a755a45d JG	98	u8 util_str[CLP_UTIL_STR_LEN]; /* utility string */
	99	} __packed;
	100
	101	/* Query PCI function group request */
	102	struct clp_req_query_pci_grp {
	103	struct clp_req_hdr hdr;
988b86e6	104	u32 reserved2 : 24;
a755a45d	105	u32 pfgid : 8; /* function group id */
988b86e6 MS	106	u32 reserved3;
988b86e6 MS	107	u64 reserved4;
a755a45d JG	108	} __packed;
	109
	110	/* Query PCI function group response */
	111	struct clp_rsp_query_pci_grp {
	112	struct clp_rsp_hdr hdr;
a755a45d JG	113	u16 : 4;
	114	u16 noi : 12; /* number of interrupts */
	115	u8 version;
	116	u8 : 6;
	117	u8 frame : 1;
	118	u8 refresh : 1; /* TLB refresh mode */
	119	u16 reserved2;
	120	u16 mui;
	121	u64 reserved3;
	122	u64 dasm; /* dma address space mask */
	123	u64 msia; /* MSI address */
	124	u64 reserved4;
	125	u64 reserved5;
	126	} __packed;
	127
	128	/* Set PCI function request */
	129	struct clp_req_set_pci {
	130	struct clp_req_hdr hdr;
a755a45d JG	131	u32 fh; /* function handle */
	132	u16 reserved2;
	133	u8 oc; /* operation controls */
	134	u8 ndas; /* number of dma spaces */
	135	u64 reserved3;
	136	} __packed;
	137
	138	/* Set PCI function response */
	139	struct clp_rsp_set_pci {
	140	struct clp_rsp_hdr hdr;
a755a45d JG	141	u32 fh; /* function handle */
	142	u32 reserved3;
	143	u64 reserved4;
	144	} __packed;
	145
	146	/* Combined request/response block structures used by clp insn */
	147	struct clp_req_rsp_list_pci {
	148	struct clp_req_list_pci request;
	149	struct clp_rsp_list_pci response;
	150	} __packed;
	151
	152	struct clp_req_rsp_set_pci {
	153	struct clp_req_set_pci request;
	154	struct clp_rsp_set_pci response;
	155	} __packed;
	156
	157	struct clp_req_rsp_query_pci {
	158	struct clp_req_query_pci request;
	159	struct clp_rsp_query_pci response;
	160	} __packed;
	161
	162	struct clp_req_rsp_query_pci_grp {
	163	struct clp_req_query_pci_grp request;
	164	struct clp_rsp_query_pci_grp response;
	165	} __packed;
	166
	167	#endif