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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
b02bad12 | 2 | /* |
b33718c6 VZ |
3 | * (C) Copyright 2016 Vladimir Zapolskiy <vz@mleia.com> |
4 | * (C) Copyright 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> | |
b02bad12 NI |
5 | */ |
6 | ||
7 | #include <common.h> | |
8 | #include <command.h> | |
9edefc27 | 9 | #include <cpu_func.h> |
90526e9f | 10 | #include <asm/cache.h> |
b02bad12 | 11 | #include <asm/io.h> |
c230a378 VZ |
12 | #include <asm/processor.h> |
13 | #include <asm/system.h> | |
b02bad12 NI |
14 | |
15 | #define CACHE_VALID 1 | |
16 | #define CACHE_UPDATED 2 | |
17 | ||
18 | static inline void cache_wback_all(void) | |
19 | { | |
20 | unsigned long addr, data, i, j; | |
21 | ||
6ab8b961 | 22 | for (i = 0; i < CACHE_OC_NUM_ENTRIES; i++) { |
b02bad12 | 23 | for (j = 0; j < CACHE_OC_NUM_WAYS; j++) { |
6ab8b961 VZ |
24 | addr = CACHE_OC_ADDRESS_ARRAY |
25 | | (j << CACHE_OC_WAY_SHIFT) | |
b02bad12 | 26 | | (i << CACHE_OC_ENTRY_SHIFT); |
53677ef1 | 27 | data = inl(addr); |
b02bad12 NI |
28 | if (data & CACHE_UPDATED) { |
29 | data &= ~CACHE_UPDATED; | |
30 | outl(data, addr); | |
31 | } | |
32 | } | |
33 | } | |
b02bad12 NI |
34 | } |
35 | ||
b02bad12 NI |
36 | #define CACHE_ENABLE 0 |
37 | #define CACHE_DISABLE 1 | |
38 | ||
b33718c6 | 39 | static int cache_control(unsigned int cmd) |
b02bad12 NI |
40 | { |
41 | unsigned long ccr; | |
42 | ||
43 | jump_to_P2(); | |
44 | ccr = inl(CCR); | |
45 | ||
46 | if (ccr & CCR_CACHE_ENABLE) | |
47 | cache_wback_all(); | |
48 | ||
49 | if (cmd == CACHE_DISABLE) | |
50 | outl(CCR_CACHE_STOP, CCR); | |
51 | else | |
52 | outl(CCR_CACHE_INIT, CCR); | |
53 | back_to_P1(); | |
54 | ||
55 | return 0; | |
56 | } | |
17210643 | 57 | |
a633a18f | 58 | void flush_dcache_range(unsigned long start, unsigned long end) |
17210643 MF |
59 | { |
60 | u32 v; | |
61 | ||
62 | start &= ~(L1_CACHE_BYTES - 1); | |
63 | for (v = start; v < end; v += L1_CACHE_BYTES) { | |
ee47c4cb | 64 | asm volatile ("ocbp %0" : /* no output */ |
17210643 MF |
65 | : "m" (__m(v))); |
66 | } | |
67 | } | |
68 | ||
a633a18f | 69 | void invalidate_dcache_range(unsigned long start, unsigned long end) |
17210643 MF |
70 | { |
71 | u32 v; | |
72 | ||
73 | start &= ~(L1_CACHE_BYTES - 1); | |
74 | for (v = start; v < end; v += L1_CACHE_BYTES) { | |
75 | asm volatile ("ocbi %0" : /* no output */ | |
76 | : "m" (__m(v))); | |
77 | } | |
78 | } | |
b33718c6 VZ |
79 | |
80 | void flush_cache(unsigned long addr, unsigned long size) | |
81 | { | |
82 | flush_dcache_range(addr , addr + size); | |
83 | } | |
84 | ||
85 | void icache_enable(void) | |
86 | { | |
87 | cache_control(CACHE_ENABLE); | |
88 | } | |
89 | ||
90 | void icache_disable(void) | |
91 | { | |
92 | cache_control(CACHE_DISABLE); | |
93 | } | |
94 | ||
95 | int icache_status(void) | |
96 | { | |
97 | return 0; | |
98 | } | |
99 | ||
100 | void dcache_enable(void) | |
101 | { | |
102 | } | |
103 | ||
104 | void dcache_disable(void) | |
105 | { | |
106 | } | |
107 | ||
108 | int dcache_status(void) | |
109 | { | |
110 | return 0; | |
111 | } |