projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| b02bad12 | 2 | /* |
| b55523ef | 3 | * (C) Copyright 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
| b02bad12 NI |
4 | */ |
| 5 | ||
| 0b135cfc NI |
6 | #ifndef _ASM_CPU_SH4_H_ |
| 7 | #define _ASM_CPU_SH4_H_ | |
| b02bad12 NI |
8 | |
| 9 | /* cache control */ | |
| 10 | #define CCR_CACHE_STOP 0x00000808 | |
| 11 | #define CCR_CACHE_ENABLE 0x00000101 | |
| 12 | #define CCR_CACHE_ICI 0x00000800 | |
| 13 | ||
| 14 | #define CACHE_OC_ADDRESS_ARRAY 0xf4000000 | |
| c54b9a42 NI |
15 | |
| 16 | #if defined (CONFIG_CPU_SH7750) || \ | |
| 17 | defined(CONFIG_CPU_SH7751) | |
| b02bad12 NI |
18 | #define CACHE_OC_WAY_SHIFT 14 |
| 19 | #define CACHE_OC_NUM_ENTRIES 512 | |
| c54b9a42 NI |
20 | #else |
| 21 | #define CACHE_OC_WAY_SHIFT 13 | |
| 22 | #define CACHE_OC_NUM_ENTRIES 256 | |
| 23 | #endif | |
| b02bad12 | 24 | #define CACHE_OC_ENTRY_SHIFT 5 |
| b02bad12 | 25 | |
| 56693327 NI |
26 | #if defined (CONFIG_CPU_SH7750) || \ |
| 27 | defined(CONFIG_CPU_SH7751) | |
| 28 | # include <asm/cpu_sh7750.h> | |
| b02bad12 | 29 | #elif defined (CONFIG_CPU_SH7722) |
| 56693327 | 30 | # include <asm/cpu_sh7722.h> |
| ab09f433 NI |
31 | #elif defined (CONFIG_CPU_SH7723) |
| 32 | # include <asm/cpu_sh7723.h> | |
| 2a57e7ec NI |
33 | #elif defined (CONFIG_CPU_SH7734) |
| 34 | # include <asm/cpu_sh7734.h> | |
| 1a2621ba YS |
35 | #elif defined (CONFIG_CPU_SH7752) |
| 36 | # include <asm/cpu_sh7752.h> | |
| 320cf350 YS |
37 | #elif defined (CONFIG_CPU_SH7753) |
| 38 | # include <asm/cpu_sh7753.h> | |
| 8e9c897b YS |
39 | #elif defined (CONFIG_CPU_SH7757) |
| 40 | # include <asm/cpu_sh7757.h> | |
| 60179098 NI |
41 | #elif defined (CONFIG_CPU_SH7763) |
| 42 | # include <asm/cpu_sh7763.h> | |
| b55523ef | 43 | #elif defined (CONFIG_CPU_SH7780) |
| 56693327 | 44 | # include <asm/cpu_sh7780.h> |
| 0b135cfc | 45 | #else |
| 56693327 | 46 | # error "Unknown SH4 variant" |
| 0b135cfc | 47 | #endif |
| b02bad12 | 48 | |
| 6d84ae39 YS |
49 | #if defined(CONFIG_SH_32BIT) |
| 50 | #define PMB_ADDR_ARRAY 0xf6100000 | |
| 51 | #define PMB_ADDR_ENTRY 8 | |
| 52 | #define PMB_VPN 24 | |
| 53 | ||
| 54 | #define PMB_DATA_ARRAY 0xf7100000 | |
| 55 | #define PMB_DATA_ENTRY 8 | |
| 56 | #define PMB_PPN 24 | |
| 57 | #define PMB_UB 9 /* Buffered write */ | |
| 58 | #define PMB_V 8 /* Valid */ | |
| 59 | #define PMB_SZ1 7 /* Page size (upper bit) */ | |
| 60 | #define PMB_SZ0 4 /* Page size (lower bit) */ | |
| 61 | #define PMB_C 3 /* Cacheability */ | |
| 62 | #define PMB_WT 0 /* Write-through */ | |
| 63 | ||
| 64 | #define PMB_ADDR_BASE(entry) (PMB_ADDR_ARRAY + (entry << PMB_ADDR_ENTRY)) | |
| 65 | #define PMB_DATA_BASE(entry) (PMB_DATA_ARRAY + (entry << PMB_DATA_ENTRY)) | |
| 66 | #define mk_pmb_addr_val(vpn) ((vpn << PMB_VPN)) | |
| 67 | #define mk_pmb_data_val(ppn, ub, v, sz1, sz0, c, wt) \ | |
| 68 | ((ppn << PMB_PPN) | (ub << PMB_UB) | \ | |
| 69 | (v << PMB_V) | (sz1 << PMB_SZ1) | \ | |
| 70 | (sz0 << PMB_SZ0) | (c << PMB_C) | \ | |
| 71 | (wt << PMB_WT)) | |
| 72 | #endif | |
| 73 | ||
| b02bad12 | 74 | #endif /* _ASM_CPU_SH4_H_ */ |