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1da177e4
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1/*
2 * Copyright (C) 1999 Niibe Yutaka
cdcc9708 3 * Copyright (C) 2003 - 2007 Paul Mundt
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4 *
5 * ASID handling idea taken from MIPS implementation.
6 */
7#ifndef __ASM_SH_MMU_CONTEXT_H
8#define __ASM_SH_MMU_CONTEXT_H
1da177e4 9
cdcc9708 10#ifdef __KERNEL__
f15cbe6f 11#include <cpu/mmu_context.h>
1da177e4 12#include <asm/tlbflush.h>
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13#include <asm/uaccess.h>
14#include <asm/io.h>
d6dd61c8 15#include <asm-generic/mm_hooks.h>
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16
17/*
18 * The MMU "context" consists of two things:
19 * (a) TLB cache version (or round, cycle whatever expression you like)
20 * (b) ASID (Address Space IDentifier)
21 */
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22#ifdef CONFIG_CPU_HAS_PTEAEX
23#define MMU_CONTEXT_ASID_MASK 0x0000ffff
24#else
1da177e4 25#define MMU_CONTEXT_ASID_MASK 0x000000ff
8263a67e 26#endif
1da177e4 27
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28#define MMU_CONTEXT_VERSION_MASK (~0UL & ~MMU_CONTEXT_ASID_MASK)
29#define MMU_CONTEXT_FIRST_VERSION (MMU_CONTEXT_ASID_MASK + 1)
30
31/* Impossible ASID value, to differentiate from NO_CONTEXT. */
32#define MMU_NO_ASID MMU_CONTEXT_FIRST_VERSION
33#define NO_CONTEXT 0UL
1da177e4 34
aec5e0e1 35#define asid_cache(cpu) (cpu_data[cpu].asid_cache)
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36
37#ifdef CONFIG_MMU
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38#define cpu_context(cpu, mm) ((mm)->context.id[cpu])
39
40#define cpu_asid(cpu, mm) \
41 (cpu_context((cpu), (mm)) & MMU_CONTEXT_ASID_MASK)
aec5e0e1 42
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43/*
44 * Virtual Page Number mask
45 */
46#define MMU_VPN_MASK 0xfffff000
47
cdcc9708 48#if defined(CONFIG_SUPERH32)
a1ce3928 49#include <asm/mmu_context_32.h>
cdcc9708 50#else
a1ce3928 51#include <asm/mmu_context_64.h>
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52#endif
53
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54/*
55 * Get MMU context if needed.
56 */
aec5e0e1 57static inline void get_mmu_context(struct mm_struct *mm, unsigned int cpu)
1da177e4 58{
aec5e0e1 59 unsigned long asid = asid_cache(cpu);
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60
61 /* Check if we have old version of context. */
aec5e0e1 62 if (((cpu_context(cpu, mm) ^ asid) & MMU_CONTEXT_VERSION_MASK) == 0)
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63 /* It's up to date, do nothing */
64 return;
65
66 /* It's old, we need to get new context with new version. */
aec5e0e1 67 if (!(++asid & MMU_CONTEXT_ASID_MASK)) {
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68 /*
69 * We exhaust ASID of this version.
70 * Flush all TLB and start new cycle.
71 */
711e522d 72 local_flush_tlb_all();
6e4662ff 73
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74#ifdef CONFIG_SUPERH64
75 /*
76 * The SH-5 cache uses the ASIDs, requiring both the I and D
77 * cache to be flushed when the ASID is exhausted. Weak.
78 */
79 flush_cache_all();
80#endif
81
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82 /*
83 * Fix version; Note that we avoid version #0
aa5e5dc2 84 * to distinguish NO_CONTEXT.
1da177e4 85 */
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86 if (!asid)
87 asid = MMU_CONTEXT_FIRST_VERSION;
1da177e4 88 }
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89
90 cpu_context(cpu, mm) = asid_cache(cpu) = asid;
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91}
92
93/*
94 * Initialize the context related info for a new mm_struct
95 * instance.
96 */
6e4662ff 97static inline int init_new_context(struct task_struct *tsk,
aec5e0e1 98 struct mm_struct *mm)
1da177e4 99{
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100 int i;
101
102 for (i = 0; i < num_online_cpus(); i++)
103 cpu_context(i, mm) = NO_CONTEXT;
104
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105 return 0;
106}
107
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108/*
109 * After we have set current->mm to a new value, this activates
110 * the context for the new mm so we see the new mappings.
111 */
aec5e0e1 112static inline void activate_context(struct mm_struct *mm, unsigned int cpu)
1da177e4 113{
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114 get_mmu_context(mm, cpu);
115 set_asid(cpu_asid(cpu, mm));
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116}
117
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118static inline void switch_mm(struct mm_struct *prev,
119 struct mm_struct *next,
120 struct task_struct *tsk)
121{
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122 unsigned int cpu = smp_processor_id();
123
6e4662ff 124 if (likely(prev != next)) {
74c86d67 125 cpumask_set_cpu(cpu, mm_cpumask(next));
6e4662ff 126 set_TTB(next->pgd);
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127 activate_context(next, cpu);
128 } else
74c86d67 129 if (!cpumask_test_and_set_cpu(cpu, mm_cpumask(next)))
aec5e0e1 130 activate_context(next, cpu);
1da177e4 131}
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132
133#define activate_mm(prev, next) switch_mm((prev),(next),NULL)
134#define deactivate_mm(tsk,mm) do { } while (0)
135#define enter_lazy_tlb(mm,tsk) do { } while (0)
136
cdcc9708 137#else
7b275822 138
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139#define set_asid(asid) do { } while (0)
140#define get_asid() (0)
35724a0a 141#define cpu_asid(cpu, mm) ({ (void)cpu; NO_CONTEXT; })
ccd80587 142#define switch_and_save_asid(asid) (0)
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143#define set_TTB(pgd) do { } while (0)
144#define get_TTB() (0)
cdcc9708 145
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146#include <asm-generic/mmu_context.h>
147
148#endif /* CONFIG_MMU */
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149
150#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4)
151/*
152 * If this processor has an MMU, we need methods to turn it off/on ..
153 * paging_init() will also have to be updated for the processor in
154 * question.
155 */
156static inline void enable_mmu(void)
157{
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158 unsigned int cpu = smp_processor_id();
159
1da177e4 160 /* Enable MMU */
9d56dd3b 161 __raw_writel(MMU_CONTROL_INIT, MMUCR);
29847622 162 ctrl_barrier();
1da177e4 163
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164 if (asid_cache(cpu) == NO_CONTEXT)
165 asid_cache(cpu) = MMU_CONTEXT_FIRST_VERSION;
1da177e4 166
aec5e0e1 167 set_asid(asid_cache(cpu) & MMU_CONTEXT_ASID_MASK);
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168}
169
170static inline void disable_mmu(void)
171{
172 unsigned long cr;
173
9d56dd3b 174 cr = __raw_readl(MMUCR);
1da177e4 175 cr &= ~MMU_CONTROL_INIT;
9d56dd3b 176 __raw_writel(cr, MMUCR);
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177
178 ctrl_barrier();
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179}
180#else
181/*
182 * MMU control handlers for processors lacking memory
183 * management hardware.
184 */
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185#define enable_mmu() do { } while (0)
186#define disable_mmu() do { } while (0)
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187#endif
188
189#endif /* __KERNEL__ */
190#endif /* __ASM_SH_MMU_CONTEXT_H */