[thirdparty/kernel/linux.git] / arch / sparc / kernel / etrap_64.S

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * etrap.S: Preparing for entry into the kernel on Sparc V9.
 *
 * Copyright (C) 1996, 1997 David S. Miller (davem@caip.rutgers.edu)
 * Copyright (C) 1997, 1998, 1999 Jakub Jelinek (jj@ultra.linux.cz)
 */


#include <asm/asi.h>
#include <asm/pstate.h>
#include <asm/ptrace.h>
#include <asm/page.h>
#include <asm/spitfire.h>
#include <asm/head.h>
#include <asm/processor.h>
#include <asm/mmu.h>

#define		TASK_REGOFF		(THREAD_SIZE-TRACEREG_SZ-STACKFRAME_SZ)
#define		ETRAP_PSTATE1		(PSTATE_TSO | PSTATE_PRIV)
#define		ETRAP_PSTATE2		\
		(PSTATE_TSO | PSTATE_PEF | PSTATE_PRIV | PSTATE_IE)

/*
 * On entry, %g7 is return address - 0x4.
 * %g4 and %g5 will be preserved %l4 and %l5 respectively.
 */

		.text		
		.align	64
		.globl	etrap_syscall, etrap, etrap_irq, etraptl1
etrap:		rdpr	%pil, %g2
etrap_irq:	clr	%g3
etrap_syscall:	TRAP_LOAD_THREAD_REG(%g6, %g1)
		rdpr	%tstate, %g1
		or	%g1, %g3, %g1
		sllx	%g2, 20, %g3
		andcc	%g1, TSTATE_PRIV, %g0
		or	%g1, %g3, %g1
		bne,pn	%xcc, 1f
		 sub	%sp, STACKFRAME_SZ+TRACEREG_SZ-STACK_BIAS, %g2
661:		wrpr	%g0, 7, %cleanwin
		.section .fast_win_ctrl_1insn_patch, "ax"
		.word	661b
		.word	0x85880000	! allclean
		.previous

		sethi	%hi(TASK_REGOFF), %g2
		sethi	%hi(TSTATE_PEF), %g3
		or	%g2, %lo(TASK_REGOFF), %g2
		and	%g1, %g3, %g3
		brnz,pn	%g3, 1f
		 add	%g6, %g2, %g2
		wr	%g0, 0, %fprs
1:		rdpr	%tpc, %g3

		stx	%g1, [%g2 + STACKFRAME_SZ + PT_V9_TSTATE]
		rdpr	%tnpc, %g1
		stx	%g3, [%g2 + STACKFRAME_SZ + PT_V9_TPC]
		rd	%y, %g3
		stx	%g1, [%g2 + STACKFRAME_SZ + PT_V9_TNPC]
		rdpr	%tt, %g1
		st	%g3, [%g2 + STACKFRAME_SZ + PT_V9_Y]
		sethi	%hi(PT_REGS_MAGIC), %g3
		or	%g3, %g1, %g1
		st	%g1, [%g2 + STACKFRAME_SZ + PT_V9_MAGIC]

		rdpr	%cansave, %g1
		brnz,pt %g1, etrap_save
		 nop

		rdpr	%cwp, %g1
		add	%g1, 2, %g1
		wrpr	%g1, %cwp
		be,pt	%xcc, etrap_user_spill
		 mov	ASI_AIUP, %g3

		rdpr	%otherwin, %g3
		brz	%g3, etrap_kernel_spill
		 mov	ASI_AIUS, %g3

etrap_user_spill:

		wr	%g3, 0x0, %asi
		ldx	[%g6 + TI_FLAGS], %g3
		and	%g3, _TIF_32BIT, %g3
		brnz,pt	%g3, etrap_user_spill_32bit
		 nop
		ba,a,pt	%xcc, etrap_user_spill_64bit

etrap_save:	save	%g2, -STACK_BIAS, %sp
		mov	%g6, %l6

		bne,pn	%xcc, 3f
		 mov	PRIMARY_CONTEXT, %l4
661:		rdpr	%canrestore, %g3
		.section .fast_win_ctrl_1insn_patch, "ax"
		.word	661b
		nop
		.previous

		rdpr	%wstate, %g2
661:		wrpr	%g0, 0, %canrestore
		.section .fast_win_ctrl_1insn_patch, "ax"
		.word	661b
		nop
		.previous
		sll	%g2, 3, %g2

		/* Set TI_SYS_FPDEPTH to 1 and clear TI_SYS_NOERROR.  */
		mov	1, %l5
		sth	%l5, [%l6 + TI_SYS_NOERROR]

661:		wrpr	%g3, 0, %otherwin
		.section .fast_win_ctrl_1insn_patch, "ax"
		.word	661b
		.word	0x87880000	! otherw
		.previous

		wrpr	%g2, 0, %wstate
		sethi	%hi(sparc64_kern_pri_context), %g2
		ldx	[%g2 + %lo(sparc64_kern_pri_context)], %g3

661:		stxa	%g3, [%l4] ASI_DMMU
		.section .sun4v_1insn_patch, "ax"
		.word	661b
		stxa	%g3, [%l4] ASI_MMU
		.previous

		sethi	%hi(KERNBASE), %l4
		flush	%l4
		mov	ASI_AIUS, %l7
2:		mov	%g4, %l4
		mov	%g5, %l5
		add	%g7, 4, %l2

		/* Go to trap time globals so we can save them.  */
661:		wrpr	%g0, ETRAP_PSTATE1, %pstate
		.section .sun4v_1insn_patch, "ax"
		.word	661b
		SET_GL(0)
		.previous

		stx	%g1, [%sp + PTREGS_OFF + PT_V9_G1]
		stx	%g2, [%sp + PTREGS_OFF + PT_V9_G2]
		sllx	%l7, 24, %l7
		stx	%g3, [%sp + PTREGS_OFF + PT_V9_G3]
		rdpr	%cwp, %l0
		stx	%g4, [%sp + PTREGS_OFF + PT_V9_G4]
		stx	%g5, [%sp + PTREGS_OFF + PT_V9_G5]
		stx	%g6, [%sp + PTREGS_OFF + PT_V9_G6]
		stx	%g7, [%sp + PTREGS_OFF + PT_V9_G7]
		or	%l7, %l0, %l7
		sethi	%hi(TSTATE_TSO | TSTATE_PEF), %l0
		or	%l7, %l0, %l7
		wrpr	%l2, %tnpc
		wrpr	%l7, (TSTATE_PRIV | TSTATE_IE), %tstate
		stx	%i0, [%sp + PTREGS_OFF + PT_V9_I0]
		stx	%i1, [%sp + PTREGS_OFF + PT_V9_I1]
		stx	%i2, [%sp + PTREGS_OFF + PT_V9_I2]
		stx	%i3, [%sp + PTREGS_OFF + PT_V9_I3]
		stx	%i4, [%sp + PTREGS_OFF + PT_V9_I4]
		stx	%i5, [%sp + PTREGS_OFF + PT_V9_I5]
		stx	%i6, [%sp + PTREGS_OFF + PT_V9_I6]
		mov	%l6, %g6
		stx	%i7, [%sp + PTREGS_OFF + PT_V9_I7]
		LOAD_PER_CPU_BASE(%g5, %g6, %g4, %g3, %l1)
		ldx	[%g6 + TI_TASK], %g4
		done

3:		mov	ASI_P, %l7
		ldub	[%l6 + TI_FPDEPTH], %l5
		add	%l6, TI_FPSAVED + 1, %l4
		srl	%l5, 1, %l3
		add	%l5, 2, %l5

		/* Set TI_SYS_FPDEPTH to %l5 and clear TI_SYS_NOERROR.  */
		sth	%l5, [%l6 + TI_SYS_NOERROR]
		ba,pt	%xcc, 2b
		 stb	%g0, [%l4 + %l3]
		nop

etraptl1:	/* Save tstate/tpc/tnpc of TL 1-->4 and the tl register itself.
		 * We place this right after pt_regs on the trap stack.
		 * The layout is:
		 *	0x00	TL1's TSTATE
		 *	0x08	TL1's TPC
		 *	0x10	TL1's TNPC
		 *	0x18	TL1's TT
		 *	 ...
		 *	0x58	TL4's TT
		 *	0x60	TL
		 */
		TRAP_LOAD_THREAD_REG(%g6, %g1)
		sub	%sp, ((4 * 8) * 4) + 8, %g2
		rdpr	%tl, %g1

		wrpr	%g0, 1, %tl
		rdpr	%tstate, %g3
		stx	%g3, [%g2 + STACK_BIAS + 0x00]
		rdpr	%tpc, %g3
		stx	%g3, [%g2 + STACK_BIAS + 0x08]
		rdpr	%tnpc, %g3
		stx	%g3, [%g2 + STACK_BIAS + 0x10]
		rdpr	%tt, %g3
		stx	%g3, [%g2 + STACK_BIAS + 0x18]

		wrpr	%g0, 2, %tl
		rdpr	%tstate, %g3
		stx	%g3, [%g2 + STACK_BIAS + 0x20]
		rdpr	%tpc, %g3
		stx	%g3, [%g2 + STACK_BIAS + 0x28]
		rdpr	%tnpc, %g3
		stx	%g3, [%g2 + STACK_BIAS + 0x30]
		rdpr	%tt, %g3
		stx	%g3, [%g2 + STACK_BIAS + 0x38]

		sethi	%hi(is_sun4v), %g3
		lduw	[%g3 + %lo(is_sun4v)], %g3
		brnz,pn	%g3, finish_tl1_capture
		 nop

		wrpr	%g0, 3, %tl
		rdpr	%tstate, %g3
		stx	%g3, [%g2 + STACK_BIAS + 0x40]
		rdpr	%tpc, %g3
		stx	%g3, [%g2 + STACK_BIAS + 0x48]
		rdpr	%tnpc, %g3
		stx	%g3, [%g2 + STACK_BIAS + 0x50]
		rdpr	%tt, %g3
		stx	%g3, [%g2 + STACK_BIAS + 0x58]

		wrpr	%g0, 4, %tl
		rdpr	%tstate, %g3
		stx	%g3, [%g2 + STACK_BIAS + 0x60]
		rdpr	%tpc, %g3
		stx	%g3, [%g2 + STACK_BIAS + 0x68]
		rdpr	%tnpc, %g3
		stx	%g3, [%g2 + STACK_BIAS + 0x70]
		rdpr	%tt, %g3
		stx	%g3, [%g2 + STACK_BIAS + 0x78]

		stx	%g1, [%g2 + STACK_BIAS + 0x80]

finish_tl1_capture:
		wrpr	%g0, 1, %tl
661:		nop
		.section .sun4v_1insn_patch, "ax"
		.word	661b
		SET_GL(1)
		.previous

		rdpr	%tstate, %g1
		sub	%g2, STACKFRAME_SZ + TRACEREG_SZ - STACK_BIAS, %g2
		ba,pt	%xcc, 1b
		 andcc	%g1, TSTATE_PRIV, %g0

#undef TASK_REGOFF
#undef ETRAP_PSTATE1
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
b00dc837	2	/*
1da177e4 LT	3	* etrap.S: Preparing for entry into the kernel on Sparc V9.
	4	*
	5	* Copyright (C) 1996, 1997 David S. Miller (davem@caip.rutgers.edu)
	6	* Copyright (C) 1997, 1998, 1999 Jakub Jelinek (jj@ultra.linux.cz)
	7	*/
	8
1da177e4 LT	9
	10	#include <asm/asi.h>
	11	#include <asm/pstate.h>
	12	#include <asm/ptrace.h>
	13	#include <asm/page.h>
	14	#include <asm/spitfire.h>
	15	#include <asm/head.h>
	16	#include <asm/processor.h>
	17	#include <asm/mmu.h>
	18
	19	#define TASK_REGOFF (THREAD_SIZE-TRACEREG_SZ-STACKFRAME_SZ)
64f2dde3	20	#define ETRAP_PSTATE1 (PSTATE_TSO \| PSTATE_PRIV)
1da177e4	21	#define ETRAP_PSTATE2 \
64f2dde3	22	(PSTATE_TSO \| PSTATE_PEF \| PSTATE_PRIV \| PSTATE_IE)
1da177e4 LT	23
	24	/*
	25	* On entry, %g7 is return address - 0x4.
	26	* %g4 and %g5 will be preserved %l4 and %l5 respectively.
	27	*/
	28
	29	.text
	30	.align 64
28e61036	31	.globl etrap_syscall, etrap, etrap_irq, etraptl1
1da177e4	32	etrap: rdpr %pil, %g2
28e61036 DM	33	etrap_irq: clr %g3
28e61036 DM	34	etrap_syscall: TRAP_LOAD_THREAD_REG(%g6, %g1)
1da177e4	35	rdpr %tstate, %g1
28e61036	36	or %g1, %g3, %g1
1da177e4 LT	37	sllx %g2, 20, %g3
	38	andcc %g1, TSTATE_PRIV, %g0
	39	or %g1, %g3, %g1
	40	bne,pn %xcc, 1f
	41	sub %sp, STACKFRAME_SZ+TRACEREG_SZ-STACK_BIAS, %g2
a7159a87 AY	42	661: wrpr %g0, 7, %cleanwin
	43	.section .fast_win_ctrl_1insn_patch, "ax"
	44	.word 661b
	45	.word 0x85880000 ! allclean
	46	.previous
1da177e4 LT	47
	48	sethi %hi(TASK_REGOFF), %g2
	49	sethi %hi(TSTATE_PEF), %g3
	50	or %g2, %lo(TASK_REGOFF), %g2
	51	and %g1, %g3, %g3
	52	brnz,pn %g3, 1f
	53	add %g6, %g2, %g2
	54	wr %g0, 0, %fprs
	55	1: rdpr %tpc, %g3
	56
	57	stx %g1, [%g2 + STACKFRAME_SZ + PT_V9_TSTATE]
	58	rdpr %tnpc, %g1
	59	stx %g3, [%g2 + STACKFRAME_SZ + PT_V9_TPC]
	60	rd %y, %g3
	61	stx %g1, [%g2 + STACKFRAME_SZ + PT_V9_TNPC]
8243e40a	62	rdpr %tt, %g1
1da177e4	63	st %g3, [%g2 + STACKFRAME_SZ + PT_V9_Y]
8243e40a DM	64	sethi %hi(PT_REGS_MAGIC), %g3
	65	or %g3, %g1, %g1
	66	st %g1, [%g2 + STACKFRAME_SZ + PT_V9_MAGIC]
314ef685 DM	67
	68	rdpr %cansave, %g1
	69	brnz,pt %g1, etrap_save
	70	nop
	71
	72	rdpr %cwp, %g1
	73	add %g1, 2, %g1
	74	wrpr %g1, %cwp
	75	be,pt %xcc, etrap_user_spill
	76	mov ASI_AIUP, %g3
	77
	78	rdpr %otherwin, %g3
	79	brz %g3, etrap_kernel_spill
	80	mov ASI_AIUS, %g3
	81
	82	etrap_user_spill:
	83
	84	wr %g3, 0x0, %asi
	85	ldx [%g6 + TI_FLAGS], %g3
	86	and %g3, _TIF_32BIT, %g3
	87	brnz,pt %g3, etrap_user_spill_32bit
	88	nop
	89	ba,a,pt %xcc, etrap_user_spill_64bit
	90
	91	etrap_save: save %g2, -STACK_BIAS, %sp
1da177e4 LT	92	mov %g6, %l6
	93
	94	bne,pn %xcc, 3f
	95	mov PRIMARY_CONTEXT, %l4
a7159a87 AY	96	661: rdpr %canrestore, %g3
	97	.section .fast_win_ctrl_1insn_patch, "ax"
	98	.word 661b
	99	nop
	100	.previous
	101
1da177e4	102	rdpr %wstate, %g2
a7159a87 AY	103	661: wrpr %g0, 0, %canrestore
	104	.section .fast_win_ctrl_1insn_patch, "ax"
	105	.word 661b
	106	nop
	107	.previous
1da177e4	108	sll %g2, 3, %g2
dff933da AV	109
dff933da AV	110	/* Set TI_SYS_FPDEPTH to 1 and clear TI_SYS_NOERROR. */
1da177e4	111	mov 1, %l5
dff933da	112	sth %l5, [%l6 + TI_SYS_NOERROR]
1da177e4	113
a7159a87 AY	114	661: wrpr %g3, 0, %otherwin
	115	.section .fast_win_ctrl_1insn_patch, "ax"
	116	.word 661b
	117	.word 0x87880000 ! otherw
	118	.previous
	119
1da177e4	120	wrpr %g2, 0, %wstate
0835ae0f DM	121	sethi %hi(sparc64_kern_pri_context), %g2
0835ae0f DM	122	ldx [%g2 + %lo(sparc64_kern_pri_context)], %g3
8b11bd12 DM	123
	124	661: stxa %g3, [%l4] ASI_DMMU
	125	.section .sun4v_1insn_patch, "ax"
	126	.word 661b
	127	stxa %g3, [%l4] ASI_MMU
	128	.previous
	129
4da808c3 DM	130	sethi %hi(KERNBASE), %l4
4da808c3 DM	131	flush %l4
6e02493a DM	132	mov ASI_AIUS, %l7
6e02493a DM	133	2: mov %g4, %l4
1da177e4	134	mov %g5, %l5
6e02493a	135	add %g7, 4, %l2
936f482a DM	136
	137	/* Go to trap time globals so we can save them. */
	138	661: wrpr %g0, ETRAP_PSTATE1, %pstate
df7d6aec	139	.section .sun4v_1insn_patch, "ax"
936f482a DM	140	.word 661b
	141	SET_GL(0)
	142	.previous
	143
1da177e4 LT	144	stx %g1, [%sp + PTREGS_OFF + PT_V9_G1]
1da177e4 LT	145	stx %g2, [%sp + PTREGS_OFF + PT_V9_G2]
6e02493a	146	sllx %l7, 24, %l7
1da177e4	147	stx %g3, [%sp + PTREGS_OFF + PT_V9_G3]
6e02493a	148	rdpr %cwp, %l0
1da177e4 LT	149	stx %g4, [%sp + PTREGS_OFF + PT_V9_G4]
	150	stx %g5, [%sp + PTREGS_OFF + PT_V9_G5]
	151	stx %g6, [%sp + PTREGS_OFF + PT_V9_G6]
1da177e4	152	stx %g7, [%sp + PTREGS_OFF + PT_V9_G7]
6e02493a	153	or %l7, %l0, %l7
64f2dde3	154	sethi %hi(TSTATE_TSO \| TSTATE_PEF), %l0
6e02493a DM	155	or %l7, %l0, %l7
	156	wrpr %l2, %tnpc
	157	wrpr %l7, (TSTATE_PRIV \| TSTATE_IE), %tstate
1da177e4 LT	158	stx %i0, [%sp + PTREGS_OFF + PT_V9_I0]
	159	stx %i1, [%sp + PTREGS_OFF + PT_V9_I1]
	160	stx %i2, [%sp + PTREGS_OFF + PT_V9_I2]
	161	stx %i3, [%sp + PTREGS_OFF + PT_V9_I3]
	162	stx %i4, [%sp + PTREGS_OFF + PT_V9_I4]
	163	stx %i5, [%sp + PTREGS_OFF + PT_V9_I5]
1da177e4	164	stx %i6, [%sp + PTREGS_OFF + PT_V9_I6]
1da177e4	165	mov %l6, %g6
6e02493a	166	stx %i7, [%sp + PTREGS_OFF + PT_V9_I7]
ffe483d5	167	LOAD_PER_CPU_BASE(%g5, %g6, %g4, %g3, %l1)
6e02493a DM	168	ldx [%g6 + TI_TASK], %g4
6e02493a DM	169	done
1da177e4	170
6e02493a DM	171	3: mov ASI_P, %l7
6e02493a DM	172	ldub [%l6 + TI_FPDEPTH], %l5
1da177e4 LT	173	add %l6, TI_FPSAVED + 1, %l4
	174	srl %l5, 1, %l3
	175	add %l5, 2, %l5
dff933da AV	176
	177	/* Set TI_SYS_FPDEPTH to %l5 and clear TI_SYS_NOERROR. */
	178	sth %l5, [%l6 + TI_SYS_NOERROR]
1da177e4 LT	179	ba,pt %xcc, 2b
	180	stb %g0, [%l4 + %l3]
	181	nop
	182
	183	etraptl1: /* Save tstate/tpc/tnpc of TL 1-->4 and the tl register itself.
	184	* We place this right after pt_regs on the trap stack.
	185	* The layout is:
	186	* 0x00 TL1's TSTATE
	187	* 0x08 TL1's TPC
	188	* 0x10 TL1's TNPC
	189	* 0x18 TL1's TT
	190	* ...
	191	* 0x58 TL4's TT
	192	* 0x60 TL
	193	*/
ffe483d5	194	TRAP_LOAD_THREAD_REG(%g6, %g1)
1da177e4 LT	195	sub %sp, ((4 * 8) * 4) + 8, %g2
	196	rdpr %tl, %g1
	197
	198	wrpr %g0, 1, %tl
	199	rdpr %tstate, %g3
	200	stx %g3, [%g2 + STACK_BIAS + 0x00]
	201	rdpr %tpc, %g3
	202	stx %g3, [%g2 + STACK_BIAS + 0x08]
	203	rdpr %tnpc, %g3
	204	stx %g3, [%g2 + STACK_BIAS + 0x10]
	205	rdpr %tt, %g3
	206	stx %g3, [%g2 + STACK_BIAS + 0x18]
	207
	208	wrpr %g0, 2, %tl
	209	rdpr %tstate, %g3
	210	stx %g3, [%g2 + STACK_BIAS + 0x20]
	211	rdpr %tpc, %g3
	212	stx %g3, [%g2 + STACK_BIAS + 0x28]
	213	rdpr %tnpc, %g3
	214	stx %g3, [%g2 + STACK_BIAS + 0x30]
	215	rdpr %tt, %g3
	216	stx %g3, [%g2 + STACK_BIAS + 0x38]
	217
3d6395cb DM	218	sethi %hi(is_sun4v), %g3
	219	lduw [%g3 + %lo(is_sun4v)], %g3
	220	brnz,pn %g3, finish_tl1_capture
	221	nop
	222
1da177e4 LT	223	wrpr %g0, 3, %tl
	224	rdpr %tstate, %g3
	225	stx %g3, [%g2 + STACK_BIAS + 0x40]
	226	rdpr %tpc, %g3
	227	stx %g3, [%g2 + STACK_BIAS + 0x48]
	228	rdpr %tnpc, %g3
	229	stx %g3, [%g2 + STACK_BIAS + 0x50]
	230	rdpr %tt, %g3
	231	stx %g3, [%g2 + STACK_BIAS + 0x58]
	232
	233	wrpr %g0, 4, %tl
	234	rdpr %tstate, %g3
	235	stx %g3, [%g2 + STACK_BIAS + 0x60]
	236	rdpr %tpc, %g3
	237	stx %g3, [%g2 + STACK_BIAS + 0x68]
	238	rdpr %tnpc, %g3
	239	stx %g3, [%g2 + STACK_BIAS + 0x70]
	240	rdpr %tt, %g3
	241	stx %g3, [%g2 + STACK_BIAS + 0x78]
	242
1da177e4 LT	243	stx %g1, [%g2 + STACK_BIAS + 0x80]
1da177e4 LT	244
3d6395cb	245	finish_tl1_capture:
936f482a DM	246	wrpr %g0, 1, %tl
936f482a DM	247	661: nop
df7d6aec	248	.section .sun4v_1insn_patch, "ax"
936f482a DM	249	.word 661b
	250	SET_GL(1)
	251	.previous
	252
1da177e4 LT	253	rdpr %tstate, %g1
	254	sub %g2, STACKFRAME_SZ + TRACEREG_SZ - STACK_BIAS, %g2
	255	ba,pt %xcc, 1b
	256	andcc %g1, TSTATE_PRIV, %g0
	257
1da177e4 LT	258	#undef TASK_REGOFF
1da177e4 LT	259	#undef ETRAP_PSTATE1