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Commit | Line | Data |
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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
ad7ad57c | 2 | /* iommu.c: Generic sparc64 IOMMU support. |
1da177e4 | 3 | * |
d284142c | 4 | * Copyright (C) 1999, 2007, 2008 David S. Miller (davem@davemloft.net) |
1da177e4 LT |
5 | * Copyright (C) 1999, 2000 Jakub Jelinek (jakub@redhat.com) |
6 | */ | |
7 | ||
8 | #include <linux/kernel.h> | |
066bcaca | 9 | #include <linux/export.h> |
5a0e3ad6 | 10 | #include <linux/slab.h> |
4dbc30fb | 11 | #include <linux/delay.h> |
ad7ad57c DM |
12 | #include <linux/device.h> |
13 | #include <linux/dma-mapping.h> | |
14 | #include <linux/errno.h> | |
d284142c | 15 | #include <linux/iommu-helper.h> |
a66022c4 | 16 | #include <linux/bitmap.h> |
bb620c3d | 17 | #include <linux/iommu-common.h> |
ad7ad57c DM |
18 | |
19 | #ifdef CONFIG_PCI | |
c57c2ffb | 20 | #include <linux/pci.h> |
ad7ad57c | 21 | #endif |
1da177e4 | 22 | |
ad7ad57c | 23 | #include <asm/iommu.h> |
1da177e4 LT |
24 | |
25 | #include "iommu_common.h" | |
4ac7b826 | 26 | #include "kernel.h" |
1da177e4 | 27 | |
ad7ad57c | 28 | #define STC_CTXMATCH_ADDR(STC, CTX) \ |
1da177e4 | 29 | ((STC)->strbuf_ctxmatch_base + ((CTX) << 3)) |
ad7ad57c DM |
30 | #define STC_FLUSHFLAG_INIT(STC) \ |
31 | (*((STC)->strbuf_flushflag) = 0UL) | |
32 | #define STC_FLUSHFLAG_SET(STC) \ | |
33 | (*((STC)->strbuf_flushflag) != 0UL) | |
1da177e4 | 34 | |
ad7ad57c | 35 | #define iommu_read(__reg) \ |
1da177e4 LT |
36 | ({ u64 __ret; \ |
37 | __asm__ __volatile__("ldxa [%1] %2, %0" \ | |
38 | : "=r" (__ret) \ | |
39 | : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \ | |
40 | : "memory"); \ | |
41 | __ret; \ | |
42 | }) | |
ad7ad57c | 43 | #define iommu_write(__reg, __val) \ |
1da177e4 LT |
44 | __asm__ __volatile__("stxa %0, [%1] %2" \ |
45 | : /* no outputs */ \ | |
46 | : "r" (__val), "r" (__reg), \ | |
47 | "i" (ASI_PHYS_BYPASS_EC_E)) | |
48 | ||
49 | /* Must be invoked under the IOMMU lock. */ | |
bb620c3d | 50 | static void iommu_flushall(struct iommu_map_table *iommu_map_table) |
1da177e4 | 51 | { |
bb620c3d | 52 | struct iommu *iommu = container_of(iommu_map_table, struct iommu, tbl); |
861fe906 | 53 | if (iommu->iommu_flushinv) { |
ad7ad57c | 54 | iommu_write(iommu->iommu_flushinv, ~(u64)0); |
861fe906 DM |
55 | } else { |
56 | unsigned long tag; | |
57 | int entry; | |
1da177e4 | 58 | |
ad7ad57c | 59 | tag = iommu->iommu_tags; |
861fe906 | 60 | for (entry = 0; entry < 16; entry++) { |
ad7ad57c | 61 | iommu_write(tag, 0); |
861fe906 DM |
62 | tag += 8; |
63 | } | |
1da177e4 | 64 | |
861fe906 | 65 | /* Ensure completion of previous PIO writes. */ |
ad7ad57c | 66 | (void) iommu_read(iommu->write_complete_reg); |
861fe906 | 67 | } |
1da177e4 LT |
68 | } |
69 | ||
70 | #define IOPTE_CONSISTENT(CTX) \ | |
71 | (IOPTE_VALID | IOPTE_CACHE | \ | |
72 | (((CTX) << 47) & IOPTE_CONTEXT)) | |
73 | ||
74 | #define IOPTE_STREAMING(CTX) \ | |
75 | (IOPTE_CONSISTENT(CTX) | IOPTE_STBUF) | |
76 | ||
77 | /* Existing mappings are never marked invalid, instead they | |
78 | * are pointed to a dummy page. | |
79 | */ | |
80 | #define IOPTE_IS_DUMMY(iommu, iopte) \ | |
81 | ((iopte_val(*iopte) & IOPTE_PAGE) == (iommu)->dummy_page_pa) | |
82 | ||
16ce82d8 | 83 | static inline void iopte_make_dummy(struct iommu *iommu, iopte_t *iopte) |
1da177e4 LT |
84 | { |
85 | unsigned long val = iopte_val(*iopte); | |
86 | ||
87 | val &= ~IOPTE_PAGE; | |
88 | val |= iommu->dummy_page_pa; | |
89 | ||
90 | iopte_val(*iopte) = val; | |
91 | } | |
92 | ||
ad7ad57c | 93 | int iommu_table_init(struct iommu *iommu, int tsbsize, |
c1b1a5f1 DM |
94 | u32 dma_offset, u32 dma_addr_mask, |
95 | int numa_node) | |
1da177e4 | 96 | { |
c1b1a5f1 DM |
97 | unsigned long i, order, sz, num_tsb_entries; |
98 | struct page *page; | |
688cb30b DM |
99 | |
100 | num_tsb_entries = tsbsize / sizeof(iopte_t); | |
51e85136 DM |
101 | |
102 | /* Setup initial software IOMMU state. */ | |
103 | spin_lock_init(&iommu->lock); | |
104 | iommu->ctx_lowest_free = 1; | |
bb620c3d | 105 | iommu->tbl.table_map_base = dma_offset; |
51e85136 DM |
106 | iommu->dma_addr_mask = dma_addr_mask; |
107 | ||
688cb30b DM |
108 | /* Allocate and initialize the free area map. */ |
109 | sz = num_tsb_entries / 8; | |
110 | sz = (sz + 7UL) & ~7UL; | |
bb620c3d SV |
111 | iommu->tbl.map = kmalloc_node(sz, GFP_KERNEL, numa_node); |
112 | if (!iommu->tbl.map) | |
ad7ad57c | 113 | return -ENOMEM; |
bb620c3d | 114 | memset(iommu->tbl.map, 0, sz); |
f1600e54 | 115 | |
bb620c3d SV |
116 | iommu_tbl_pool_init(&iommu->tbl, num_tsb_entries, IO_PAGE_SHIFT, |
117 | (tlb_type != hypervisor ? iommu_flushall : NULL), | |
118 | false, 1, false); | |
d284142c | 119 | |
51e85136 DM |
120 | /* Allocate and initialize the dummy page which we |
121 | * set inactive IO PTEs to point to. | |
122 | */ | |
c1b1a5f1 DM |
123 | page = alloc_pages_node(numa_node, GFP_KERNEL, 0); |
124 | if (!page) { | |
ad7ad57c DM |
125 | printk(KERN_ERR "IOMMU: Error, gfp(dummy_page) failed.\n"); |
126 | goto out_free_map; | |
51e85136 | 127 | } |
c1b1a5f1 DM |
128 | iommu->dummy_page = (unsigned long) page_address(page); |
129 | memset((void *)iommu->dummy_page, 0, PAGE_SIZE); | |
51e85136 DM |
130 | iommu->dummy_page_pa = (unsigned long) __pa(iommu->dummy_page); |
131 | ||
132 | /* Now allocate and setup the IOMMU page table itself. */ | |
133 | order = get_order(tsbsize); | |
c1b1a5f1 DM |
134 | page = alloc_pages_node(numa_node, GFP_KERNEL, order); |
135 | if (!page) { | |
ad7ad57c DM |
136 | printk(KERN_ERR "IOMMU: Error, gfp(tsb) failed.\n"); |
137 | goto out_free_dummy_page; | |
51e85136 | 138 | } |
c1b1a5f1 | 139 | iommu->page_table = (iopte_t *)page_address(page); |
1da177e4 | 140 | |
688cb30b | 141 | for (i = 0; i < num_tsb_entries; i++) |
1da177e4 | 142 | iopte_make_dummy(iommu, &iommu->page_table[i]); |
ad7ad57c DM |
143 | |
144 | return 0; | |
145 | ||
146 | out_free_dummy_page: | |
147 | free_page(iommu->dummy_page); | |
148 | iommu->dummy_page = 0UL; | |
149 | ||
150 | out_free_map: | |
bb620c3d SV |
151 | kfree(iommu->tbl.map); |
152 | iommu->tbl.map = NULL; | |
ad7ad57c DM |
153 | |
154 | return -ENOMEM; | |
1da177e4 LT |
155 | } |
156 | ||
bb620c3d SV |
157 | static inline iopte_t *alloc_npages(struct device *dev, |
158 | struct iommu *iommu, | |
d284142c | 159 | unsigned long npages) |
1da177e4 | 160 | { |
d284142c | 161 | unsigned long entry; |
1da177e4 | 162 | |
bb620c3d SV |
163 | entry = iommu_tbl_range_alloc(dev, &iommu->tbl, npages, NULL, |
164 | (unsigned long)(-1), 0); | |
d618382b | 165 | if (unlikely(entry == IOMMU_ERROR_CODE)) |
688cb30b | 166 | return NULL; |
1da177e4 | 167 | |
688cb30b | 168 | return iommu->page_table + entry; |
1da177e4 LT |
169 | } |
170 | ||
16ce82d8 | 171 | static int iommu_alloc_ctx(struct iommu *iommu) |
7c963ad1 DM |
172 | { |
173 | int lowest = iommu->ctx_lowest_free; | |
711c71a0 | 174 | int n = find_next_zero_bit(iommu->ctx_bitmap, IOMMU_NUM_CTXS, lowest); |
7c963ad1 | 175 | |
711c71a0 | 176 | if (unlikely(n == IOMMU_NUM_CTXS)) { |
7c963ad1 DM |
177 | n = find_next_zero_bit(iommu->ctx_bitmap, lowest, 1); |
178 | if (unlikely(n == lowest)) { | |
179 | printk(KERN_WARNING "IOMMU: Ran out of contexts.\n"); | |
180 | n = 0; | |
181 | } | |
182 | } | |
183 | if (n) | |
184 | __set_bit(n, iommu->ctx_bitmap); | |
185 | ||
186 | return n; | |
187 | } | |
188 | ||
16ce82d8 | 189 | static inline void iommu_free_ctx(struct iommu *iommu, int ctx) |
7c963ad1 DM |
190 | { |
191 | if (likely(ctx)) { | |
192 | __clear_bit(ctx, iommu->ctx_bitmap); | |
193 | if (ctx < iommu->ctx_lowest_free) | |
194 | iommu->ctx_lowest_free = ctx; | |
195 | } | |
196 | } | |
197 | ||
ad7ad57c | 198 | static void *dma_4u_alloc_coherent(struct device *dev, size_t size, |
c416258a | 199 | dma_addr_t *dma_addrp, gfp_t gfp, |
00085f1e | 200 | unsigned long attrs) |
1da177e4 | 201 | { |
bb620c3d | 202 | unsigned long order, first_page; |
16ce82d8 | 203 | struct iommu *iommu; |
c1b1a5f1 DM |
204 | struct page *page; |
205 | int npages, nid; | |
1da177e4 | 206 | iopte_t *iopte; |
1da177e4 | 207 | void *ret; |
1da177e4 LT |
208 | |
209 | size = IO_PAGE_ALIGN(size); | |
210 | order = get_order(size); | |
211 | if (order >= 10) | |
212 | return NULL; | |
213 | ||
c1b1a5f1 DM |
214 | nid = dev->archdata.numa_node; |
215 | page = alloc_pages_node(nid, gfp, order); | |
216 | if (unlikely(!page)) | |
1da177e4 | 217 | return NULL; |
c1b1a5f1 DM |
218 | |
219 | first_page = (unsigned long) page_address(page); | |
1da177e4 LT |
220 | memset((char *)first_page, 0, PAGE_SIZE << order); |
221 | ||
ad7ad57c | 222 | iommu = dev->archdata.iommu; |
1da177e4 | 223 | |
d284142c | 224 | iopte = alloc_npages(dev, iommu, size >> IO_PAGE_SHIFT); |
688cb30b DM |
225 | |
226 | if (unlikely(iopte == NULL)) { | |
1da177e4 LT |
227 | free_pages(first_page, order); |
228 | return NULL; | |
229 | } | |
230 | ||
bb620c3d | 231 | *dma_addrp = (iommu->tbl.table_map_base + |
1da177e4 LT |
232 | ((iopte - iommu->page_table) << IO_PAGE_SHIFT)); |
233 | ret = (void *) first_page; | |
234 | npages = size >> IO_PAGE_SHIFT; | |
1da177e4 LT |
235 | first_page = __pa(first_page); |
236 | while (npages--) { | |
688cb30b | 237 | iopte_val(*iopte) = (IOPTE_CONSISTENT(0UL) | |
1da177e4 LT |
238 | IOPTE_WRITE | |
239 | (first_page & IOPTE_PAGE)); | |
240 | iopte++; | |
241 | first_page += IO_PAGE_SIZE; | |
242 | } | |
243 | ||
1da177e4 LT |
244 | return ret; |
245 | } | |
246 | ||
ad7ad57c | 247 | static void dma_4u_free_coherent(struct device *dev, size_t size, |
c416258a | 248 | void *cpu, dma_addr_t dvma, |
00085f1e | 249 | unsigned long attrs) |
1da177e4 | 250 | { |
16ce82d8 | 251 | struct iommu *iommu; |
bb620c3d | 252 | unsigned long order, npages; |
1da177e4 LT |
253 | |
254 | npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT; | |
ad7ad57c | 255 | iommu = dev->archdata.iommu; |
1da177e4 | 256 | |
d618382b | 257 | iommu_tbl_range_free(&iommu->tbl, dvma, npages, IOMMU_ERROR_CODE); |
1da177e4 LT |
258 | |
259 | order = get_order(size); | |
260 | if (order < 10) | |
261 | free_pages((unsigned long)cpu, order); | |
262 | } | |
263 | ||
797a7568 FT |
264 | static dma_addr_t dma_4u_map_page(struct device *dev, struct page *page, |
265 | unsigned long offset, size_t sz, | |
bc0a14f1 | 266 | enum dma_data_direction direction, |
00085f1e | 267 | unsigned long attrs) |
1da177e4 | 268 | { |
16ce82d8 DM |
269 | struct iommu *iommu; |
270 | struct strbuf *strbuf; | |
1da177e4 LT |
271 | iopte_t *base; |
272 | unsigned long flags, npages, oaddr; | |
273 | unsigned long i, base_paddr, ctx; | |
274 | u32 bus_addr, ret; | |
275 | unsigned long iopte_protection; | |
276 | ||
ad7ad57c DM |
277 | iommu = dev->archdata.iommu; |
278 | strbuf = dev->archdata.stc; | |
1da177e4 | 279 | |
ad7ad57c | 280 | if (unlikely(direction == DMA_NONE)) |
688cb30b | 281 | goto bad_no_ctx; |
1da177e4 | 282 | |
797a7568 | 283 | oaddr = (unsigned long)(page_address(page) + offset); |
1da177e4 LT |
284 | npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK); |
285 | npages >>= IO_PAGE_SHIFT; | |
286 | ||
c12f048f | 287 | base = alloc_npages(dev, iommu, npages); |
bb620c3d | 288 | spin_lock_irqsave(&iommu->lock, flags); |
688cb30b DM |
289 | ctx = 0; |
290 | if (iommu->iommu_ctxflush) | |
291 | ctx = iommu_alloc_ctx(iommu); | |
292 | spin_unlock_irqrestore(&iommu->lock, flags); | |
1da177e4 | 293 | |
688cb30b | 294 | if (unlikely(!base)) |
1da177e4 | 295 | goto bad; |
688cb30b | 296 | |
bb620c3d | 297 | bus_addr = (iommu->tbl.table_map_base + |
1da177e4 LT |
298 | ((base - iommu->page_table) << IO_PAGE_SHIFT)); |
299 | ret = bus_addr | (oaddr & ~IO_PAGE_MASK); | |
300 | base_paddr = __pa(oaddr & IO_PAGE_MASK); | |
1da177e4 LT |
301 | if (strbuf->strbuf_enabled) |
302 | iopte_protection = IOPTE_STREAMING(ctx); | |
303 | else | |
304 | iopte_protection = IOPTE_CONSISTENT(ctx); | |
ad7ad57c | 305 | if (direction != DMA_TO_DEVICE) |
1da177e4 LT |
306 | iopte_protection |= IOPTE_WRITE; |
307 | ||
308 | for (i = 0; i < npages; i++, base++, base_paddr += IO_PAGE_SIZE) | |
309 | iopte_val(*base) = iopte_protection | base_paddr; | |
310 | ||
1da177e4 LT |
311 | return ret; |
312 | ||
313 | bad: | |
688cb30b DM |
314 | iommu_free_ctx(iommu, ctx); |
315 | bad_no_ctx: | |
316 | if (printk_ratelimit()) | |
317 | WARN_ON(1); | |
ceaf481c | 318 | return SPARC_MAPPING_ERROR; |
1da177e4 LT |
319 | } |
320 | ||
ad7ad57c DM |
321 | static void strbuf_flush(struct strbuf *strbuf, struct iommu *iommu, |
322 | u32 vaddr, unsigned long ctx, unsigned long npages, | |
323 | enum dma_data_direction direction) | |
4dbc30fb DM |
324 | { |
325 | int limit; | |
326 | ||
4dbc30fb DM |
327 | if (strbuf->strbuf_ctxflush && |
328 | iommu->iommu_ctxflush) { | |
329 | unsigned long matchreg, flushreg; | |
7c963ad1 | 330 | u64 val; |
4dbc30fb DM |
331 | |
332 | flushreg = strbuf->strbuf_ctxflush; | |
ad7ad57c | 333 | matchreg = STC_CTXMATCH_ADDR(strbuf, ctx); |
4dbc30fb | 334 | |
ad7ad57c DM |
335 | iommu_write(flushreg, ctx); |
336 | val = iommu_read(matchreg); | |
88314ee7 DM |
337 | val &= 0xffff; |
338 | if (!val) | |
7c963ad1 DM |
339 | goto do_flush_sync; |
340 | ||
7c963ad1 DM |
341 | while (val) { |
342 | if (val & 0x1) | |
ad7ad57c | 343 | iommu_write(flushreg, ctx); |
7c963ad1 | 344 | val >>= 1; |
a228dfd5 | 345 | } |
ad7ad57c | 346 | val = iommu_read(matchreg); |
7c963ad1 | 347 | if (unlikely(val)) { |
ad7ad57c | 348 | printk(KERN_WARNING "strbuf_flush: ctx flush " |
90181136 | 349 | "timeout matchreg[%llx] ctx[%lx]\n", |
7c963ad1 DM |
350 | val, ctx); |
351 | goto do_page_flush; | |
352 | } | |
4dbc30fb DM |
353 | } else { |
354 | unsigned long i; | |
355 | ||
7c963ad1 | 356 | do_page_flush: |
4dbc30fb | 357 | for (i = 0; i < npages; i++, vaddr += IO_PAGE_SIZE) |
ad7ad57c | 358 | iommu_write(strbuf->strbuf_pflush, vaddr); |
4dbc30fb DM |
359 | } |
360 | ||
7c963ad1 DM |
361 | do_flush_sync: |
362 | /* If the device could not have possibly put dirty data into | |
363 | * the streaming cache, no flush-flag synchronization needs | |
364 | * to be performed. | |
365 | */ | |
ad7ad57c | 366 | if (direction == DMA_TO_DEVICE) |
7c963ad1 DM |
367 | return; |
368 | ||
ad7ad57c DM |
369 | STC_FLUSHFLAG_INIT(strbuf); |
370 | iommu_write(strbuf->strbuf_fsync, strbuf->strbuf_flushflag_pa); | |
371 | (void) iommu_read(iommu->write_complete_reg); | |
4dbc30fb | 372 | |
a228dfd5 | 373 | limit = 100000; |
ad7ad57c | 374 | while (!STC_FLUSHFLAG_SET(strbuf)) { |
4dbc30fb DM |
375 | limit--; |
376 | if (!limit) | |
377 | break; | |
a228dfd5 | 378 | udelay(1); |
4f07118f | 379 | rmb(); |
4dbc30fb DM |
380 | } |
381 | if (!limit) | |
ad7ad57c | 382 | printk(KERN_WARNING "strbuf_flush: flushflag timeout " |
4dbc30fb DM |
383 | "vaddr[%08x] ctx[%lx] npages[%ld]\n", |
384 | vaddr, ctx, npages); | |
385 | } | |
386 | ||
797a7568 | 387 | static void dma_4u_unmap_page(struct device *dev, dma_addr_t bus_addr, |
bc0a14f1 | 388 | size_t sz, enum dma_data_direction direction, |
00085f1e | 389 | unsigned long attrs) |
1da177e4 | 390 | { |
16ce82d8 DM |
391 | struct iommu *iommu; |
392 | struct strbuf *strbuf; | |
1da177e4 | 393 | iopte_t *base; |
688cb30b | 394 | unsigned long flags, npages, ctx, i; |
1da177e4 | 395 | |
ad7ad57c | 396 | if (unlikely(direction == DMA_NONE)) { |
688cb30b DM |
397 | if (printk_ratelimit()) |
398 | WARN_ON(1); | |
399 | return; | |
400 | } | |
1da177e4 | 401 | |
ad7ad57c DM |
402 | iommu = dev->archdata.iommu; |
403 | strbuf = dev->archdata.stc; | |
1da177e4 LT |
404 | |
405 | npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK); | |
406 | npages >>= IO_PAGE_SHIFT; | |
407 | base = iommu->page_table + | |
bb620c3d | 408 | ((bus_addr - iommu->tbl.table_map_base) >> IO_PAGE_SHIFT); |
1da177e4 LT |
409 | bus_addr &= IO_PAGE_MASK; |
410 | ||
411 | spin_lock_irqsave(&iommu->lock, flags); | |
412 | ||
413 | /* Record the context, if any. */ | |
414 | ctx = 0; | |
415 | if (iommu->iommu_ctxflush) | |
416 | ctx = (iopte_val(*base) & IOPTE_CONTEXT) >> 47UL; | |
417 | ||
418 | /* Step 1: Kick data out of streaming buffers if necessary. */ | |
68bbc28f | 419 | if (strbuf->strbuf_enabled && !(attrs & DMA_ATTR_SKIP_CPU_SYNC)) |
ad7ad57c DM |
420 | strbuf_flush(strbuf, iommu, bus_addr, ctx, |
421 | npages, direction); | |
1da177e4 | 422 | |
688cb30b DM |
423 | /* Step 2: Clear out TSB entries. */ |
424 | for (i = 0; i < npages; i++) | |
425 | iopte_make_dummy(iommu, base + i); | |
1da177e4 | 426 | |
7c963ad1 | 427 | iommu_free_ctx(iommu, ctx); |
c12f048f | 428 | spin_unlock_irqrestore(&iommu->lock, flags); |
bb620c3d | 429 | |
d618382b | 430 | iommu_tbl_range_free(&iommu->tbl, bus_addr, npages, IOMMU_ERROR_CODE); |
1da177e4 LT |
431 | } |
432 | ||
ad7ad57c | 433 | static int dma_4u_map_sg(struct device *dev, struct scatterlist *sglist, |
bc0a14f1 | 434 | int nelems, enum dma_data_direction direction, |
00085f1e | 435 | unsigned long attrs) |
1da177e4 | 436 | { |
13fa14e1 DM |
437 | struct scatterlist *s, *outs, *segstart; |
438 | unsigned long flags, handle, prot, ctx; | |
439 | dma_addr_t dma_next = 0, dma_addr; | |
440 | unsigned int max_seg_size; | |
f0880257 | 441 | unsigned long seg_boundary_size; |
13fa14e1 | 442 | int outcount, incount, i; |
16ce82d8 | 443 | struct strbuf *strbuf; |
38192d52 | 444 | struct iommu *iommu; |
f0880257 | 445 | unsigned long base_shift; |
13fa14e1 DM |
446 | |
447 | BUG_ON(direction == DMA_NONE); | |
1da177e4 | 448 | |
ad7ad57c DM |
449 | iommu = dev->archdata.iommu; |
450 | strbuf = dev->archdata.stc; | |
13fa14e1 DM |
451 | if (nelems == 0 || !iommu) |
452 | return 0; | |
1da177e4 LT |
453 | |
454 | spin_lock_irqsave(&iommu->lock, flags); | |
455 | ||
688cb30b DM |
456 | ctx = 0; |
457 | if (iommu->iommu_ctxflush) | |
458 | ctx = iommu_alloc_ctx(iommu); | |
459 | ||
1da177e4 | 460 | if (strbuf->strbuf_enabled) |
13fa14e1 | 461 | prot = IOPTE_STREAMING(ctx); |
1da177e4 | 462 | else |
13fa14e1 | 463 | prot = IOPTE_CONSISTENT(ctx); |
ad7ad57c | 464 | if (direction != DMA_TO_DEVICE) |
13fa14e1 DM |
465 | prot |= IOPTE_WRITE; |
466 | ||
467 | outs = s = segstart = &sglist[0]; | |
468 | outcount = 1; | |
469 | incount = nelems; | |
470 | handle = 0; | |
471 | ||
472 | /* Init first segment length for backout at failure */ | |
473 | outs->dma_length = 0; | |
474 | ||
475 | max_seg_size = dma_get_max_seg_size(dev); | |
f0880257 FT |
476 | seg_boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, |
477 | IO_PAGE_SIZE) >> IO_PAGE_SHIFT; | |
bb620c3d | 478 | base_shift = iommu->tbl.table_map_base >> IO_PAGE_SHIFT; |
13fa14e1 | 479 | for_each_sg(sglist, s, nelems, i) { |
f0880257 | 480 | unsigned long paddr, npages, entry, out_entry = 0, slen; |
13fa14e1 DM |
481 | iopte_t *base; |
482 | ||
483 | slen = s->length; | |
484 | /* Sanity check */ | |
485 | if (slen == 0) { | |
486 | dma_next = 0; | |
487 | continue; | |
488 | } | |
489 | /* Allocate iommu entries for that segment */ | |
490 | paddr = (unsigned long) SG_ENT_PHYS_ADDRESS(s); | |
0fcff28f | 491 | npages = iommu_num_pages(paddr, slen, IO_PAGE_SIZE); |
bb620c3d SV |
492 | entry = iommu_tbl_range_alloc(dev, &iommu->tbl, npages, |
493 | &handle, (unsigned long)(-1), 0); | |
13fa14e1 DM |
494 | |
495 | /* Handle failure */ | |
d618382b | 496 | if (unlikely(entry == IOMMU_ERROR_CODE)) { |
13fa14e1 DM |
497 | if (printk_ratelimit()) |
498 | printk(KERN_INFO "iommu_alloc failed, iommu %p paddr %lx" | |
499 | " npages %lx\n", iommu, paddr, npages); | |
500 | goto iommu_map_failed; | |
501 | } | |
688cb30b | 502 | |
13fa14e1 | 503 | base = iommu->page_table + entry; |
1da177e4 | 504 | |
13fa14e1 | 505 | /* Convert entry to a dma_addr_t */ |
bb620c3d | 506 | dma_addr = iommu->tbl.table_map_base + |
13fa14e1 DM |
507 | (entry << IO_PAGE_SHIFT); |
508 | dma_addr |= (s->offset & ~IO_PAGE_MASK); | |
38192d52 | 509 | |
13fa14e1 | 510 | /* Insert into HW table */ |
38192d52 | 511 | paddr &= IO_PAGE_MASK; |
13fa14e1 DM |
512 | while (npages--) { |
513 | iopte_val(*base) = prot | paddr; | |
38192d52 DM |
514 | base++; |
515 | paddr += IO_PAGE_SIZE; | |
38192d52 | 516 | } |
13fa14e1 DM |
517 | |
518 | /* If we are in an open segment, try merging */ | |
519 | if (segstart != s) { | |
520 | /* We cannot merge if: | |
521 | * - allocated dma_addr isn't contiguous to previous allocation | |
522 | */ | |
523 | if ((dma_addr != dma_next) || | |
f0880257 FT |
524 | (outs->dma_length + s->length > max_seg_size) || |
525 | (is_span_boundary(out_entry, base_shift, | |
526 | seg_boundary_size, outs, s))) { | |
13fa14e1 DM |
527 | /* Can't merge: create a new segment */ |
528 | segstart = s; | |
529 | outcount++; | |
530 | outs = sg_next(outs); | |
531 | } else { | |
532 | outs->dma_length += s->length; | |
533 | } | |
534 | } | |
535 | ||
536 | if (segstart == s) { | |
537 | /* This is a new segment, fill entries */ | |
538 | outs->dma_address = dma_addr; | |
539 | outs->dma_length = slen; | |
f0880257 | 540 | out_entry = entry; |
13fa14e1 DM |
541 | } |
542 | ||
543 | /* Calculate next page pointer for contiguous check */ | |
544 | dma_next = dma_addr + slen; | |
38192d52 DM |
545 | } |
546 | ||
13fa14e1 DM |
547 | spin_unlock_irqrestore(&iommu->lock, flags); |
548 | ||
549 | if (outcount < incount) { | |
550 | outs = sg_next(outs); | |
ceaf481c | 551 | outs->dma_address = SPARC_MAPPING_ERROR; |
13fa14e1 DM |
552 | outs->dma_length = 0; |
553 | } | |
554 | ||
555 | return outcount; | |
556 | ||
557 | iommu_map_failed: | |
558 | for_each_sg(sglist, s, nelems, i) { | |
559 | if (s->dma_length != 0) { | |
6c830fef | 560 | unsigned long vaddr, npages, entry, j; |
13fa14e1 DM |
561 | iopte_t *base; |
562 | ||
563 | vaddr = s->dma_address & IO_PAGE_MASK; | |
0fcff28f JR |
564 | npages = iommu_num_pages(s->dma_address, s->dma_length, |
565 | IO_PAGE_SIZE); | |
13fa14e1 | 566 | |
bb620c3d | 567 | entry = (vaddr - iommu->tbl.table_map_base) |
13fa14e1 DM |
568 | >> IO_PAGE_SHIFT; |
569 | base = iommu->page_table + entry; | |
570 | ||
6c830fef DM |
571 | for (j = 0; j < npages; j++) |
572 | iopte_make_dummy(iommu, base + j); | |
13fa14e1 | 573 | |
bb620c3d | 574 | iommu_tbl_range_free(&iommu->tbl, vaddr, npages, |
d618382b | 575 | IOMMU_ERROR_CODE); |
bb620c3d | 576 | |
ceaf481c | 577 | s->dma_address = SPARC_MAPPING_ERROR; |
13fa14e1 DM |
578 | s->dma_length = 0; |
579 | } | |
580 | if (s == outs) | |
581 | break; | |
582 | } | |
583 | spin_unlock_irqrestore(&iommu->lock, flags); | |
1da177e4 | 584 | |
688cb30b | 585 | return 0; |
1da177e4 LT |
586 | } |
587 | ||
13fa14e1 DM |
588 | /* If contexts are being used, they are the same in all of the mappings |
589 | * we make for a particular SG. | |
590 | */ | |
c12f048f | 591 | static unsigned long fetch_sg_ctx(struct iommu *iommu, struct scatterlist *sg) |
13fa14e1 DM |
592 | { |
593 | unsigned long ctx = 0; | |
594 | ||
595 | if (iommu->iommu_ctxflush) { | |
596 | iopte_t *base; | |
597 | u32 bus_addr; | |
bb620c3d | 598 | struct iommu_map_table *tbl = &iommu->tbl; |
13fa14e1 DM |
599 | |
600 | bus_addr = sg->dma_address & IO_PAGE_MASK; | |
601 | base = iommu->page_table + | |
bb620c3d | 602 | ((bus_addr - tbl->table_map_base) >> IO_PAGE_SHIFT); |
13fa14e1 DM |
603 | |
604 | ctx = (iopte_val(*base) & IOPTE_CONTEXT) >> 47UL; | |
605 | } | |
606 | return ctx; | |
607 | } | |
608 | ||
ad7ad57c | 609 | static void dma_4u_unmap_sg(struct device *dev, struct scatterlist *sglist, |
bc0a14f1 | 610 | int nelems, enum dma_data_direction direction, |
00085f1e | 611 | unsigned long attrs) |
1da177e4 | 612 | { |
13fa14e1 DM |
613 | unsigned long flags, ctx; |
614 | struct scatterlist *sg; | |
16ce82d8 | 615 | struct strbuf *strbuf; |
38192d52 | 616 | struct iommu *iommu; |
1da177e4 | 617 | |
13fa14e1 | 618 | BUG_ON(direction == DMA_NONE); |
1da177e4 | 619 | |
ad7ad57c DM |
620 | iommu = dev->archdata.iommu; |
621 | strbuf = dev->archdata.stc; | |
622 | ||
13fa14e1 | 623 | ctx = fetch_sg_ctx(iommu, sglist); |
1da177e4 | 624 | |
13fa14e1 | 625 | spin_lock_irqsave(&iommu->lock, flags); |
1da177e4 | 626 | |
13fa14e1 DM |
627 | sg = sglist; |
628 | while (nelems--) { | |
629 | dma_addr_t dma_handle = sg->dma_address; | |
630 | unsigned int len = sg->dma_length; | |
631 | unsigned long npages, entry; | |
632 | iopte_t *base; | |
633 | int i; | |
1da177e4 | 634 | |
13fa14e1 DM |
635 | if (!len) |
636 | break; | |
0fcff28f | 637 | npages = iommu_num_pages(dma_handle, len, IO_PAGE_SIZE); |
1da177e4 | 638 | |
bb620c3d | 639 | entry = ((dma_handle - iommu->tbl.table_map_base) |
13fa14e1 DM |
640 | >> IO_PAGE_SHIFT); |
641 | base = iommu->page_table + entry; | |
1da177e4 | 642 | |
13fa14e1 | 643 | dma_handle &= IO_PAGE_MASK; |
68bbc28f | 644 | if (strbuf->strbuf_enabled && !(attrs & DMA_ATTR_SKIP_CPU_SYNC)) |
13fa14e1 DM |
645 | strbuf_flush(strbuf, iommu, dma_handle, ctx, |
646 | npages, direction); | |
1da177e4 | 647 | |
13fa14e1 DM |
648 | for (i = 0; i < npages; i++) |
649 | iopte_make_dummy(iommu, base + i); | |
1da177e4 | 650 | |
bb620c3d | 651 | iommu_tbl_range_free(&iommu->tbl, dma_handle, npages, |
d618382b | 652 | IOMMU_ERROR_CODE); |
13fa14e1 DM |
653 | sg = sg_next(sg); |
654 | } | |
1da177e4 | 655 | |
7c963ad1 DM |
656 | iommu_free_ctx(iommu, ctx); |
657 | ||
1da177e4 LT |
658 | spin_unlock_irqrestore(&iommu->lock, flags); |
659 | } | |
660 | ||
ad7ad57c DM |
661 | static void dma_4u_sync_single_for_cpu(struct device *dev, |
662 | dma_addr_t bus_addr, size_t sz, | |
663 | enum dma_data_direction direction) | |
1da177e4 | 664 | { |
16ce82d8 DM |
665 | struct iommu *iommu; |
666 | struct strbuf *strbuf; | |
1da177e4 LT |
667 | unsigned long flags, ctx, npages; |
668 | ||
ad7ad57c DM |
669 | iommu = dev->archdata.iommu; |
670 | strbuf = dev->archdata.stc; | |
1da177e4 LT |
671 | |
672 | if (!strbuf->strbuf_enabled) | |
673 | return; | |
674 | ||
675 | spin_lock_irqsave(&iommu->lock, flags); | |
676 | ||
677 | npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK); | |
678 | npages >>= IO_PAGE_SHIFT; | |
679 | bus_addr &= IO_PAGE_MASK; | |
680 | ||
681 | /* Step 1: Record the context, if any. */ | |
682 | ctx = 0; | |
683 | if (iommu->iommu_ctxflush && | |
684 | strbuf->strbuf_ctxflush) { | |
685 | iopte_t *iopte; | |
bb620c3d | 686 | struct iommu_map_table *tbl = &iommu->tbl; |
1da177e4 LT |
687 | |
688 | iopte = iommu->page_table + | |
bb620c3d | 689 | ((bus_addr - tbl->table_map_base)>>IO_PAGE_SHIFT); |
1da177e4 LT |
690 | ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL; |
691 | } | |
692 | ||
693 | /* Step 2: Kick data out of streaming buffers. */ | |
ad7ad57c | 694 | strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction); |
1da177e4 LT |
695 | |
696 | spin_unlock_irqrestore(&iommu->lock, flags); | |
697 | } | |
698 | ||
ad7ad57c DM |
699 | static void dma_4u_sync_sg_for_cpu(struct device *dev, |
700 | struct scatterlist *sglist, int nelems, | |
701 | enum dma_data_direction direction) | |
1da177e4 | 702 | { |
16ce82d8 DM |
703 | struct iommu *iommu; |
704 | struct strbuf *strbuf; | |
4dbc30fb | 705 | unsigned long flags, ctx, npages, i; |
2c941a20 | 706 | struct scatterlist *sg, *sgprv; |
4dbc30fb | 707 | u32 bus_addr; |
1da177e4 | 708 | |
ad7ad57c DM |
709 | iommu = dev->archdata.iommu; |
710 | strbuf = dev->archdata.stc; | |
1da177e4 LT |
711 | |
712 | if (!strbuf->strbuf_enabled) | |
713 | return; | |
714 | ||
715 | spin_lock_irqsave(&iommu->lock, flags); | |
716 | ||
717 | /* Step 1: Record the context, if any. */ | |
718 | ctx = 0; | |
719 | if (iommu->iommu_ctxflush && | |
720 | strbuf->strbuf_ctxflush) { | |
721 | iopte_t *iopte; | |
bb620c3d | 722 | struct iommu_map_table *tbl = &iommu->tbl; |
1da177e4 | 723 | |
bb620c3d SV |
724 | iopte = iommu->page_table + ((sglist[0].dma_address - |
725 | tbl->table_map_base) >> IO_PAGE_SHIFT); | |
1da177e4 LT |
726 | ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL; |
727 | } | |
728 | ||
729 | /* Step 2: Kick data out of streaming buffers. */ | |
4dbc30fb | 730 | bus_addr = sglist[0].dma_address & IO_PAGE_MASK; |
2c941a20 JA |
731 | sgprv = NULL; |
732 | for_each_sg(sglist, sg, nelems, i) { | |
733 | if (sg->dma_length == 0) | |
4dbc30fb | 734 | break; |
2c941a20 JA |
735 | sgprv = sg; |
736 | } | |
737 | ||
738 | npages = (IO_PAGE_ALIGN(sgprv->dma_address + sgprv->dma_length) | |
4dbc30fb | 739 | - bus_addr) >> IO_PAGE_SHIFT; |
ad7ad57c | 740 | strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction); |
1da177e4 LT |
741 | |
742 | spin_unlock_irqrestore(&iommu->lock, flags); | |
743 | } | |
744 | ||
ceaf481c CH |
745 | static int dma_4u_mapping_error(struct device *dev, dma_addr_t dma_addr) |
746 | { | |
747 | return dma_addr == SPARC_MAPPING_ERROR; | |
748 | } | |
749 | ||
b02c2b0b CH |
750 | static int dma_4u_supported(struct device *dev, u64 device_mask) |
751 | { | |
752 | struct iommu *iommu = dev->archdata.iommu; | |
753 | ||
754 | if (device_mask > DMA_BIT_MASK(32)) | |
755 | return 0; | |
756 | if ((device_mask & iommu->dma_addr_mask) == iommu->dma_addr_mask) | |
757 | return 1; | |
758 | #ifdef CONFIG_PCI | |
759 | if (dev_is_pci(dev)) | |
760 | return pci64_dma_supported(to_pci_dev(dev), device_mask); | |
761 | #endif | |
762 | return 0; | |
763 | } | |
764 | ||
5299709d | 765 | static const struct dma_map_ops sun4u_dma_ops = { |
c416258a AP |
766 | .alloc = dma_4u_alloc_coherent, |
767 | .free = dma_4u_free_coherent, | |
797a7568 FT |
768 | .map_page = dma_4u_map_page, |
769 | .unmap_page = dma_4u_unmap_page, | |
ad7ad57c DM |
770 | .map_sg = dma_4u_map_sg, |
771 | .unmap_sg = dma_4u_unmap_sg, | |
772 | .sync_single_for_cpu = dma_4u_sync_single_for_cpu, | |
773 | .sync_sg_for_cpu = dma_4u_sync_sg_for_cpu, | |
b02c2b0b | 774 | .dma_supported = dma_4u_supported, |
ceaf481c | 775 | .mapping_error = dma_4u_mapping_error, |
8f6a93a1 DM |
776 | }; |
777 | ||
5299709d | 778 | const struct dma_map_ops *dma_ops = &sun4u_dma_ops; |
ad7ad57c | 779 | EXPORT_SYMBOL(dma_ops); |