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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1da177e4 LT |
2 | /* smp.c: Sparc SMP support. |
3 | * | |
4 | * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu) | |
5 | * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz) | |
6 | * Copyright (C) 2004 Keith M Wesolowski (wesolows@foobazco.org) | |
7 | */ | |
8 | ||
9 | #include <asm/head.h> | |
10 | ||
11 | #include <linux/kernel.h> | |
12 | #include <linux/sched.h> | |
13 | #include <linux/threads.h> | |
14 | #include <linux/smp.h> | |
1da177e4 LT |
15 | #include <linux/interrupt.h> |
16 | #include <linux/kernel_stat.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/spinlock.h> | |
19 | #include <linux/mm.h> | |
20 | #include <linux/fs.h> | |
21 | #include <linux/seq_file.h> | |
22 | #include <linux/cache.h> | |
23 | #include <linux/delay.h> | |
d3091298 | 24 | #include <linux/profile.h> |
f9fd3488 | 25 | #include <linux/cpu.h> |
1da177e4 LT |
26 | |
27 | #include <asm/ptrace.h> | |
60063497 | 28 | #include <linux/atomic.h> |
1da177e4 LT |
29 | |
30 | #include <asm/irq.h> | |
31 | #include <asm/page.h> | |
32 | #include <asm/pgalloc.h> | |
33 | #include <asm/pgtable.h> | |
34 | #include <asm/oplib.h> | |
35 | #include <asm/cacheflush.h> | |
36 | #include <asm/tlbflush.h> | |
37 | #include <asm/cpudata.h> | |
f9fd3488 | 38 | #include <asm/timer.h> |
8401707f | 39 | #include <asm/leon.h> |
1da177e4 | 40 | |
f9fd3488 | 41 | #include "kernel.h" |
32231a66 AV |
42 | #include "irq.h" |
43 | ||
2066aadd | 44 | volatile unsigned long cpu_callin_map[NR_CPUS] = {0,}; |
1da177e4 | 45 | |
a54123e2 | 46 | cpumask_t smp_commenced_mask = CPU_MASK_NONE; |
1da177e4 | 47 | |
4ba22b16 SR |
48 | const struct sparc32_ipi_ops *sparc32_ipi_ops; |
49 | ||
1da177e4 LT |
50 | /* The only guaranteed locking primitive available on all Sparc |
51 | * processors is 'ldstub [%reg + immediate], %dest_reg' which atomically | |
52 | * places the current byte at the effective address into dest_reg and | |
53 | * places 0xff there afterwards. Pretty lame locking primitive | |
54 | * compared to the Alpha and the Intel no? Most Sparcs have 'swap' | |
55 | * instruction which is much better... | |
56 | */ | |
57 | ||
2066aadd | 58 | void smp_store_cpu_info(int id) |
1da177e4 LT |
59 | { |
60 | int cpu_node; | |
f486b3dc | 61 | int mid; |
1da177e4 LT |
62 | |
63 | cpu_data(id).udelay_val = loops_per_jiffy; | |
64 | ||
65 | cpu_find_by_mid(id, &cpu_node); | |
66 | cpu_data(id).clock_tick = prom_getintdefault(cpu_node, | |
67 | "clock-frequency", 0); | |
68 | cpu_data(id).prom_node = cpu_node; | |
f486b3dc | 69 | mid = cpu_get_hwmid(cpu_node); |
650fb838 | 70 | |
f486b3dc | 71 | if (mid < 0) { |
551d57ff | 72 | printk(KERN_NOTICE "No MID found for CPU%d at node 0x%08x", id, cpu_node); |
f486b3dc SR |
73 | mid = 0; |
74 | } | |
75 | cpu_data(id).mid = mid; | |
1da177e4 LT |
76 | } |
77 | ||
78 | void __init smp_cpus_done(unsigned int max_cpus) | |
79 | { | |
a54123e2 | 80 | unsigned long bogosum = 0; |
ec7c14bd | 81 | int cpu, num = 0; |
a54123e2 | 82 | |
ec7c14bd RR |
83 | for_each_online_cpu(cpu) { |
84 | num++; | |
85 | bogosum += cpu_data(cpu).udelay_val; | |
86 | } | |
a54123e2 BB |
87 | |
88 | printk("Total of %d processors activated (%lu.%02lu BogoMIPS).\n", | |
89 | num, bogosum/(500000/HZ), | |
90 | (bogosum/(5000/HZ))%100); | |
91 | ||
8b3c848c | 92 | switch(sparc_cpu_model) { |
8b3c848c RB |
93 | case sun4m: |
94 | smp4m_smp_done(); | |
95 | break; | |
96 | case sun4d: | |
97 | smp4d_smp_done(); | |
98 | break; | |
8401707f KE |
99 | case sparc_leon: |
100 | leon_smp_done(); | |
101 | break; | |
8b3c848c RB |
102 | case sun4e: |
103 | printk("SUN4E\n"); | |
104 | BUG(); | |
105 | break; | |
106 | case sun4u: | |
107 | printk("SUN4U\n"); | |
108 | BUG(); | |
109 | break; | |
110 | default: | |
111 | printk("UNKNOWN!\n"); | |
112 | BUG(); | |
113 | break; | |
6cb79b3f | 114 | } |
1da177e4 LT |
115 | } |
116 | ||
117 | void cpu_panic(void) | |
118 | { | |
119 | printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id()); | |
120 | panic("SMP bolixed\n"); | |
121 | } | |
122 | ||
2066aadd | 123 | struct linux_prom_registers smp_penguin_ctable = { 0 }; |
1da177e4 | 124 | |
1da177e4 LT |
125 | void smp_send_reschedule(int cpu) |
126 | { | |
d6d04819 DH |
127 | /* |
128 | * CPU model dependent way of implementing IPI generation targeting | |
129 | * a single CPU. The trap handler needs only to do trap entry/return | |
130 | * to call schedule. | |
131 | */ | |
4ba22b16 | 132 | sparc32_ipi_ops->resched(cpu); |
1da177e4 LT |
133 | } |
134 | ||
135 | void smp_send_stop(void) | |
136 | { | |
137 | } | |
138 | ||
d6d04819 DH |
139 | void arch_send_call_function_single_ipi(int cpu) |
140 | { | |
141 | /* trigger one IPI single call on one CPU */ | |
4ba22b16 | 142 | sparc32_ipi_ops->single(cpu); |
d6d04819 DH |
143 | } |
144 | ||
145 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) | |
146 | { | |
147 | int cpu; | |
148 | ||
149 | /* trigger IPI mask call on each CPU */ | |
150 | for_each_cpu(cpu, mask) | |
4ba22b16 | 151 | sparc32_ipi_ops->mask_one(cpu); |
d6d04819 DH |
152 | } |
153 | ||
154 | void smp_resched_interrupt(void) | |
155 | { | |
90d3ac15 DM |
156 | irq_enter(); |
157 | scheduler_ipi(); | |
d6d04819 | 158 | local_cpu_data().irq_resched_count++; |
90d3ac15 DM |
159 | irq_exit(); |
160 | /* re-schedule routine called by interrupt return code. */ | |
d6d04819 DH |
161 | } |
162 | ||
163 | void smp_call_function_single_interrupt(void) | |
164 | { | |
165 | irq_enter(); | |
166 | generic_smp_call_function_single_interrupt(); | |
167 | local_cpu_data().irq_call_count++; | |
168 | irq_exit(); | |
169 | } | |
170 | ||
171 | void smp_call_function_interrupt(void) | |
172 | { | |
173 | irq_enter(); | |
174 | generic_smp_call_function_interrupt(); | |
175 | local_cpu_data().irq_call_count++; | |
176 | irq_exit(); | |
177 | } | |
178 | ||
1da177e4 LT |
179 | int setup_profiling_timer(unsigned int multiplier) |
180 | { | |
62f08283 | 181 | return -EINVAL; |
1da177e4 LT |
182 | } |
183 | ||
a54123e2 | 184 | void __init smp_prepare_cpus(unsigned int max_cpus) |
1da177e4 | 185 | { |
7202fb49 | 186 | int i, cpuid, extra; |
a54123e2 | 187 | |
a54123e2 BB |
188 | printk("Entering SMP Mode...\n"); |
189 | ||
a54123e2 BB |
190 | extra = 0; |
191 | for (i = 0; !cpu_find_by_instance(i, NULL, &cpuid); i++) { | |
7202fb49 | 192 | if (cpuid >= NR_CPUS) |
a54123e2 BB |
193 | extra++; |
194 | } | |
7202fb49 BB |
195 | /* i = number of cpus */ |
196 | if (extra && max_cpus > i - extra) | |
a54123e2 BB |
197 | printk("Warning: NR_CPUS is too low to start all cpus\n"); |
198 | ||
199 | smp_store_cpu_info(boot_cpu_id); | |
200 | ||
8b3c848c | 201 | switch(sparc_cpu_model) { |
8b3c848c RB |
202 | case sun4m: |
203 | smp4m_boot_cpus(); | |
204 | break; | |
205 | case sun4d: | |
206 | smp4d_boot_cpus(); | |
207 | break; | |
8401707f KE |
208 | case sparc_leon: |
209 | leon_boot_cpus(); | |
210 | break; | |
8b3c848c RB |
211 | case sun4e: |
212 | printk("SUN4E\n"); | |
213 | BUG(); | |
214 | break; | |
215 | case sun4u: | |
216 | printk("SUN4U\n"); | |
217 | BUG(); | |
218 | break; | |
219 | default: | |
220 | printk("UNKNOWN!\n"); | |
221 | BUG(); | |
222 | break; | |
6cb79b3f | 223 | } |
1da177e4 LT |
224 | } |
225 | ||
7202fb49 BB |
226 | /* Set this up early so that things like the scheduler can init |
227 | * properly. We use the same cpu mask for both the present and | |
228 | * possible cpu map. | |
229 | */ | |
230 | void __init smp_setup_cpu_possible_map(void) | |
231 | { | |
232 | int instance, mid; | |
233 | ||
234 | instance = 0; | |
235 | while (!cpu_find_by_instance(instance, NULL, &mid)) { | |
236 | if (mid < NR_CPUS) { | |
fe73971c RR |
237 | set_cpu_possible(mid, true); |
238 | set_cpu_present(mid, true); | |
7202fb49 BB |
239 | } |
240 | instance++; | |
241 | } | |
242 | } | |
243 | ||
92d452f0 | 244 | void __init smp_prepare_boot_cpu(void) |
1da177e4 | 245 | { |
a54123e2 BB |
246 | int cpuid = hard_smp_processor_id(); |
247 | ||
248 | if (cpuid >= NR_CPUS) { | |
249 | prom_printf("Serious problem, boot cpu id >= NR_CPUS\n"); | |
250 | prom_halt(); | |
251 | } | |
252 | if (cpuid != 0) | |
253 | printk("boot cpu id != 0, this could work but is untested\n"); | |
254 | ||
255 | current_thread_info()->cpu = cpuid; | |
fe73971c RR |
256 | set_cpu_online(cpuid, true); |
257 | set_cpu_possible(cpuid, true); | |
1da177e4 LT |
258 | } |
259 | ||
2066aadd | 260 | int __cpu_up(unsigned int cpu, struct task_struct *tidle) |
1da177e4 | 261 | { |
8b3c848c RB |
262 | int ret=0; |
263 | ||
264 | switch(sparc_cpu_model) { | |
8b3c848c | 265 | case sun4m: |
f0a2bc7e | 266 | ret = smp4m_boot_one_cpu(cpu, tidle); |
8b3c848c RB |
267 | break; |
268 | case sun4d: | |
f0a2bc7e | 269 | ret = smp4d_boot_one_cpu(cpu, tidle); |
8b3c848c | 270 | break; |
8401707f | 271 | case sparc_leon: |
f0a2bc7e | 272 | ret = leon_boot_one_cpu(cpu, tidle); |
8401707f | 273 | break; |
8b3c848c RB |
274 | case sun4e: |
275 | printk("SUN4E\n"); | |
276 | BUG(); | |
277 | break; | |
278 | case sun4u: | |
279 | printk("SUN4U\n"); | |
280 | BUG(); | |
281 | break; | |
282 | default: | |
283 | printk("UNKNOWN!\n"); | |
284 | BUG(); | |
285 | break; | |
6cb79b3f | 286 | } |
a54123e2 BB |
287 | |
288 | if (!ret) { | |
fb1fece5 | 289 | cpumask_set_cpu(cpu, &smp_commenced_mask); |
a54123e2 BB |
290 | while (!cpu_online(cpu)) |
291 | mb(); | |
292 | } | |
293 | return ret; | |
1da177e4 LT |
294 | } |
295 | ||
c0b0ba84 | 296 | static void arch_cpu_pre_starting(void *arg) |
f9fd3488 SR |
297 | { |
298 | local_ops->cache_all(); | |
299 | local_ops->tlb_all(); | |
300 | ||
301 | switch(sparc_cpu_model) { | |
302 | case sun4m: | |
303 | sun4m_cpu_pre_starting(arg); | |
304 | break; | |
305 | case sun4d: | |
306 | sun4d_cpu_pre_starting(arg); | |
307 | break; | |
308 | case sparc_leon: | |
309 | leon_cpu_pre_starting(arg); | |
310 | break; | |
311 | default: | |
312 | BUG(); | |
313 | } | |
314 | } | |
315 | ||
c0b0ba84 | 316 | static void arch_cpu_pre_online(void *arg) |
f9fd3488 SR |
317 | { |
318 | unsigned int cpuid = hard_smp_processor_id(); | |
319 | ||
320 | register_percpu_ce(cpuid); | |
321 | ||
322 | calibrate_delay(); | |
323 | smp_store_cpu_info(cpuid); | |
324 | ||
325 | local_ops->cache_all(); | |
326 | local_ops->tlb_all(); | |
327 | ||
328 | switch(sparc_cpu_model) { | |
329 | case sun4m: | |
330 | sun4m_cpu_pre_online(arg); | |
331 | break; | |
332 | case sun4d: | |
333 | sun4d_cpu_pre_online(arg); | |
334 | break; | |
335 | case sparc_leon: | |
336 | leon_cpu_pre_online(arg); | |
337 | break; | |
338 | default: | |
339 | BUG(); | |
340 | } | |
341 | } | |
342 | ||
c0b0ba84 | 343 | static void sparc_start_secondary(void *arg) |
f9fd3488 SR |
344 | { |
345 | unsigned int cpu; | |
346 | ||
347 | /* | |
348 | * SMP booting is extremely fragile in some architectures. So run | |
349 | * the cpu initialization code first before anything else. | |
350 | */ | |
351 | arch_cpu_pre_starting(arg); | |
352 | ||
353 | preempt_disable(); | |
354 | cpu = smp_processor_id(); | |
355 | ||
f9fd3488 | 356 | notify_cpu_starting(cpu); |
f9fd3488 SR |
357 | arch_cpu_pre_online(arg); |
358 | ||
359 | /* Set the CPU in the cpu_online_mask */ | |
360 | set_cpu_online(cpu, true); | |
361 | ||
362 | /* Enable local interrupts now */ | |
363 | local_irq_enable(); | |
364 | ||
365 | wmb(); | |
fc6d73d6 | 366 | cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); |
f9fd3488 SR |
367 | |
368 | /* We should never reach here! */ | |
369 | BUG(); | |
370 | } | |
371 | ||
2066aadd | 372 | void smp_callin(void) |
f9fd3488 SR |
373 | { |
374 | sparc_start_secondary(NULL); | |
375 | } | |
376 | ||
1da177e4 LT |
377 | void smp_bogo(struct seq_file *m) |
378 | { | |
379 | int i; | |
380 | ||
394e3902 AM |
381 | for_each_online_cpu(i) { |
382 | seq_printf(m, | |
383 | "Cpu%dBogo\t: %lu.%02lu\n", | |
384 | i, | |
385 | cpu_data(i).udelay_val/(500000/HZ), | |
386 | (cpu_data(i).udelay_val/(5000/HZ))%100); | |
1da177e4 LT |
387 | } |
388 | } | |
389 | ||
390 | void smp_info(struct seq_file *m) | |
391 | { | |
392 | int i; | |
393 | ||
394 | seq_printf(m, "State:\n"); | |
394e3902 AM |
395 | for_each_online_cpu(i) |
396 | seq_printf(m, "CPU%d\t\t: online\n", i); | |
1da177e4 | 397 | } |