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2153e8fb SG |
1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | /* | |
3 | * Copyright 2019 Google LLC | |
4 | * Written by Simon Glass <sjg@chromium.org> | |
5 | */ | |
6 | ||
7 | #include <common.h> | |
8 | #include <acpi_s3.h> | |
9 | #include <binman.h> | |
10 | #include <dm.h> | |
11 | #include <irq.h> | |
336d4615 | 12 | #include <malloc.h> |
2153e8fb SG |
13 | #include <asm/intel_pinctrl.h> |
14 | #include <asm/io.h> | |
15 | #include <asm/intel_regs.h> | |
16 | #include <asm/msr.h> | |
17 | #include <asm/msr-index.h> | |
18 | #include <asm/pci.h> | |
19 | #include <asm/arch/cpu.h> | |
20 | #include <asm/arch/systemagent.h> | |
21 | #include <asm/arch/fsp/fsp_configs.h> | |
22 | #include <asm/arch/fsp/fsp_s_upd.h> | |
23 | ||
24 | #define PCH_P2SB_E0 0xe0 | |
25 | #define HIDE_BIT BIT(0) | |
26 | ||
27 | #define INTEL_GSPI_MAX 3 | |
28 | #define INTEL_I2C_DEV_MAX 8 | |
29 | #define MAX_USB2_PORTS 8 | |
30 | ||
31 | enum { | |
32 | CHIPSET_LOCKDOWN_FSP = 0, /* FSP handles locking per UPDs */ | |
33 | CHIPSET_LOCKDOWN_COREBOOT, /* coreboot handles locking */ | |
34 | }; | |
35 | ||
36 | enum i2c_speed { | |
37 | I2C_SPEED_STANDARD = 100000, | |
38 | I2C_SPEED_FAST = 400000, | |
39 | I2C_SPEED_FAST_PLUS = 1000000, | |
40 | I2C_SPEED_HIGH = 3400000, | |
41 | I2C_SPEED_FAST_ULTRA = 5000000, | |
42 | }; | |
43 | ||
44 | /* | |
45 | * Timing values are in units of clock period, with the clock speed | |
46 | * provided by the SOC | |
47 | * | |
48 | * TODO(sjg@chromium.org): Connect this up to the I2C driver | |
49 | */ | |
50 | struct dw_i2c_speed_config { | |
51 | enum i2c_speed speed; | |
52 | /* SCL high and low period count */ | |
53 | u16 scl_lcnt; | |
54 | u16 scl_hcnt; | |
55 | /* | |
56 | * SDA hold time should be 300ns in standard and fast modes | |
57 | * and long enough for deterministic logic level change in | |
58 | * fast-plus and high speed modes. | |
59 | * | |
60 | * [15:0] SDA TX Hold Time | |
61 | * [23:16] SDA RX Hold Time | |
62 | */ | |
63 | u32 sda_hold; | |
64 | }; | |
65 | ||
66 | /* Serial IRQ control. SERIRQ_QUIET is the default (0) */ | |
67 | enum serirq_mode { | |
68 | SERIRQ_QUIET, | |
69 | SERIRQ_CONTINUOUS, | |
70 | SERIRQ_OFF, | |
71 | }; | |
72 | ||
73 | /* | |
74 | * This I2C controller has support for 3 independent speed configs but can | |
75 | * support both FAST_PLUS and HIGH speeds through the same set of speed | |
76 | * config registers. These are treated separately so the speed config values | |
77 | * can be provided via ACPI to the OS. | |
78 | */ | |
79 | #define DW_I2C_SPEED_CONFIG_COUNT 4 | |
80 | ||
81 | struct dw_i2c_bus_config { | |
82 | /* Bus should be enabled in TPL with temporary base */ | |
83 | int early_init; | |
84 | /* Bus speed in Hz, default is I2C_SPEED_FAST (400 KHz) */ | |
85 | enum i2c_speed speed; | |
86 | /* | |
87 | * If rise_time_ns is non-zero the calculations for lcnt and hcnt | |
88 | * registers take into account the times of the bus. However, if | |
89 | * there is a match in speed_config those register values take | |
90 | * precedence | |
91 | */ | |
92 | int rise_time_ns; | |
93 | int fall_time_ns; | |
94 | int data_hold_time_ns; | |
95 | /* Specific bus speed configuration */ | |
96 | struct dw_i2c_speed_config speed_config[DW_I2C_SPEED_CONFIG_COUNT]; | |
97 | }; | |
98 | ||
99 | struct gspi_cfg { | |
100 | /* Bus speed in MHz */ | |
101 | u32 speed_mhz; | |
102 | /* Bus should be enabled prior to ramstage with temporary base */ | |
103 | u8 early_init; | |
104 | }; | |
105 | ||
106 | /* | |
107 | * This structure will hold data required by common blocks. | |
108 | * These are soc specific configurations which will be filled by soc. | |
109 | * We'll fill this structure once during init and use the data in common block. | |
110 | */ | |
111 | struct soc_intel_common_config { | |
112 | int chipset_lockdown; | |
113 | struct gspi_cfg gspi[INTEL_GSPI_MAX]; | |
114 | struct dw_i2c_bus_config i2c[INTEL_I2C_DEV_MAX]; | |
115 | }; | |
116 | ||
117 | enum pnp_settings { | |
118 | PNP_PERF, | |
119 | PNP_POWER, | |
120 | PNP_PERF_POWER, | |
121 | }; | |
122 | ||
123 | struct usb2_eye_per_port { | |
124 | u8 per_port_tx_pe_half; | |
125 | u8 per_port_pe_txi_set; | |
126 | u8 per_port_txi_set; | |
127 | u8 hs_skew_sel; | |
128 | u8 usb_tx_emphasis_en; | |
129 | u8 per_port_rxi_set; | |
130 | u8 hs_npre_drv_sel; | |
131 | u8 override_en; | |
132 | }; | |
133 | ||
134 | struct apl_config { | |
135 | /* Common structure containing soc config data required by common code*/ | |
136 | struct soc_intel_common_config common_soc_config; | |
137 | ||
138 | /* | |
139 | * Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has | |
140 | * four CLKREQ inputs, but six root ports. Root ports without an | |
141 | * associated CLKREQ signal must be marked with "CLKREQ_DISABLED" | |
142 | */ | |
143 | u8 pcie_rp_clkreq_pin[MAX_PCIE_PORTS]; | |
144 | ||
145 | /* Enable/disable hot-plug for root ports (0 = disable, 1 = enable) */ | |
146 | u8 pcie_rp_hotplug_enable[MAX_PCIE_PORTS]; | |
147 | ||
148 | /* De-emphasis enable configuration for each PCIe root port */ | |
149 | u8 pcie_rp_deemphasis_enable[MAX_PCIE_PORTS]; | |
150 | ||
151 | /* | |
152 | * [14:8] DDR mode Number of dealy elements.Each = 125pSec. | |
153 | * [6:0] SDR mode Number of dealy elements.Each = 125pSec. | |
154 | */ | |
155 | u32 emmc_tx_cmd_cntl; | |
156 | ||
157 | /* | |
158 | * [14:8] HS400 mode Number of dealy elements.Each = 125pSec. | |
159 | * [6:0] SDR104/HS200 mode Number of dealy elements.Each = 125pSec. | |
160 | */ | |
161 | u32 emmc_tx_data_cntl1; | |
162 | ||
163 | /* | |
164 | * [30:24] SDR50 mode Number of dealy elements.Each = 125pSec. | |
165 | * [22:16] DDR50 mode Number of dealy elements.Each = 125pSec. | |
166 | * [14:8] SDR25/HS50 mode Number of dealy elements.Each = 125pSec. | |
167 | * [6:0] SDR12/Compatibility mode Number of dealy elements. | |
168 | * Each = 125pSec. | |
169 | */ | |
170 | u32 emmc_tx_data_cntl2; | |
171 | ||
172 | /* | |
173 | * [30:24] SDR50 mode Number of dealy elements.Each = 125pSec. | |
174 | * [22:16] DDR50 mode Number of dealy elements.Each = 125pSec. | |
175 | * [14:8] SDR25/HS50 mode Number of dealy elements.Each = 125pSec. | |
176 | * [6:0] SDR12/Compatibility mode Number of dealy elements. | |
177 | * Each = 125pSec. | |
178 | */ | |
179 | u32 emmc_rx_cmd_data_cntl1; | |
180 | ||
181 | /* | |
182 | * [14:8] HS400 mode 1 Number of dealy elements.Each = 125pSec. | |
183 | * [6:0] HS400 mode 2 Number of dealy elements.Each = 125pSec. | |
184 | */ | |
185 | u32 emmc_rx_strobe_cntl; | |
186 | ||
187 | /* | |
188 | * [13:8] Auto Tuning mode Number of dealy elements.Each = 125pSec. | |
189 | * [6:0] SDR104/HS200 Number of dealy elements.Each = 125pSec. | |
190 | */ | |
191 | u32 emmc_rx_cmd_data_cntl2; | |
192 | ||
193 | /* Select the eMMC max speed allowed */ | |
194 | u32 emmc_host_max_speed; | |
195 | ||
196 | /* Specifies on which IRQ the SCI will internally appear */ | |
197 | u32 sci_irq; | |
198 | ||
199 | /* Configure serial IRQ (SERIRQ) line */ | |
200 | enum serirq_mode serirq_mode; | |
201 | ||
202 | /* Configure LPSS S0ix Enable */ | |
203 | bool lpss_s0ix_enable; | |
204 | ||
205 | /* Enable DPTF support */ | |
206 | bool dptf_enable; | |
207 | ||
208 | /* TCC activation offset value in degrees Celsius */ | |
209 | int tcc_offset; | |
210 | ||
211 | /* | |
212 | * Configure Audio clk gate and power gate | |
213 | * IOSF-SB port ID 92 offset 0x530 [5] and [3] | |
214 | */ | |
215 | bool hdaudio_clk_gate_enable; | |
216 | bool hdaudio_pwr_gate_enable; | |
217 | bool hdaudio_bios_config_lockdown; | |
218 | ||
219 | /* SLP S3 minimum assertion width */ | |
220 | int slp_s3_assertion_width_usecs; | |
221 | ||
222 | /* GPIO pin for PERST_0 */ | |
223 | u32 prt0_gpio; | |
224 | ||
225 | /* USB2 eye diagram settings per port */ | |
226 | struct usb2_eye_per_port usb2eye[MAX_USB2_PORTS]; | |
227 | ||
228 | /* GPIO SD card detect pin */ | |
229 | unsigned int sdcard_cd_gpio; | |
230 | ||
231 | /* | |
232 | * PRMRR size setting with three options | |
233 | * 0x02000000 - 32MiB | |
234 | * 0x04000000 - 64MiB | |
235 | * 0x08000000 - 128MiB | |
236 | */ | |
237 | u32 PrmrrSize; | |
238 | ||
239 | /* | |
240 | * Enable SGX feature. | |
241 | * Enabling SGX feature is 2 step process, | |
242 | * (1) set sgx_enable = 1 | |
243 | * (2) set PrmrrSize to supported size | |
244 | */ | |
245 | bool sgx_enable; | |
246 | ||
247 | /* | |
248 | * Select PNP Settings. | |
249 | * (0) Performance, | |
250 | * (1) Power | |
251 | * (2) Power & Performance | |
252 | */ | |
253 | enum pnp_settings pnp_settings; | |
254 | ||
255 | /* | |
256 | * PMIC PCH_PWROK delay configuration - IPC Configuration | |
257 | * Upd for changing PCH_PWROK delay configuration : I2C_Slave_Address | |
258 | * (31:24) + Register_Offset (23:16) + OR Value (15:8) + AND Value (7:0) | |
259 | */ | |
260 | u32 pmic_pmc_ipc_ctrl; | |
261 | ||
262 | /* | |
263 | * Options to disable XHCI Link Compliance Mode. Default is FALSE to not | |
264 | * disable Compliance Mode. Set TRUE to disable Compliance Mode. | |
265 | * 0:FALSE(Default), 1:True. | |
266 | */ | |
267 | bool disable_compliance_mode; | |
268 | ||
269 | /* | |
270 | * Options to change USB3 ModPhy setting for the Integrated Filter (IF) | |
271 | * value. Default is 0 to not changing default IF value (0x12). Set | |
272 | * value with the range from 0x01 to 0xff to change IF value. | |
273 | */ | |
274 | u32 mod_phy_if_value; | |
275 | ||
276 | /* | |
277 | * Options to bump USB3 LDO voltage. Default is FALSE to not increasing | |
278 | * LDO voltage. Set TRUE to increase LDO voltage with 40mV. | |
279 | * 0:FALSE (default), 1:True. | |
280 | */ | |
281 | bool mod_phy_voltage_bump; | |
282 | ||
283 | /* | |
284 | * Options to adjust PMIC Vdd2 voltage. Default is 0 to not adjusting | |
285 | * the PMIC Vdd2 default voltage 1.20v. Upd for changing Vdd2 Voltage | |
286 | * configuration: I2C_Slave_Address (31:23) + Register_Offset (23:16) | |
287 | * + OR Value (15:8) + AND Value (7:0) through BUCK5_VID[3:2]: | |
288 | * 00=1.10v, 01=1.15v, 10=1.24v, 11=1.20v (default). | |
289 | */ | |
290 | u32 pmic_vdd2_voltage; | |
291 | ||
292 | /* Option to enable VTD feature */ | |
293 | bool enable_vtd; | |
294 | }; | |
295 | ||
296 | static int get_config(struct udevice *dev, struct apl_config *apl) | |
297 | { | |
298 | const u8 *ptr; | |
299 | ofnode node; | |
300 | u32 emmc[4]; | |
301 | int ret; | |
302 | ||
303 | memset(apl, '\0', sizeof(*apl)); | |
304 | ||
305 | node = dev_read_subnode(dev, "fsp-s"); | |
306 | if (!ofnode_valid(node)) | |
307 | return log_msg_ret("fsp-s settings", -ENOENT); | |
308 | ||
309 | ptr = ofnode_read_u8_array_ptr(node, "pcie-rp-clkreq-pin", | |
310 | MAX_PCIE_PORTS); | |
311 | if (!ptr) | |
312 | return log_msg_ret("pcie-rp-clkreq-pin", -EINVAL); | |
313 | memcpy(apl->pcie_rp_clkreq_pin, ptr, MAX_PCIE_PORTS); | |
314 | ||
315 | ret = ofnode_read_u32(node, "prt0-gpio", &apl->prt0_gpio); | |
316 | if (ret) | |
317 | return log_msg_ret("prt0-gpio", ret); | |
318 | ret = ofnode_read_u32(node, "sdcard-cd-gpio", &apl->sdcard_cd_gpio); | |
319 | if (ret) | |
320 | return log_msg_ret("sdcard-cd-gpio", ret); | |
321 | ||
322 | ret = ofnode_read_u32_array(node, "emmc", emmc, ARRAY_SIZE(emmc)); | |
323 | if (ret) | |
324 | return log_msg_ret("emmc", ret); | |
325 | apl->emmc_tx_data_cntl1 = emmc[0]; | |
326 | apl->emmc_tx_data_cntl2 = emmc[1]; | |
327 | apl->emmc_rx_cmd_data_cntl1 = emmc[2]; | |
328 | apl->emmc_rx_cmd_data_cntl2 = emmc[3]; | |
329 | ||
330 | apl->dptf_enable = ofnode_read_bool(node, "dptf-enable"); | |
331 | ||
332 | apl->hdaudio_clk_gate_enable = ofnode_read_bool(node, | |
333 | "hdaudio-clk-gate-enable"); | |
334 | apl->hdaudio_pwr_gate_enable = ofnode_read_bool(node, | |
335 | "hdaudio-pwr-gate-enable"); | |
336 | apl->hdaudio_bios_config_lockdown = ofnode_read_bool(node, | |
337 | "hdaudio-bios-config-lockdown"); | |
338 | apl->lpss_s0ix_enable = ofnode_read_bool(node, "lpss-s0ix-enable"); | |
339 | ||
340 | /* Santa */ | |
341 | apl->usb2eye[1].per_port_pe_txi_set = 7; | |
342 | apl->usb2eye[1].per_port_txi_set = 2; | |
343 | ||
344 | return 0; | |
345 | } | |
346 | ||
347 | static void apl_fsp_silicon_init_params_cb(struct apl_config *apl, | |
348 | struct fsp_s_config *cfg) | |
349 | { | |
350 | u8 port; | |
351 | ||
352 | for (port = 0; port < MAX_USB2_PORTS; port++) { | |
353 | if (apl->usb2eye[port].per_port_tx_pe_half) | |
354 | cfg->port_usb20_per_port_tx_pe_half[port] = | |
355 | apl->usb2eye[port].per_port_tx_pe_half; | |
356 | ||
357 | if (apl->usb2eye[port].per_port_pe_txi_set) | |
358 | cfg->port_usb20_per_port_pe_txi_set[port] = | |
359 | apl->usb2eye[port].per_port_pe_txi_set; | |
360 | ||
361 | if (apl->usb2eye[port].per_port_txi_set) | |
362 | cfg->port_usb20_per_port_txi_set[port] = | |
363 | apl->usb2eye[port].per_port_txi_set; | |
364 | ||
365 | if (apl->usb2eye[port].hs_skew_sel) | |
366 | cfg->port_usb20_hs_skew_sel[port] = | |
367 | apl->usb2eye[port].hs_skew_sel; | |
368 | ||
369 | if (apl->usb2eye[port].usb_tx_emphasis_en) | |
370 | cfg->port_usb20_i_usb_tx_emphasis_en[port] = | |
371 | apl->usb2eye[port].usb_tx_emphasis_en; | |
372 | ||
373 | if (apl->usb2eye[port].per_port_rxi_set) | |
374 | cfg->port_usb20_per_port_rxi_set[port] = | |
375 | apl->usb2eye[port].per_port_rxi_set; | |
376 | ||
377 | if (apl->usb2eye[port].hs_npre_drv_sel) | |
378 | cfg->port_usb20_hs_npre_drv_sel[port] = | |
379 | apl->usb2eye[port].hs_npre_drv_sel; | |
380 | } | |
381 | } | |
382 | ||
383 | int fsps_update_config(struct udevice *dev, ulong rom_offset, | |
384 | struct fsps_upd *upd) | |
385 | { | |
386 | struct fsp_s_config *cfg = &upd->config; | |
387 | struct apl_config *apl; | |
388 | struct binman_entry vbt; | |
389 | void *buf; | |
390 | int ret; | |
391 | ||
392 | ret = binman_entry_find("intel-vbt", &vbt); | |
393 | if (ret) | |
394 | return log_msg_ret("Cannot find VBT", ret); | |
395 | vbt.image_pos += rom_offset; | |
396 | buf = malloc(vbt.size); | |
397 | if (!buf) | |
398 | return log_msg_ret("Alloc VBT", -ENOMEM); | |
399 | ||
400 | /* | |
401 | * Load VBT before devicetree-specific config. This only supports | |
402 | * memory-mapped SPI at present. | |
403 | */ | |
404 | bootstage_start(BOOTSTAGE_ID_ACCUM_MMAP_SPI, "mmap_spi"); | |
405 | memcpy(buf, (void *)vbt.image_pos, vbt.size); | |
406 | bootstage_accum(BOOTSTAGE_ID_ACCUM_MMAP_SPI); | |
407 | if (*(u32 *)buf != VBT_SIGNATURE) | |
408 | return log_msg_ret("VBT signature", -EINVAL); | |
409 | cfg->graphics_config_ptr = (ulong)buf; | |
410 | ||
411 | apl = malloc(sizeof(*apl)); | |
412 | if (!apl) | |
413 | return log_msg_ret("config", -ENOMEM); | |
414 | get_config(dev, apl); | |
415 | ||
416 | cfg->ish_enable = 0; | |
417 | cfg->enable_sata = 0; | |
418 | cfg->pcie_root_port_en[2] = 0; | |
419 | cfg->pcie_rp_hot_plug[2] = 0; | |
420 | cfg->pcie_root_port_en[3] = 0; | |
421 | cfg->pcie_rp_hot_plug[3] = 0; | |
422 | cfg->pcie_root_port_en[4] = 0; | |
423 | cfg->pcie_rp_hot_plug[4] = 0; | |
424 | cfg->pcie_root_port_en[5] = 0; | |
425 | cfg->pcie_rp_hot_plug[5] = 0; | |
426 | cfg->pcie_root_port_en[1] = 0; | |
427 | cfg->pcie_rp_hot_plug[1] = 0; | |
428 | cfg->usb_otg = 0; | |
429 | cfg->i2c6_enable = 0; | |
430 | cfg->i2c7_enable = 0; | |
431 | cfg->hsuart3_enable = 0; | |
432 | cfg->spi1_enable = 0; | |
433 | cfg->spi2_enable = 0; | |
434 | cfg->sdio_enabled = 0; | |
435 | ||
436 | memcpy(cfg->pcie_rp_clk_req_number, apl->pcie_rp_clkreq_pin, | |
437 | sizeof(cfg->pcie_rp_clk_req_number)); | |
438 | ||
439 | memcpy(cfg->pcie_rp_hot_plug, apl->pcie_rp_hotplug_enable, | |
440 | sizeof(cfg->pcie_rp_hot_plug)); | |
441 | ||
442 | switch (apl->serirq_mode) { | |
443 | case SERIRQ_QUIET: | |
444 | cfg->sirq_enable = 1; | |
445 | cfg->sirq_mode = 0; | |
446 | break; | |
447 | case SERIRQ_CONTINUOUS: | |
448 | cfg->sirq_enable = 1; | |
449 | cfg->sirq_mode = 1; | |
450 | break; | |
451 | case SERIRQ_OFF: | |
452 | default: | |
453 | cfg->sirq_enable = 0; | |
454 | break; | |
455 | } | |
456 | ||
457 | if (apl->emmc_tx_cmd_cntl) | |
458 | cfg->emmc_tx_cmd_cntl = apl->emmc_tx_cmd_cntl; | |
459 | if (apl->emmc_tx_data_cntl1) | |
460 | cfg->emmc_tx_data_cntl1 = apl->emmc_tx_data_cntl1; | |
461 | if (apl->emmc_tx_data_cntl2) | |
462 | cfg->emmc_tx_data_cntl2 = apl->emmc_tx_data_cntl2; | |
463 | if (apl->emmc_rx_cmd_data_cntl1) | |
464 | cfg->emmc_rx_cmd_data_cntl1 = apl->emmc_rx_cmd_data_cntl1; | |
465 | if (apl->emmc_rx_strobe_cntl) | |
466 | cfg->emmc_rx_strobe_cntl = apl->emmc_rx_strobe_cntl; | |
467 | if (apl->emmc_rx_cmd_data_cntl2) | |
468 | cfg->emmc_rx_cmd_data_cntl2 = apl->emmc_rx_cmd_data_cntl2; | |
469 | if (apl->emmc_host_max_speed) | |
470 | cfg->e_mmc_host_max_speed = apl->emmc_host_max_speed; | |
471 | ||
472 | cfg->lpss_s0ix_enable = apl->lpss_s0ix_enable; | |
473 | ||
474 | cfg->skip_mp_init = true; | |
475 | ||
476 | /* Disable setting of EISS bit in FSP */ | |
477 | cfg->spi_eiss = 0; | |
478 | ||
479 | /* Disable FSP from locking access to the RTC NVRAM */ | |
480 | cfg->rtc_lock = 0; | |
481 | ||
482 | /* Enable Audio clk gate and power gate */ | |
483 | cfg->hd_audio_clk_gate = apl->hdaudio_clk_gate_enable; | |
484 | cfg->hd_audio_pwr_gate = apl->hdaudio_pwr_gate_enable; | |
485 | /* Bios config lockdown Audio clk and power gate */ | |
486 | cfg->bios_cfg_lock_down = apl->hdaudio_bios_config_lockdown; | |
487 | apl_fsp_silicon_init_params_cb(apl, cfg); | |
488 | ||
489 | cfg->usb_otg = true; | |
490 | cfg->vtd_enable = apl->enable_vtd; | |
491 | ||
492 | return 0; | |
493 | } | |
494 | ||
495 | static void p2sb_set_hide_bit(pci_dev_t dev, int hide) | |
496 | { | |
497 | pci_x86_clrset_config(dev, PCH_P2SB_E0 + 1, HIDE_BIT, | |
498 | hide ? HIDE_BIT : 0, PCI_SIZE_8); | |
499 | } | |
500 | ||
501 | /* Configure package power limits */ | |
502 | static int set_power_limits(struct udevice *dev) | |
503 | { | |
504 | msr_t rapl_msr_reg, limit; | |
505 | u32 power_unit; | |
506 | u32 tdp, min_power, max_power; | |
507 | u32 pl2_val; | |
508 | u32 override_tdp[2]; | |
509 | int ret; | |
510 | ||
511 | /* Get units */ | |
512 | rapl_msr_reg = msr_read(MSR_PKG_POWER_SKU_UNIT); | |
513 | power_unit = 1 << (rapl_msr_reg.lo & 0xf); | |
514 | ||
515 | /* Get power defaults for this SKU */ | |
516 | rapl_msr_reg = msr_read(MSR_PKG_POWER_SKU); | |
517 | tdp = rapl_msr_reg.lo & PKG_POWER_LIMIT_MASK; | |
518 | pl2_val = rapl_msr_reg.hi & PKG_POWER_LIMIT_MASK; | |
519 | min_power = (rapl_msr_reg.lo >> 16) & PKG_POWER_LIMIT_MASK; | |
520 | max_power = rapl_msr_reg.hi & PKG_POWER_LIMIT_MASK; | |
521 | ||
522 | if (min_power > 0 && tdp < min_power) | |
523 | tdp = min_power; | |
524 | ||
525 | if (max_power > 0 && tdp > max_power) | |
526 | tdp = max_power; | |
527 | ||
528 | ret = dev_read_u32_array(dev, "tdp-pl-override-mw", override_tdp, | |
529 | ARRAY_SIZE(override_tdp)); | |
530 | if (ret) | |
531 | return log_msg_ret("tdp-pl-override-mw", ret); | |
532 | ||
533 | /* Set PL1 override value */ | |
534 | if (override_tdp[0]) | |
535 | tdp = override_tdp[0] * power_unit / 1000; | |
536 | ||
537 | /* Set PL2 override value */ | |
538 | if (override_tdp[1]) | |
539 | pl2_val = override_tdp[1] * power_unit / 1000; | |
540 | ||
541 | /* Set long term power limit to TDP */ | |
542 | limit.lo = tdp & PKG_POWER_LIMIT_MASK; | |
543 | /* Set PL1 Pkg Power clamp bit */ | |
544 | limit.lo |= PKG_POWER_LIMIT_CLAMP; | |
545 | ||
546 | limit.lo |= PKG_POWER_LIMIT_EN; | |
547 | limit.lo |= (MB_POWER_LIMIT1_TIME_DEFAULT & | |
548 | PKG_POWER_LIMIT_TIME_MASK) << PKG_POWER_LIMIT_TIME_SHIFT; | |
549 | ||
550 | /* Set short term power limit PL2 */ | |
551 | limit.hi = pl2_val & PKG_POWER_LIMIT_MASK; | |
552 | limit.hi |= PKG_POWER_LIMIT_EN; | |
553 | ||
554 | /* Program package power limits in RAPL MSR */ | |
555 | msr_write(MSR_PKG_POWER_LIMIT, limit); | |
556 | log_info("RAPL PL1 %d.%dW\n", tdp / power_unit, | |
557 | 100 * (tdp % power_unit) / power_unit); | |
558 | log_info("RAPL PL2 %d.%dW\n", pl2_val / power_unit, | |
559 | 100 * (pl2_val % power_unit) / power_unit); | |
560 | ||
561 | /* | |
562 | * Sett RAPL MMIO register for Power limits. RAPL driver is using MSR | |
563 | * instead of MMIO, so disable LIMIT_EN bit for MMIO | |
564 | */ | |
565 | writel(limit.lo & ~PKG_POWER_LIMIT_EN, MCHBAR_REG(MCHBAR_RAPL_PPL)); | |
566 | writel(limit.hi & ~PKG_POWER_LIMIT_EN, MCHBAR_REG(MCHBAR_RAPL_PPL + 4)); | |
567 | ||
568 | return 0; | |
569 | } | |
570 | ||
571 | int p2sb_unhide(void) | |
572 | { | |
573 | pci_dev_t dev = PCI_BDF(0, 0xd, 0); | |
574 | ulong val; | |
575 | ||
576 | p2sb_set_hide_bit(dev, 0); | |
577 | ||
578 | pci_x86_read_config(dev, PCI_VENDOR_ID, &val, PCI_SIZE_16); | |
579 | ||
580 | if (val != PCI_VENDOR_ID_INTEL) | |
581 | return log_msg_ret("p2sb unhide", -EIO); | |
582 | ||
583 | return 0; | |
584 | } | |
585 | ||
586 | /* Overwrites the SCI IRQ if another IRQ number is given by device tree */ | |
587 | static void set_sci_irq(void) | |
588 | { | |
589 | /* Skip this for now */ | |
590 | } | |
591 | ||
592 | int arch_fsps_preinit(void) | |
593 | { | |
594 | struct udevice *itss; | |
595 | int ret; | |
596 | ||
597 | ret = uclass_first_device_err(UCLASS_IRQ, &itss); | |
598 | if (ret) | |
599 | return log_msg_ret("no itss", ret); | |
600 | /* | |
601 | * Snapshot the current GPIO IRQ polarities. FSP is setting a default | |
602 | * policy that doesn't honour boards' requirements | |
603 | */ | |
604 | irq_snapshot_polarities(itss); | |
605 | ||
606 | /* | |
607 | * Clear the GPI interrupt status and enable registers. These | |
608 | * registers do not get reset to default state when booting from S5. | |
609 | */ | |
610 | ret = pinctrl_gpi_clear_int_cfg(); | |
611 | if (ret) | |
612 | return log_msg_ret("gpi_clear", ret); | |
613 | ||
614 | return 0; | |
615 | } | |
616 | ||
617 | int arch_fsp_init_r(void) | |
618 | { | |
619 | #ifdef CONFIG_HAVE_ACPI_RESUME | |
620 | bool s3wake = gd->arch.prev_sleep_state == ACPI_S3; | |
621 | #else | |
622 | bool s3wake = false; | |
623 | #endif | |
624 | struct udevice *dev, *itss; | |
625 | int ret; | |
626 | ||
627 | /* | |
628 | * This must be called before any devices are probed. Put any probing | |
629 | * into arch_fsps_preinit() above. | |
630 | * | |
631 | * We don't use CONFIG_APL_BOOT_FROM_FAST_SPI_FLASH here since it will | |
632 | * force PCI to be probed. | |
633 | */ | |
634 | ret = fsp_silicon_init(s3wake, false); | |
635 | if (ret) | |
636 | return ret; | |
637 | ||
638 | ret = uclass_first_device_err(UCLASS_IRQ, &itss); | |
639 | if (ret) | |
640 | return log_msg_ret("no itss", ret); | |
641 | /* Restore GPIO IRQ polarities back to previous settings */ | |
642 | irq_restore_polarities(itss); | |
643 | ||
644 | /* soc_init() */ | |
645 | ret = p2sb_unhide(); | |
646 | if (ret) | |
647 | return log_msg_ret("unhide p2sb", ret); | |
648 | ||
649 | /* Set RAPL MSR for Package power limits*/ | |
650 | ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &dev); | |
651 | if (ret) | |
652 | return log_msg_ret("Cannot get northbridge", ret); | |
653 | set_power_limits(dev); | |
654 | ||
655 | /* | |
656 | * FSP-S routes SCI to IRQ 9. With the help of this function you can | |
657 | * select another IRQ for SCI. | |
658 | */ | |
659 | set_sci_irq(); | |
660 | ||
661 | return 0; | |
662 | } |