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Commit | Line | Data |
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2262cfee | 1 | /* |
dbf7115a GR |
2 | * (C) Copyright 2008-2011 |
3 | * Graeme Russ, <graeme.russ@gmail.com> | |
4 | * | |
2262cfee | 5 | * (C) Copyright 2002 |
fa82f871 | 6 | * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> |
8bde7f77 | 7 | * |
2262cfee WD |
8 | * (C) Copyright 2002 |
9 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
10 | * Marius Groeger <mgroeger@sysgo.de> | |
11 | * | |
12 | * (C) Copyright 2002 | |
13 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
14 | * Alex Zuepke <azu@sysgo.de> | |
15 | * | |
52f952bf BM |
16 | * Part of this file is adapted from coreboot |
17 | * src/arch/x86/lib/cpu.c | |
18 | * | |
1a459660 | 19 | * SPDX-License-Identifier: GPL-2.0+ |
2262cfee WD |
20 | */ |
21 | ||
2262cfee WD |
22 | #include <common.h> |
23 | #include <command.h> | |
6e6f4ce4 | 24 | #include <dm.h> |
200182a7 SG |
25 | #include <errno.h> |
26 | #include <malloc.h> | |
d8906c1f | 27 | #include <syscon.h> |
b727961b | 28 | #include <asm/acpi_s3.h> |
3a34cae0 | 29 | #include <asm/acpi_table.h> |
095593c0 | 30 | #include <asm/control_regs.h> |
d19c9074 | 31 | #include <asm/coreboot_tables.h> |
200182a7 | 32 | #include <asm/cpu.h> |
6e6f4ce4 | 33 | #include <asm/lapic.h> |
e77b62e2 | 34 | #include <asm/microcode.h> |
6e6f4ce4 | 35 | #include <asm/mp.h> |
0c2b7eef | 36 | #include <asm/mrccache.h> |
43dd22f5 BM |
37 | #include <asm/msr.h> |
38 | #include <asm/mtrr.h> | |
a49e3c7f | 39 | #include <asm/post.h> |
c53fd2bb | 40 | #include <asm/processor.h> |
0c24c9cc | 41 | #include <asm/processor-flags.h> |
3f5f18d1 | 42 | #include <asm/interrupt.h> |
5e2400e8 | 43 | #include <asm/tables.h> |
60a9b6bf | 44 | #include <linux/compiler.h> |
2262cfee | 45 | |
52f952bf BM |
46 | DECLARE_GLOBAL_DATA_PTR; |
47 | ||
52f952bf BM |
48 | static const char *const x86_vendor_name[] = { |
49 | [X86_VENDOR_INTEL] = "Intel", | |
50 | [X86_VENDOR_CYRIX] = "Cyrix", | |
51 | [X86_VENDOR_AMD] = "AMD", | |
52 | [X86_VENDOR_UMC] = "UMC", | |
53 | [X86_VENDOR_NEXGEN] = "NexGen", | |
54 | [X86_VENDOR_CENTAUR] = "Centaur", | |
55 | [X86_VENDOR_RISE] = "Rise", | |
56 | [X86_VENDOR_TRANSMETA] = "Transmeta", | |
57 | [X86_VENDOR_NSC] = "NSC", | |
58 | [X86_VENDOR_SIS] = "SiS", | |
59 | }; | |
60 | ||
f30fc4de GB |
61 | int __weak x86_cleanup_before_linux(void) |
62 | { | |
7949703a | 63 | #ifdef CONFIG_BOOTSTAGE_STASH |
ee2b2434 | 64 | bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH_ADDR, |
7949703a SG |
65 | CONFIG_BOOTSTAGE_STASH_SIZE); |
66 | #endif | |
67 | ||
f30fc4de GB |
68 | return 0; |
69 | } | |
70 | ||
d653244b GR |
71 | int x86_init_cache(void) |
72 | { | |
73 | enable_caches(); | |
0ea76e92 | 74 | |
2262cfee WD |
75 | return 0; |
76 | } | |
d653244b | 77 | int init_cache(void) __attribute__((weak, alias("x86_init_cache"))); |
2262cfee | 78 | |
54841ab5 | 79 | int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
2262cfee | 80 | { |
717979fd | 81 | printf("resetting ...\n"); |
dbf7115a GR |
82 | |
83 | /* wait 50 ms */ | |
84 | udelay(50000); | |
2262cfee WD |
85 | disable_interrupts(); |
86 | reset_cpu(0); | |
87 | ||
88 | /*NOTREACHED*/ | |
89 | return 0; | |
90 | } | |
91 | ||
717979fd | 92 | void flush_cache(unsigned long dummy1, unsigned long dummy2) |
2262cfee WD |
93 | { |
94 | asm("wbinvd\n"); | |
2262cfee | 95 | } |
3f5f18d1 | 96 | |
e1ffd817 | 97 | __weak void reset_cpu(ulong addr) |
3f5f18d1 | 98 | { |
ff6a8f3c | 99 | /* Do a hard reset through the chipset's reset control register */ |
2a605d4d | 100 | outb(SYS_RST | RST_CPU, IO_PORT_RESET); |
ff6a8f3c SG |
101 | for (;;) |
102 | cpu_hlt(); | |
103 | } | |
104 | ||
105 | void x86_full_reset(void) | |
106 | { | |
2a605d4d | 107 | outb(FULL_RST | SYS_RST | RST_CPU, IO_PORT_RESET); |
3f5f18d1 | 108 | } |
095593c0 | 109 | |
095593c0 SR |
110 | /* Define these functions to allow ehch-hcd to function */ |
111 | void flush_dcache_range(unsigned long start, unsigned long stop) | |
112 | { | |
113 | } | |
114 | ||
115 | void invalidate_dcache_range(unsigned long start, unsigned long stop) | |
116 | { | |
117 | } | |
89371409 SG |
118 | |
119 | void dcache_enable(void) | |
120 | { | |
121 | enable_caches(); | |
122 | } | |
123 | ||
124 | void dcache_disable(void) | |
125 | { | |
126 | disable_caches(); | |
127 | } | |
128 | ||
129 | void icache_enable(void) | |
130 | { | |
131 | } | |
132 | ||
133 | void icache_disable(void) | |
134 | { | |
135 | } | |
136 | ||
137 | int icache_status(void) | |
138 | { | |
139 | return 1; | |
140 | } | |
7bddac94 | 141 | |
52f952bf BM |
142 | const char *cpu_vendor_name(int vendor) |
143 | { | |
144 | const char *name; | |
145 | name = "<invalid cpu vendor>"; | |
146 | if ((vendor < (ARRAY_SIZE(x86_vendor_name))) && | |
147 | (x86_vendor_name[vendor] != 0)) | |
148 | name = x86_vendor_name[vendor]; | |
92cc94a1 | 149 | |
52f952bf | 150 | return name; |
92cc94a1 SG |
151 | } |
152 | ||
727c1a98 | 153 | char *cpu_get_name(char *name) |
92cc94a1 | 154 | { |
727c1a98 | 155 | unsigned int *name_as_ints = (unsigned int *)name; |
52f952bf | 156 | struct cpuid_result regs; |
727c1a98 | 157 | char *ptr; |
52f952bf | 158 | int i; |
92cc94a1 | 159 | |
727c1a98 | 160 | /* This bit adds up to 48 bytes */ |
52f952bf BM |
161 | for (i = 0; i < 3; i++) { |
162 | regs = cpuid(0x80000002 + i); | |
163 | name_as_ints[i * 4 + 0] = regs.eax; | |
164 | name_as_ints[i * 4 + 1] = regs.ebx; | |
165 | name_as_ints[i * 4 + 2] = regs.ecx; | |
166 | name_as_ints[i * 4 + 3] = regs.edx; | |
167 | } | |
727c1a98 | 168 | name[CPU_MAX_NAME_LEN - 1] = '\0'; |
92cc94a1 | 169 | |
52f952bf | 170 | /* Skip leading spaces. */ |
727c1a98 SG |
171 | ptr = name; |
172 | while (*ptr == ' ') | |
173 | ptr++; | |
52f952bf | 174 | |
727c1a98 | 175 | return ptr; |
92cc94a1 SG |
176 | } |
177 | ||
727c1a98 | 178 | int default_print_cpuinfo(void) |
92cc94a1 | 179 | { |
52f952bf BM |
180 | printf("CPU: %s, vendor %s, device %xh\n", |
181 | cpu_has_64bit() ? "x86_64" : "x86", | |
182 | cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device); | |
92cc94a1 | 183 | |
b727961b BM |
184 | #ifdef CONFIG_HAVE_ACPI_RESUME |
185 | debug("ACPI previous sleep state: %s\n", | |
186 | acpi_ss_string(gd->arch.prev_sleep_state)); | |
187 | #endif | |
188 | ||
92cc94a1 SG |
189 | return 0; |
190 | } | |
200182a7 | 191 | |
a49e3c7f SG |
192 | void show_boot_progress(int val) |
193 | { | |
a49e3c7f SG |
194 | outb(val, POST_PORT); |
195 | } | |
5e2400e8 BM |
196 | |
197 | #ifndef CONFIG_SYS_COREBOOT | |
1e2f7b9e BM |
198 | /* |
199 | * Implement a weak default function for boards that optionally | |
200 | * need to clean up the system before jumping to the kernel. | |
201 | */ | |
202 | __weak void board_final_cleanup(void) | |
203 | { | |
204 | } | |
205 | ||
5e2400e8 BM |
206 | int last_stage_init(void) |
207 | { | |
bffd7981 BM |
208 | board_final_cleanup(); |
209 | ||
3a34cae0 | 210 | #if CONFIG_HAVE_ACPI_RESUME |
0f4e2588 | 211 | struct acpi_fadt *fadt = acpi_find_fadt(); |
3a34cae0 | 212 | |
0f4e2588 BM |
213 | if (fadt != NULL && gd->arch.prev_sleep_state == ACPI_S3) |
214 | acpi_resume(fadt); | |
3a34cae0 BM |
215 | #endif |
216 | ||
5e2400e8 BM |
217 | write_tables(); |
218 | ||
219 | return 0; | |
220 | } | |
221 | #endif | |
bcb0c61e | 222 | |
afd5d50c | 223 | static int x86_init_cpus(void) |
bcb0c61e | 224 | { |
6e6f4ce4 BM |
225 | #ifdef CONFIG_SMP |
226 | debug("Init additional CPUs\n"); | |
227 | x86_mp_init(); | |
c77b8912 BM |
228 | #else |
229 | struct udevice *dev; | |
230 | ||
231 | /* | |
232 | * This causes the cpu-x86 driver to be probed. | |
233 | * We don't check return value here as we want to allow boards | |
234 | * which have not been converted to use cpu uclass driver to boot. | |
235 | */ | |
236 | uclass_first_device(UCLASS_CPU, &dev); | |
6e6f4ce4 BM |
237 | #endif |
238 | ||
bcb0c61e SG |
239 | return 0; |
240 | } | |
241 | ||
242 | int cpu_init_r(void) | |
243 | { | |
ac643e03 SG |
244 | struct udevice *dev; |
245 | int ret; | |
246 | ||
247 | if (!ll_boot_init()) | |
248 | return 0; | |
249 | ||
250 | ret = x86_init_cpus(); | |
251 | if (ret) | |
252 | return ret; | |
253 | ||
254 | /* | |
255 | * Set up the northbridge, PCH and LPC if available. Note that these | |
256 | * may have had some limited pre-relocation init if they were probed | |
257 | * before relocation, but this is post relocation. | |
258 | */ | |
259 | uclass_first_device(UCLASS_NORTHBRIDGE, &dev); | |
260 | uclass_first_device(UCLASS_PCH, &dev); | |
261 | uclass_first_device(UCLASS_LPC, &dev); | |
e49cceac | 262 | |
d8906c1f BM |
263 | /* Set up pin control if available */ |
264 | ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &dev); | |
265 | debug("%s, pinctrl=%p, ret=%d\n", __func__, dev, ret); | |
266 | ||
e49cceac | 267 | return 0; |
bcb0c61e | 268 | } |
0c2b7eef BM |
269 | |
270 | #ifndef CONFIG_EFI_STUB | |
271 | int reserve_arch(void) | |
272 | { | |
273 | #ifdef CONFIG_ENABLE_MRC_CACHE | |
d19c9074 BM |
274 | mrccache_reserve(); |
275 | #endif | |
276 | ||
277 | #ifdef CONFIG_SEABIOS | |
278 | high_table_reserve(); | |
0c2b7eef | 279 | #endif |
d19c9074 | 280 | |
5ae5aa93 BM |
281 | #ifdef CONFIG_HAVE_ACPI_RESUME |
282 | acpi_s3_reserve(); | |
283 | ||
284 | #ifdef CONFIG_HAVE_FSP | |
ba65808e BM |
285 | /* |
286 | * Save stack address to CMOS so that at next S3 boot, | |
287 | * we can use it as the stack address for fsp_contiue() | |
288 | */ | |
289 | fsp_save_s3_stack(); | |
5ae5aa93 BM |
290 | #endif /* CONFIG_HAVE_FSP */ |
291 | #endif /* CONFIG_HAVE_ACPI_RESUME */ | |
ba65808e | 292 | |
d19c9074 | 293 | return 0; |
0c2b7eef BM |
294 | } |
295 | #endif |