]>
Commit | Line | Data |
---|---|---|
d496162c SG |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* | |
3 | * Copyright 2019 Google LLC | |
4 | */ | |
5 | ||
6 | #include <common.h> | |
7 | #include <asm/io.h> | |
8 | #include <asm/cpu_common.h> | |
9 | #include <asm/fast_spi.h> | |
10 | #include <asm/pci.h> | |
11 | ||
12 | /* | |
13 | * Returns bios_start and fills in size of the BIOS region. | |
14 | */ | |
15 | static ulong fast_spi_get_bios_region(struct fast_spi_regs *regs, | |
16 | uint *bios_size) | |
17 | { | |
18 | ulong bios_start, bios_end; | |
19 | ||
20 | /* | |
21 | * BIOS_BFPREG provides info about BIOS-Flash Primary Region Base and | |
22 | * Limit. Base and Limit fields are in units of 4K. | |
23 | */ | |
24 | u32 val = readl(®s->bfp); | |
25 | ||
26 | bios_start = (val & SPIBAR_BFPREG_PRB_MASK) << 12; | |
27 | bios_end = (((val & SPIBAR_BFPREG_PRL_MASK) >> | |
28 | SPIBAR_BFPREG_PRL_SHIFT) + 1) << 12; | |
29 | *bios_size = bios_end - bios_start; | |
30 | ||
31 | return bios_start; | |
32 | } | |
33 | ||
34 | int fast_spi_get_bios_mmap(pci_dev_t pdev, ulong *map_basep, uint *map_sizep, | |
35 | uint *offsetp) | |
36 | { | |
37 | struct fast_spi_regs *regs; | |
38 | ulong bar, base, mmio_base; | |
39 | ||
40 | /* Special case to find mapping without probing the device */ | |
41 | pci_x86_read_config(pdev, PCI_BASE_ADDRESS_0, &bar, PCI_SIZE_32); | |
42 | mmio_base = bar & PCI_BASE_ADDRESS_MEM_MASK; | |
43 | regs = (struct fast_spi_regs *)mmio_base; | |
44 | base = fast_spi_get_bios_region(regs, map_sizep); | |
45 | *map_basep = (u32)-*map_sizep - base; | |
46 | *offsetp = base; | |
47 | ||
48 | return 0; | |
49 | } | |
50 | ||
51 | int fast_spi_early_init(pci_dev_t pdev, ulong mmio_base) | |
52 | { | |
53 | /* Program Temporary BAR for SPI */ | |
54 | pci_x86_write_config(pdev, PCI_BASE_ADDRESS_0, | |
55 | mmio_base | PCI_BASE_ADDRESS_SPACE_MEMORY, | |
56 | PCI_SIZE_32); | |
57 | ||
58 | /* Enable Bus Master and MMIO Space */ | |
59 | pci_x86_clrset_config(pdev, PCI_COMMAND, 0, PCI_COMMAND_MASTER | | |
60 | PCI_COMMAND_MEMORY, PCI_SIZE_8); | |
61 | ||
62 | /* | |
63 | * Disable the BIOS write protect so write commands are allowed. | |
64 | * Enable Prefetching and caching. | |
65 | */ | |
66 | pci_x86_clrset_config(pdev, SPIBAR_BIOS_CONTROL, | |
67 | SPIBAR_BIOS_CONTROL_EISS | | |
68 | SPIBAR_BIOS_CONTROL_CACHE_DISABLE, | |
69 | SPIBAR_BIOS_CONTROL_WPD | | |
70 | SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE, PCI_SIZE_8); | |
71 | ||
72 | return 0; | |
73 | } |