[people/ms/u-boot.git] / arch / x86 / cpu / interrupts.c

/*
 * (C) Copyright 2008-2011
 * Graeme Russ, <graeme.russ@gmail.com>
 *
 * (C) Copyright 2002
 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
 *
 * Portions of this file are derived from the Linux kernel source
 *  Copyright (C) 1991, 1992  Linus Torvalds
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <dm.h>
#include <asm/cache.h>
#include <asm/control_regs.h>
#include <asm/interrupt.h>
#include <asm/io.h>
#include <asm/processor-flags.h>
#include <linux/compiler.h>
#include <asm/msr.h>
#include <asm/processor.h>
#include <asm/u-boot-x86.h>
#include <asm/i8259.h>

DECLARE_GLOBAL_DATA_PTR;

#define DECLARE_INTERRUPT(x) \
	".globl irq_"#x"\n" \
	".hidden irq_"#x"\n" \
	".type irq_"#x", @function\n" \
	"irq_"#x":\n" \
	"pushl $"#x"\n" \
	"jmp irq_common_entry\n"

static char *exceptions[] = {
	"Divide Error",
	"Debug",
	"NMI Interrupt",
	"Breakpoint",
	"Overflow",
	"BOUND Range Exceeded",
	"Invalid Opcode (Undefined Opcode)",
	"Device Not Avaiable (No Math Coprocessor)",
	"Double Fault",
	"Coprocessor Segment Overrun",
	"Invalid TSS",
	"Segment Not Present",
	"Stack Segment Fault",
	"General Protection",
	"Page Fault",
	"Reserved",
	"x87 FPU Floating-Point Error",
	"Alignment Check",
	"Machine Check",
	"SIMD Floating-Point Exception",
	"Virtualization Exception",
	"Reserved",
	"Reserved",
	"Reserved",
	"Reserved",
	"Reserved",
	"Reserved",
	"Reserved",
	"Reserved",
	"Reserved",
	"Reserved",
	"Reserved"
};

static void dump_regs(struct irq_regs *regs)
{
	unsigned long cs, eip, eflags;
	unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L;
	unsigned long d0, d1, d2, d3, d6, d7;
	unsigned long sp;

	/*
	 * Some exceptions cause an error code to be saved on the current stack
	 * after the EIP value. We should extract CS/EIP/EFLAGS from different
	 * position on the stack based on the exception number.
	 */
	switch (regs->irq_id) {
	case EXC_DF:
	case EXC_TS:
	case EXC_NP:
	case EXC_SS:
	case EXC_GP:
	case EXC_PF:
	case EXC_AC:
		cs = regs->context.ctx2.xcs;
		eip = regs->context.ctx2.eip;
		eflags = regs->context.ctx2.eflags;
		/* We should fix up the ESP due to error code */
		regs->esp += 4;
		break;
	default:
		cs = regs->context.ctx1.xcs;
		eip = regs->context.ctx1.eip;
		eflags = regs->context.ctx1.eflags;
		break;
	}

	printf("EIP: %04x:[<%08lx>] EFLAGS: %08lx\n",
			(u16)cs, eip, eflags);
	if (gd->flags & GD_FLG_RELOC)
		printf("Original EIP :[<%08lx>]\n", eip - gd->reloc_off);

	printf("EAX: %08lx EBX: %08lx ECX: %08lx EDX: %08lx\n",
		regs->eax, regs->ebx, regs->ecx, regs->edx);
	printf("ESI: %08lx EDI: %08lx EBP: %08lx ESP: %08lx\n",
		regs->esi, regs->edi, regs->ebp, regs->esp);
	printf(" DS: %04x ES: %04x FS: %04x GS: %04x SS: %04x\n",
	       (u16)regs->xds, (u16)regs->xes, (u16)regs->xfs,
	       (u16)regs->xgs, (u16)regs->xss);

	cr0 = read_cr0();
	cr2 = read_cr2();
	cr3 = read_cr3();
	cr4 = read_cr4();

	printf("CR0: %08lx CR2: %08lx CR3: %08lx CR4: %08lx\n",
			cr0, cr2, cr3, cr4);

	d0 = get_debugreg(0);
	d1 = get_debugreg(1);
	d2 = get_debugreg(2);
	d3 = get_debugreg(3);

	printf("DR0: %08lx DR1: %08lx DR2: %08lx DR3: %08lx\n",
			d0, d1, d2, d3);

	d6 = get_debugreg(6);
	d7 = get_debugreg(7);
	printf("DR6: %08lx DR7: %08lx\n",
			d6, d7);

	printf("Stack:\n");
	sp = regs->esp;

	sp += 64;

	while (sp > (regs->esp - 16)) {
		if (sp == regs->esp)
			printf("--->");
		else
			printf("    ");
		printf("0x%8.8lx : 0x%8.8lx\n", sp, (ulong)readl(sp));
		sp -= 4;
	}
}

static void do_exception(struct irq_regs *regs)
{
	printf("%s\n", exceptions[regs->irq_id]);
	dump_regs(regs);
	hang();
}

struct idt_entry {
	u16	base_low;
	u16	selector;
	u8	res;
	u8	access;
	u16	base_high;
} __packed;

struct desc_ptr {
	unsigned short size;
	unsigned long address;
} __packed;

struct idt_entry idt[256] __aligned(16);

struct desc_ptr idt_ptr;

static inline void load_idt(const struct desc_ptr *dtr)
{
	asm volatile("cs lidt %0" : : "m" (*dtr));
}

void set_vector(u8 intnum, void *routine)
{
	idt[intnum].base_high = (u16)((u32)(routine) >> 16);
	idt[intnum].base_low = (u16)((u32)(routine) & 0xffff);
}

/*
 * Ideally these would be defined static to avoid a checkpatch warning, but
 * the compiler cannot see them in the inline asm and complains that they
 * aren't defined
 */
void irq_0(void);
void irq_1(void);

int cpu_init_interrupts(void)
{
	int i;

	int irq_entry_size = irq_1 - irq_0;
	void *irq_entry = (void *)irq_0;

	/* Setup the IDT */
	for (i = 0; i < 256; i++) {
		idt[i].access = 0x8e;
		idt[i].res = 0;
		idt[i].selector = X86_GDT_ENTRY_32BIT_CS * X86_GDT_ENTRY_SIZE;
		set_vector(i, irq_entry);
		irq_entry += irq_entry_size;
	}

	idt_ptr.size = 256 * 8 - 1;
	idt_ptr.address = (unsigned long) idt;

	load_idt(&idt_ptr);

	return 0;
}

void *x86_get_idt(void)
{
	return &idt_ptr;
}

void __do_irq(int irq)
{
	printf("Unhandled IRQ : %d\n", irq);
}
void do_irq(int irq) __attribute__((weak, alias("__do_irq")));

void enable_interrupts(void)
{
	asm("sti\n");
}

int disable_interrupts(void)
{
	long flags;

	asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags) : );

	return flags & X86_EFLAGS_IF;
}

int interrupt_init(void)
{
	struct udevice *dev;
	int ret;

	/* Try to set up the interrupt router, but don't require one */
	ret = uclass_first_device_err(UCLASS_IRQ, &dev);
	if (ret && ret != -ENODEV)
		return ret;

	/*
	 * When running as an EFI application we are not in control of
	 * interrupts and should leave them alone.
	 */
#ifndef CONFIG_EFI_APP
	/* Just in case... */
	disable_interrupts();

#ifdef CONFIG_I8259_PIC
	/* Initialize the master/slave i8259 pic */
	i8259_init();
#endif

	/* Initialize core interrupt and exception functionality of CPU */
	cpu_init_interrupts();

	/*
	 * It is now safe to enable interrupts.
	 *
	 * TODO(sjg@chromium.org): But we don't handle these correctly when
	 * booted from EFI.
	 */
	if (ll_boot_init())
		enable_interrupts();
#endif

	return 0;
}

/* IRQ Low-Level Service Routine */
void irq_llsr(struct irq_regs *regs)
{
	/*
	 * For detailed description of each exception, refer to:
	 * Intel® 64 and IA-32 Architectures Software Developer's Manual
	 * Volume 1: Basic Architecture
	 * Order Number: 253665-029US, November 2008
	 * Table 6-1. Exceptions and Interrupts
	 */
	if (regs->irq_id < 32) {
		/* Architecture defined exception */
		do_exception(regs);
	} else {
		/* Hardware or User IRQ */
		do_irq(regs->irq_id);
	}
}

/*
 * OK - This looks really horrible, but it serves a purpose - It helps create
 * fully relocatable code.
 *  - The call to irq_llsr will be a relative jump
 *  - The IRQ entries will be guaranteed to be in order
 *  Interrupt entries are now very small (a push and a jump) but they are
 *  now slower (all registers pushed on stack which provides complete
 *  crash dumps in the low level handlers
 *
 * Interrupt Entry Point:
 *  - Interrupt has caused eflags, CS and EIP to be pushed
 *  - Interrupt Vector Handler has pushed orig_eax
 *  - pt_regs.esp needs to be adjusted by 40 bytes:
 *      12 bytes pushed by CPU (EFLAGSF, CS, EIP)
 *      4 bytes pushed by vector handler (irq_id)
 *      24 bytes pushed before SP (SS, GS, FS, ES, DS, EAX)
 *      NOTE: Only longs are pushed on/popped off the stack!
 */
asm(".globl irq_common_entry\n" \
	".hidden irq_common_entry\n" \
	".type irq_common_entry, @function\n" \
	"irq_common_entry:\n" \
	"cld\n" \
	"pushl %ss\n" \
	"pushl %gs\n" \
	"pushl %fs\n" \
	"pushl %es\n" \
	"pushl %ds\n" \
	"pushl %eax\n" \
	"movl  %esp, %eax\n" \
	"addl  $40, %eax\n" \
	"pushl %eax\n" \
	"pushl %ebp\n" \
	"pushl %edi\n" \
	"pushl %esi\n" \
	"pushl %edx\n" \
	"pushl %ecx\n" \
	"pushl %ebx\n" \
	"mov   %esp, %eax\n" \
	"call irq_llsr\n" \
	"popl %ebx\n" \
	"popl %ecx\n" \
	"popl %edx\n" \
	"popl %esi\n" \
	"popl %edi\n" \
	"popl %ebp\n" \
	"popl %eax\n" \
	"popl %eax\n" \
	"popl %ds\n" \
	"popl %es\n" \
	"popl %fs\n" \
	"popl %gs\n" \
	"popl %ss\n" \
	"add  $4, %esp\n" \
	"iret\n" \
	DECLARE_INTERRUPT(0) \
	DECLARE_INTERRUPT(1) \
	DECLARE_INTERRUPT(2) \
	DECLARE_INTERRUPT(3) \
	DECLARE_INTERRUPT(4) \
	DECLARE_INTERRUPT(5) \
	DECLARE_INTERRUPT(6) \
	DECLARE_INTERRUPT(7) \
	DECLARE_INTERRUPT(8) \
	DECLARE_INTERRUPT(9) \
	DECLARE_INTERRUPT(10) \
	DECLARE_INTERRUPT(11) \
	DECLARE_INTERRUPT(12) \
	DECLARE_INTERRUPT(13) \
	DECLARE_INTERRUPT(14) \
	DECLARE_INTERRUPT(15) \
	DECLARE_INTERRUPT(16) \
	DECLARE_INTERRUPT(17) \
	DECLARE_INTERRUPT(18) \
	DECLARE_INTERRUPT(19) \
	DECLARE_INTERRUPT(20) \
	DECLARE_INTERRUPT(21) \
	DECLARE_INTERRUPT(22) \
	DECLARE_INTERRUPT(23) \
	DECLARE_INTERRUPT(24) \
	DECLARE_INTERRUPT(25) \
	DECLARE_INTERRUPT(26) \
	DECLARE_INTERRUPT(27) \
	DECLARE_INTERRUPT(28) \
	DECLARE_INTERRUPT(29) \
	DECLARE_INTERRUPT(30) \
	DECLARE_INTERRUPT(31) \
	DECLARE_INTERRUPT(32) \
	DECLARE_INTERRUPT(33) \
	DECLARE_INTERRUPT(34) \
	DECLARE_INTERRUPT(35) \
	DECLARE_INTERRUPT(36) \
	DECLARE_INTERRUPT(37) \
	DECLARE_INTERRUPT(38) \
	DECLARE_INTERRUPT(39) \
	DECLARE_INTERRUPT(40) \
	DECLARE_INTERRUPT(41) \
	DECLARE_INTERRUPT(42) \
	DECLARE_INTERRUPT(43) \
	DECLARE_INTERRUPT(44) \
	DECLARE_INTERRUPT(45) \
	DECLARE_INTERRUPT(46) \
	DECLARE_INTERRUPT(47) \
	DECLARE_INTERRUPT(48) \
	DECLARE_INTERRUPT(49) \
	DECLARE_INTERRUPT(50) \
	DECLARE_INTERRUPT(51) \
	DECLARE_INTERRUPT(52) \
	DECLARE_INTERRUPT(53) \
	DECLARE_INTERRUPT(54) \
	DECLARE_INTERRUPT(55) \
	DECLARE_INTERRUPT(56) \
	DECLARE_INTERRUPT(57) \
	DECLARE_INTERRUPT(58) \
	DECLARE_INTERRUPT(59) \
	DECLARE_INTERRUPT(60) \
	DECLARE_INTERRUPT(61) \
	DECLARE_INTERRUPT(62) \
	DECLARE_INTERRUPT(63) \
	DECLARE_INTERRUPT(64) \
	DECLARE_INTERRUPT(65) \
	DECLARE_INTERRUPT(66) \
	DECLARE_INTERRUPT(67) \
	DECLARE_INTERRUPT(68) \
	DECLARE_INTERRUPT(69) \
	DECLARE_INTERRUPT(70) \
	DECLARE_INTERRUPT(71) \
	DECLARE_INTERRUPT(72) \
	DECLARE_INTERRUPT(73) \
	DECLARE_INTERRUPT(74) \
	DECLARE_INTERRUPT(75) \
	DECLARE_INTERRUPT(76) \
	DECLARE_INTERRUPT(77) \
	DECLARE_INTERRUPT(78) \
	DECLARE_INTERRUPT(79) \
	DECLARE_INTERRUPT(80) \
	DECLARE_INTERRUPT(81) \
	DECLARE_INTERRUPT(82) \
	DECLARE_INTERRUPT(83) \
	DECLARE_INTERRUPT(84) \
	DECLARE_INTERRUPT(85) \
	DECLARE_INTERRUPT(86) \
	DECLARE_INTERRUPT(87) \
	DECLARE_INTERRUPT(88) \
	DECLARE_INTERRUPT(89) \
	DECLARE_INTERRUPT(90) \
	DECLARE_INTERRUPT(91) \
	DECLARE_INTERRUPT(92) \
	DECLARE_INTERRUPT(93) \
	DECLARE_INTERRUPT(94) \
	DECLARE_INTERRUPT(95) \
	DECLARE_INTERRUPT(97) \
	DECLARE_INTERRUPT(96) \
	DECLARE_INTERRUPT(98) \
	DECLARE_INTERRUPT(99) \
	DECLARE_INTERRUPT(100) \
	DECLARE_INTERRUPT(101) \
	DECLARE_INTERRUPT(102) \
	DECLARE_INTERRUPT(103) \
	DECLARE_INTERRUPT(104) \
	DECLARE_INTERRUPT(105) \
	DECLARE_INTERRUPT(106) \
	DECLARE_INTERRUPT(107) \
	DECLARE_INTERRUPT(108) \
	DECLARE_INTERRUPT(109) \
	DECLARE_INTERRUPT(110) \
	DECLARE_INTERRUPT(111) \
	DECLARE_INTERRUPT(112) \
	DECLARE_INTERRUPT(113) \
	DECLARE_INTERRUPT(114) \
	DECLARE_INTERRUPT(115) \
	DECLARE_INTERRUPT(116) \
	DECLARE_INTERRUPT(117) \
	DECLARE_INTERRUPT(118) \
	DECLARE_INTERRUPT(119) \
	DECLARE_INTERRUPT(120) \
	DECLARE_INTERRUPT(121) \
	DECLARE_INTERRUPT(122) \
	DECLARE_INTERRUPT(123) \
	DECLARE_INTERRUPT(124) \
	DECLARE_INTERRUPT(125) \
	DECLARE_INTERRUPT(126) \
	DECLARE_INTERRUPT(127) \
	DECLARE_INTERRUPT(128) \
	DECLARE_INTERRUPT(129) \
	DECLARE_INTERRUPT(130) \
	DECLARE_INTERRUPT(131) \
	DECLARE_INTERRUPT(132) \
	DECLARE_INTERRUPT(133) \
	DECLARE_INTERRUPT(134) \
	DECLARE_INTERRUPT(135) \
	DECLARE_INTERRUPT(136) \
	DECLARE_INTERRUPT(137) \
	DECLARE_INTERRUPT(138) \
	DECLARE_INTERRUPT(139) \
	DECLARE_INTERRUPT(140) \
	DECLARE_INTERRUPT(141) \
	DECLARE_INTERRUPT(142) \
	DECLARE_INTERRUPT(143) \
	DECLARE_INTERRUPT(144) \
	DECLARE_INTERRUPT(145) \
	DECLARE_INTERRUPT(146) \
	DECLARE_INTERRUPT(147) \
	DECLARE_INTERRUPT(148) \
	DECLARE_INTERRUPT(149) \
	DECLARE_INTERRUPT(150) \
	DECLARE_INTERRUPT(151) \
	DECLARE_INTERRUPT(152) \
	DECLARE_INTERRUPT(153) \
	DECLARE_INTERRUPT(154) \
	DECLARE_INTERRUPT(155) \
	DECLARE_INTERRUPT(156) \
	DECLARE_INTERRUPT(157) \
	DECLARE_INTERRUPT(158) \
	DECLARE_INTERRUPT(159) \
	DECLARE_INTERRUPT(160) \
	DECLARE_INTERRUPT(161) \
	DECLARE_INTERRUPT(162) \
	DECLARE_INTERRUPT(163) \
	DECLARE_INTERRUPT(164) \
	DECLARE_INTERRUPT(165) \
	DECLARE_INTERRUPT(166) \
	DECLARE_INTERRUPT(167) \
	DECLARE_INTERRUPT(168) \
	DECLARE_INTERRUPT(169) \
	DECLARE_INTERRUPT(170) \
	DECLARE_INTERRUPT(171) \
	DECLARE_INTERRUPT(172) \
	DECLARE_INTERRUPT(173) \
	DECLARE_INTERRUPT(174) \
	DECLARE_INTERRUPT(175) \
	DECLARE_INTERRUPT(176) \
	DECLARE_INTERRUPT(177) \
	DECLARE_INTERRUPT(178) \
	DECLARE_INTERRUPT(179) \
	DECLARE_INTERRUPT(180) \
	DECLARE_INTERRUPT(181) \
	DECLARE_INTERRUPT(182) \
	DECLARE_INTERRUPT(183) \
	DECLARE_INTERRUPT(184) \
	DECLARE_INTERRUPT(185) \
	DECLARE_INTERRUPT(186) \
	DECLARE_INTERRUPT(187) \
	DECLARE_INTERRUPT(188) \
	DECLARE_INTERRUPT(189) \
	DECLARE_INTERRUPT(190) \
	DECLARE_INTERRUPT(191) \
	DECLARE_INTERRUPT(192) \
	DECLARE_INTERRUPT(193) \
	DECLARE_INTERRUPT(194) \
	DECLARE_INTERRUPT(195) \
	DECLARE_INTERRUPT(196) \
	DECLARE_INTERRUPT(197) \
	DECLARE_INTERRUPT(198) \
	DECLARE_INTERRUPT(199) \
	DECLARE_INTERRUPT(200) \
	DECLARE_INTERRUPT(201) \
	DECLARE_INTERRUPT(202) \
	DECLARE_INTERRUPT(203) \
	DECLARE_INTERRUPT(204) \
	DECLARE_INTERRUPT(205) \
	DECLARE_INTERRUPT(206) \
	DECLARE_INTERRUPT(207) \
	DECLARE_INTERRUPT(208) \
	DECLARE_INTERRUPT(209) \
	DECLARE_INTERRUPT(210) \
	DECLARE_INTERRUPT(211) \
	DECLARE_INTERRUPT(212) \
	DECLARE_INTERRUPT(213) \
	DECLARE_INTERRUPT(214) \
	DECLARE_INTERRUPT(215) \
	DECLARE_INTERRUPT(216) \
	DECLARE_INTERRUPT(217) \
	DECLARE_INTERRUPT(218) \
	DECLARE_INTERRUPT(219) \
	DECLARE_INTERRUPT(220) \
	DECLARE_INTERRUPT(221) \
	DECLARE_INTERRUPT(222) \
	DECLARE_INTERRUPT(223) \
	DECLARE_INTERRUPT(224) \
	DECLARE_INTERRUPT(225) \
	DECLARE_INTERRUPT(226) \
	DECLARE_INTERRUPT(227) \
	DECLARE_INTERRUPT(228) \
	DECLARE_INTERRUPT(229) \
	DECLARE_INTERRUPT(230) \
	DECLARE_INTERRUPT(231) \
	DECLARE_INTERRUPT(232) \
	DECLARE_INTERRUPT(233) \
	DECLARE_INTERRUPT(234) \
	DECLARE_INTERRUPT(235) \
	DECLARE_INTERRUPT(236) \
	DECLARE_INTERRUPT(237) \
	DECLARE_INTERRUPT(238) \
	DECLARE_INTERRUPT(239) \
	DECLARE_INTERRUPT(240) \
	DECLARE_INTERRUPT(241) \
	DECLARE_INTERRUPT(242) \
	DECLARE_INTERRUPT(243) \
	DECLARE_INTERRUPT(244) \
	DECLARE_INTERRUPT(245) \
	DECLARE_INTERRUPT(246) \
	DECLARE_INTERRUPT(247) \
	DECLARE_INTERRUPT(248) \
	DECLARE_INTERRUPT(249) \
	DECLARE_INTERRUPT(250) \
	DECLARE_INTERRUPT(251) \
	DECLARE_INTERRUPT(252) \
	DECLARE_INTERRUPT(253) \
	DECLARE_INTERRUPT(254) \
	DECLARE_INTERRUPT(255));
Commit	Line	Data
2262cfee	1	/*
dbf7115a GR	2	* (C) Copyright 2008-2011
dbf7115a GR	3	* Graeme Russ, <graeme.russ@gmail.com>
564a9984	4	*
2262cfee	5	* (C) Copyright 2002
fa82f871	6	* Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
2262cfee	7	*
433ff2bd GR	8	* Portions of this file are derived from the Linux kernel source
	9	* Copyright (C) 1991, 1992 Linus Torvalds
	10	*
1a459660	11	* SPDX-License-Identifier: GPL-2.0+
2262cfee WD	12	*/
	13
	14	#include <common.h>
12d6929e	15	#include <dm.h>
095593c0 SR	16	#include <asm/cache.h>
095593c0 SR	17	#include <asm/control_regs.h>
9933d609	18	#include <asm/interrupt.h>
ca56a4ce	19	#include <asm/io.h>
0c24c9cc	20	#include <asm/processor-flags.h>
717979fd	21	#include <linux/compiler.h>
7c71034d	22	#include <asm/msr.h>
8aba36d8	23	#include <asm/processor.h>
7c71034d	24	#include <asm/u-boot-x86.h>
1dae2e0e	25	#include <asm/i8259.h>
2262cfee	26
7282d834 SG	27	DECLARE_GLOBAL_DATA_PTR;
7282d834 SG	28
564a9984 GR	29	#define DECLARE_INTERRUPT(x) \
564a9984 GR	30	".globl irq_"#x"\n" \
0fc1b49e GR	31	".hidden irq_"#x"\n" \
0fc1b49e GR	32	".type irq_"#x", @function\n" \
564a9984	33	"irq_"#x":\n" \
564a9984 GR	34	"pushl $"#x"\n" \
564a9984 GR	35	"jmp irq_common_entry\n"
2262cfee	36
3ccd49ca BM	37	static char *exceptions[] = {
	38	"Divide Error",
	39	"Debug",
	40	"NMI Interrupt",
	41	"Breakpoint",
	42	"Overflow",
	43	"BOUND Range Exceeded",
	44	"Invalid Opcode (Undefined Opcode)",
	45	"Device Not Avaiable (No Math Coprocessor)",
	46	"Double Fault",
	47	"Coprocessor Segment Overrun",
	48	"Invalid TSS",
	49	"Segment Not Present",
	50	"Stack Segment Fault",
8aba36d8	51	"General Protection",
3ccd49ca BM	52	"Page Fault",
	53	"Reserved",
	54	"x87 FPU Floating-Point Error",
	55	"Alignment Check",
	56	"Machine Check",
	57	"SIMD Floating-Point Exception",
	58	"Virtualization Exception",
	59	"Reserved",
	60	"Reserved",
	61	"Reserved",
	62	"Reserved",
	63	"Reserved",
	64	"Reserved",
	65	"Reserved",
	66	"Reserved",
	67	"Reserved",
	68	"Reserved",
	69	"Reserved"
	70	};
	71
e1ffd817	72	static void dump_regs(struct irq_regs *regs)
433ff2bd	73	{
013cf483	74	unsigned long cs, eip, eflags;
433ff2bd GR	75	unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L;
433ff2bd GR	76	unsigned long d0, d1, d2, d3, d6, d7;
ca56a4ce	77	unsigned long sp;
433ff2bd	78
013cf483 BM	79	/*
	80	* Some exceptions cause an error code to be saved on the current stack
	81	* after the EIP value. We should extract CS/EIP/EFLAGS from different
	82	* position on the stack based on the exception number.
	83	*/
	84	switch (regs->irq_id) {
	85	case EXC_DF:
	86	case EXC_TS:
	87	case EXC_NP:
	88	case EXC_SS:
	89	case EXC_GP:
	90	case EXC_PF:
	91	case EXC_AC:
	92	cs = regs->context.ctx2.xcs;
	93	eip = regs->context.ctx2.eip;
	94	eflags = regs->context.ctx2.eflags;
	95	/* We should fix up the ESP due to error code */
	96	regs->esp += 4;
	97	break;
	98	default:
	99	cs = regs->context.ctx1.xcs;
	100	eip = regs->context.ctx1.eip;
	101	eflags = regs->context.ctx1.eflags;
	102	break;
	103	}
	104
433ff2bd	105	printf("EIP: %04x:[<%08lx>] EFLAGS: %08lx\n",
013cf483	106	(u16)cs, eip, eflags);
7399515d SG	107	if (gd->flags & GD_FLG_RELOC)
7399515d SG	108	printf("Original EIP :[<%08lx>]\n", eip - gd->reloc_off);
433ff2bd GR	109
	110	printf("EAX: %08lx EBX: %08lx ECX: %08lx EDX: %08lx\n",
	111	regs->eax, regs->ebx, regs->ecx, regs->edx);
	112	printf("ESI: %08lx EDI: %08lx EBP: %08lx ESP: %08lx\n",
	113	regs->esi, regs->edi, regs->ebp, regs->esp);
	114	printf(" DS: %04x ES: %04x FS: %04x GS: %04x SS: %04x\n",
717979fd GR	115	(u16)regs->xds, (u16)regs->xes, (u16)regs->xfs,
717979fd GR	116	(u16)regs->xgs, (u16)regs->xss);
433ff2bd GR	117
	118	cr0 = read_cr0();
	119	cr2 = read_cr2();
	120	cr3 = read_cr3();
	121	cr4 = read_cr4();
	122
	123	printf("CR0: %08lx CR2: %08lx CR3: %08lx CR4: %08lx\n",
	124	cr0, cr2, cr3, cr4);
	125
	126	d0 = get_debugreg(0);
	127	d1 = get_debugreg(1);
	128	d2 = get_debugreg(2);
	129	d3 = get_debugreg(3);
	130
	131	printf("DR0: %08lx DR1: %08lx DR2: %08lx DR3: %08lx\n",
	132	d0, d1, d2, d3);
	133
	134	d6 = get_debugreg(6);
	135	d7 = get_debugreg(7);
	136	printf("DR6: %08lx DR7: %08lx\n",
	137	d6, d7);
ca56a4ce GR	138
	139	printf("Stack:\n");
	140	sp = regs->esp;
	141
	142	sp += 64;
	143
	144	while (sp > (regs->esp - 16)) {
	145	if (sp == regs->esp)
	146	printf("--->");
	147	else
	148	printf(" ");
	149	printf("0x%8.8lx : 0x%8.8lx\n", sp, (ulong)readl(sp));
	150	sp -= 4;
	151	}
433ff2bd GR	152	}
433ff2bd GR	153
3ccd49ca BM	154	static void do_exception(struct irq_regs *regs)
	155	{
	156	printf("%s\n", exceptions[regs->irq_id]);
	157	dump_regs(regs);
	158	hang();
	159	}
	160
2262cfee WD	161	struct idt_entry {
	162	u16 base_low;
	163	u16 selector;
	164	u8 res;
	165	u8 access;
	166	u16 base_high;
717979fd	167	} __packed;
2262cfee	168
564a9984 GR	169	struct desc_ptr {
	170	unsigned short size;
	171	unsigned long address;
717979fd	172	} __packed;
2262cfee	173
58c7a675	174	struct idt_entry idt[256] __aligned(16);
2262cfee	175
564a9984	176	struct desc_ptr idt_ptr;
2262cfee	177
564a9984 GR	178	static inline void load_idt(const struct desc_ptr *dtr)
564a9984 GR	179	{
717979fd	180	asm volatile("cs lidt %0" : : "m" (*dtr));
564a9984	181	}
2262cfee	182
abf0cd3d	183	void set_vector(u8 intnum, void *routine)
2262cfee	184	{
1c409bc7 GR	185	idt[intnum].base_high = (u16)((u32)(routine) >> 16);
1c409bc7 GR	186	idt[intnum].base_low = (u16)((u32)(routine) & 0xffff);
2262cfee WD	187	}
2262cfee WD	188
717979fd GR	189	/*
	190	* Ideally these would be defined static to avoid a checkpatch warning, but
	191	* the compiler cannot see them in the inline asm and complains that they
	192	* aren't defined
	193	*/
564a9984 GR	194	void irq_0(void);
564a9984 GR	195	void irq_1(void);
2262cfee	196
abf0cd3d	197	int cpu_init_interrupts(void)
2262cfee WD	198	{
2262cfee WD	199	int i;
8bde7f77	200
564a9984 GR	201	int irq_entry_size = irq_1 - irq_0;
	202	void irq_entry = (void )irq_0;
	203
2262cfee	204	/* Setup the IDT */
717979fd	205	for (i = 0; i < 256; i++) {
2262cfee	206	idt[i].access = 0x8e;
8bde7f77	207	idt[i].res = 0;
8aba36d8	208	idt[i].selector = X86_GDT_ENTRY_32BIT_CS * X86_GDT_ENTRY_SIZE;
564a9984 GR	209	set_vector(i, irq_entry);
564a9984 GR	210	irq_entry += irq_entry_size;
8bde7f77 WD	211	}
8bde7f77 WD	212
8aba36d8	213	idt_ptr.size = 256 * 8 - 1;
564a9984	214	idt_ptr.address = (unsigned long) idt;
564a9984 GR	215
564a9984 GR	216	load_idt(&idt_ptr);
8bde7f77	217
2262cfee WD	218	return 0;
	219	}
	220
6f41e0e7 SG	221	void *x86_get_idt(void)
	222	{
	223	return &idt_ptr;
	224	}
	225
564a9984 GR	226	void __do_irq(int irq)
	227	{
	228	printf("Unhandled IRQ : %d\n", irq);
	229	}
	230	void do_irq(int irq) __attribute__((weak, alias("__do_irq")));
	231
2262cfee WD	232	void enable_interrupts(void)
	233	{
	234	asm("sti\n");
	235	}
	236
	237	int disable_interrupts(void)
	238	{
	239	long flags;
8bde7f77	240
2262cfee	241	asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags) : );
8bde7f77	242
717979fd	243	return flags & X86_EFLAGS_IF;
2262cfee	244	}
564a9984	245
1dae2e0e BM	246	int interrupt_init(void)
1dae2e0e BM	247	{
12d6929e SG	248	struct udevice *dev;
	249	int ret;
	250
	251	/* Try to set up the interrupt router, but don't require one */
3f603cbb	252	ret = uclass_first_device_err(UCLASS_IRQ, &dev);
12d6929e SG	253	if (ret && ret != -ENODEV)
	254	return ret;
	255
3dcdd17b BS	256	/*
	257	* When running as an EFI application we are not in control of
	258	* interrupts and should leave them alone.
	259	*/
	260	#ifndef CONFIG_EFI_APP
1dae2e0e BM	261	/* Just in case... */
	262	disable_interrupts();
	263
da3fe247	264	#ifdef CONFIG_I8259_PIC
1dae2e0e BM	265	/* Initialize the master/slave i8259 pic */
	266	i8259_init();
	267	#endif
	268
	269	/* Initialize core interrupt and exception functionality of CPU */
	270	cpu_init_interrupts();
	271
e49cceac SG	272	/*
	273	* It is now safe to enable interrupts.
	274	*
	275	* TODO(sjg@chromium.org): But we don't handle these correctly when
	276	* booted from EFI.
	277	*/
	278	if (ll_boot_init())
	279	enable_interrupts();
3dcdd17b	280	#endif
1dae2e0e BM	281
	282	return 0;
	283	}
	284
564a9984	285	/* IRQ Low-Level Service Routine */
7228efa3	286	void irq_llsr(struct irq_regs *regs)
564a9984 GR	287	{
	288	/*
	289	* For detailed description of each exception, refer to:
fa82f871	290	* Intel® 64 and IA-32 Architectures Software Developer's Manual
564a9984 GR	291	* Volume 1: Basic Architecture
	292	* Order Number: 253665-029US, November 2008
	293	* Table 6-1. Exceptions and Interrupts
	294	*/
3ccd49ca BM	295	if (regs->irq_id < 32) {
	296	/* Architecture defined exception */
	297	do_exception(regs);
	298	} else {
564a9984	299	/* Hardware or User IRQ */
7228efa3	300	do_irq(regs->irq_id);
564a9984 GR	301	}
	302	}
	303
	304	/*
	305	* OK - This looks really horrible, but it serves a purpose - It helps create
	306	* fully relocatable code.
	307	* - The call to irq_llsr will be a relative jump
	308	* - The IRQ entries will be guaranteed to be in order
433ff2bd GR	309	* Interrupt entries are now very small (a push and a jump) but they are
	310	* now slower (all registers pushed on stack which provides complete
	311	* crash dumps in the low level handlers
7228efa3 GR	312	*
	313	* Interrupt Entry Point:
	314	* - Interrupt has caused eflags, CS and EIP to be pushed
	315	* - Interrupt Vector Handler has pushed orig_eax
	316	* - pt_regs.esp needs to be adjusted by 40 bytes:
	317	* 12 bytes pushed by CPU (EFLAGSF, CS, EIP)
	318	* 4 bytes pushed by vector handler (irq_id)
	319	* 24 bytes pushed before SP (SS, GS, FS, ES, DS, EAX)
	320	* NOTE: Only longs are pushed on/popped off the stack!
564a9984 GR	321	*/
564a9984 GR	322	asm(".globl irq_common_entry\n" \
0fc1b49e GR	323	".hidden irq_common_entry\n" \
0fc1b49e GR	324	".type irq_common_entry, @function\n" \
564a9984	325	"irq_common_entry:\n" \
433ff2bd	326	"cld\n" \
7228efa3	327	"pushl %ss\n" \
433ff2bd GR	328	"pushl %gs\n" \
	329	"pushl %fs\n" \
	330	"pushl %es\n" \
	331	"pushl %ds\n" \
	332	"pushl %eax\n" \
7228efa3 GR	333	"movl %esp, %eax\n" \
	334	"addl $40, %eax\n" \
	335	"pushl %eax\n" \
433ff2bd GR	336	"pushl %ebp\n" \
	337	"pushl %edi\n" \
	338	"pushl %esi\n" \
	339	"pushl %edx\n" \
	340	"pushl %ecx\n" \
	341	"pushl %ebx\n" \
	342	"mov %esp, %eax\n" \
564a9984	343	"call irq_llsr\n" \
433ff2bd GR	344	"popl %ebx\n" \
	345	"popl %ecx\n" \
	346	"popl %edx\n" \
	347	"popl %esi\n" \
	348	"popl %edi\n" \
	349	"popl %ebp\n" \
	350	"popl %eax\n" \
7228efa3	351	"popl %eax\n" \
433ff2bd GR	352	"popl %ds\n" \
	353	"popl %es\n" \
	354	"popl %fs\n" \
	355	"popl %gs\n" \
7228efa3	356	"popl %ss\n" \
433ff2bd	357	"add $4, %esp\n" \
564a9984 GR	358	"iret\n" \
	359	DECLARE_INTERRUPT(0) \
	360	DECLARE_INTERRUPT(1) \
	361	DECLARE_INTERRUPT(2) \
	362	DECLARE_INTERRUPT(3) \
	363	DECLARE_INTERRUPT(4) \
	364	DECLARE_INTERRUPT(5) \
	365	DECLARE_INTERRUPT(6) \
	366	DECLARE_INTERRUPT(7) \
	367	DECLARE_INTERRUPT(8) \
	368	DECLARE_INTERRUPT(9) \
	369	DECLARE_INTERRUPT(10) \
	370	DECLARE_INTERRUPT(11) \
	371	DECLARE_INTERRUPT(12) \
	372	DECLARE_INTERRUPT(13) \
	373	DECLARE_INTERRUPT(14) \
	374	DECLARE_INTERRUPT(15) \
	375	DECLARE_INTERRUPT(16) \
	376	DECLARE_INTERRUPT(17) \
	377	DECLARE_INTERRUPT(18) \
	378	DECLARE_INTERRUPT(19) \
	379	DECLARE_INTERRUPT(20) \
	380	DECLARE_INTERRUPT(21) \
	381	DECLARE_INTERRUPT(22) \
	382	DECLARE_INTERRUPT(23) \
	383	DECLARE_INTERRUPT(24) \
	384	DECLARE_INTERRUPT(25) \
	385	DECLARE_INTERRUPT(26) \
	386	DECLARE_INTERRUPT(27) \
	387	DECLARE_INTERRUPT(28) \
	388	DECLARE_INTERRUPT(29) \
	389	DECLARE_INTERRUPT(30) \
	390	DECLARE_INTERRUPT(31) \
	391	DECLARE_INTERRUPT(32) \
	392	DECLARE_INTERRUPT(33) \
	393	DECLARE_INTERRUPT(34) \
	394	DECLARE_INTERRUPT(35) \
	395	DECLARE_INTERRUPT(36) \
	396	DECLARE_INTERRUPT(37) \
	397	DECLARE_INTERRUPT(38) \
	398	DECLARE_INTERRUPT(39) \
	399	DECLARE_INTERRUPT(40) \
	400	DECLARE_INTERRUPT(41) \
	401	DECLARE_INTERRUPT(42) \
	402	DECLARE_INTERRUPT(43) \
	403	DECLARE_INTERRUPT(44) \
	404	DECLARE_INTERRUPT(45) \
	405	DECLARE_INTERRUPT(46) \
	406	DECLARE_INTERRUPT(47) \
	407	DECLARE_INTERRUPT(48) \
	408	DECLARE_INTERRUPT(49) \
	409	DECLARE_INTERRUPT(50) \
	410	DECLARE_INTERRUPT(51) \
	411	DECLARE_INTERRUPT(52) \
	412	DECLARE_INTERRUPT(53) \
	413	DECLARE_INTERRUPT(54) \
	414	DECLARE_INTERRUPT(55) \
	415	DECLARE_INTERRUPT(56) \
	416	DECLARE_INTERRUPT(57) \
	417	DECLARE_INTERRUPT(58) \
	418	DECLARE_INTERRUPT(59) \
	419	DECLARE_INTERRUPT(60) \
	420	DECLARE_INTERRUPT(61) \
	421	DECLARE_INTERRUPT(62) \
422	DECLARE_INTERRUPT(63) \
423	DECLARE_INTERRUPT(64) \
424	DECLARE_INTERRUPT(65) \
425	DECLARE_INTERRUPT(66) \
426	DECLARE_INTERRUPT(67) \
427	DECLARE_INTERRUPT(68) \
428	DECLARE_INTERRUPT(69) \
429	DECLARE_INTERRUPT(70) \
430	DECLARE_INTERRUPT(71) \
431	DECLARE_INTERRUPT(72) \
432	DECLARE_INTERRUPT(73) \
433	DECLARE_INTERRUPT(74) \
434	DECLARE_INTERRUPT(75) \
435	DECLARE_INTERRUPT(76) \
436	DECLARE_INTERRUPT(77) \
437	DECLARE_INTERRUPT(78) \
438	DECLARE_INTERRUPT(79) \
439	DECLARE_INTERRUPT(80) \
440	DECLARE_INTERRUPT(81) \
441	DECLARE_INTERRUPT(82) \
442	DECLARE_INTERRUPT(83) \
443	DECLARE_INTERRUPT(84) \
444	DECLARE_INTERRUPT(85) \
445	DECLARE_INTERRUPT(86) \
446	DECLARE_INTERRUPT(87) \
447	DECLARE_INTERRUPT(88) \
448	DECLARE_INTERRUPT(89) \
449	DECLARE_INTERRUPT(90) \
450	DECLARE_INTERRUPT(91) \
451	DECLARE_INTERRUPT(92) \
452	DECLARE_INTERRUPT(93) \
453	DECLARE_INTERRUPT(94) \
454	DECLARE_INTERRUPT(95) \
455	DECLARE_INTERRUPT(97) \
456	DECLARE_INTERRUPT(96) \
457	DECLARE_INTERRUPT(98) \
458	DECLARE_INTERRUPT(99) \
459	DECLARE_INTERRUPT(100) \
460	DECLARE_INTERRUPT(101) \
461	DECLARE_INTERRUPT(102) \
462	DECLARE_INTERRUPT(103) \
463	DECLARE_INTERRUPT(104) \
464	DECLARE_INTERRUPT(105) \
465	DECLARE_INTERRUPT(106) \
466	DECLARE_INTERRUPT(107) \
467	DECLARE_INTERRUPT(108) \
468	DECLARE_INTERRUPT(109) \
469	DECLARE_INTERRUPT(110) \
470	DECLARE_INTERRUPT(111) \
471	DECLARE_INTERRUPT(112) \
472	DECLARE_INTERRUPT(113) \
473	DECLARE_INTERRUPT(114) \
474	DECLARE_INTERRUPT(115) \
475	DECLARE_INTERRUPT(116) \
476	DECLARE_INTERRUPT(117) \
477	DECLARE_INTERRUPT(118) \
478	DECLARE_INTERRUPT(119) \
479	DECLARE_INTERRUPT(120) \
480	DECLARE_INTERRUPT(121) \
481	DECLARE_INTERRUPT(122) \
482	DECLARE_INTERRUPT(123) \
483	DECLARE_INTERRUPT(124) \
484	DECLARE_INTERRUPT(125) \
485	DECLARE_INTERRUPT(126) \
486	DECLARE_INTERRUPT(127) \
487	DECLARE_INTERRUPT(128) \
488	DECLARE_INTERRUPT(129) \
489	DECLARE_INTERRUPT(130) \
490	DECLARE_INTERRUPT(131) \
491	DECLARE_INTERRUPT(132) \
492	DECLARE_INTERRUPT(133) \
493	DECLARE_INTERRUPT(134) \
494	DECLARE_INTERRUPT(135) \
495	DECLARE_INTERRUPT(136) \
496	DECLARE_INTERRUPT(137) \
497	DECLARE_INTERRUPT(138) \
498	DECLARE_INTERRUPT(139) \
499	DECLARE_INTERRUPT(140) \
500	DECLARE_INTERRUPT(141) \
501	DECLARE_INTERRUPT(142) \
502	DECLARE_INTERRUPT(143) \
503	DECLARE_INTERRUPT(144) \
504	DECLARE_INTERRUPT(145) \
505	DECLARE_INTERRUPT(146) \
506	DECLARE_INTERRUPT(147) \
507	DECLARE_INTERRUPT(148) \
508	DECLARE_INTERRUPT(149) \
509	DECLARE_INTERRUPT(150) \
510	DECLARE_INTERRUPT(151) \
511	DECLARE_INTERRUPT(152) \
512	DECLARE_INTERRUPT(153) \
513	DECLARE_INTERRUPT(154) \
514	DECLARE_INTERRUPT(155) \
515	DECLARE_INTERRUPT(156) \
516	DECLARE_INTERRUPT(157) \
517	DECLARE_INTERRUPT(158) \
518	DECLARE_INTERRUPT(159) \
519	DECLARE_INTERRUPT(160) \
520	DECLARE_INTERRUPT(161) \
521	DECLARE_INTERRUPT(162) \
522	DECLARE_INTERRUPT(163) \
523	DECLARE_INTERRUPT(164) \
524	DECLARE_INTERRUPT(165) \
525	DECLARE_INTERRUPT(166) \
526	DECLARE_INTERRUPT(167) \
527	DECLARE_INTERRUPT(168) \
528	DECLARE_INTERRUPT(169) \
529	DECLARE_INTERRUPT(170) \
530	DECLARE_INTERRUPT(171) \
531	DECLARE_INTERRUPT(172) \
532	DECLARE_INTERRUPT(173) \
533	DECLARE_INTERRUPT(174) \
534	DECLARE_INTERRUPT(175) \
535	DECLARE_INTERRUPT(176) \
536	DECLARE_INTERRUPT(177) \
537	DECLARE_INTERRUPT(178) \
538	DECLARE_INTERRUPT(179) \
539	DECLARE_INTERRUPT(180) \
540	DECLARE_INTERRUPT(181) \
541	DECLARE_INTERRUPT(182) \
542	DECLARE_INTERRUPT(183) \
543	DECLARE_INTERRUPT(184) \
544	DECLARE_INTERRUPT(185) \
545	DECLARE_INTERRUPT(186) \
546	DECLARE_INTERRUPT(187) \
547	DECLARE_INTERRUPT(188) \
548	DECLARE_INTERRUPT(189) \
549	DECLARE_INTERRUPT(190) \
550	DECLARE_INTERRUPT(191) \
551	DECLARE_INTERRUPT(192) \
552	DECLARE_INTERRUPT(193) \
553	DECLARE_INTERRUPT(194) \
554	DECLARE_INTERRUPT(195) \
555	DECLARE_INTERRUPT(196) \
556	DECLARE_INTERRUPT(197) \
557	DECLARE_INTERRUPT(198) \
558	DECLARE_INTERRUPT(199) \
559	DECLARE_INTERRUPT(200) \
560	DECLARE_INTERRUPT(201) \
561	DECLARE_INTERRUPT(202) \
562	DECLARE_INTERRUPT(203) \
563	DECLARE_INTERRUPT(204) \
564	DECLARE_INTERRUPT(205) \
565	DECLARE_INTERRUPT(206) \
566	DECLARE_INTERRUPT(207) \
567	DECLARE_INTERRUPT(208) \
568	DECLARE_INTERRUPT(209) \
569	DECLARE_INTERRUPT(210) \
570	DECLARE_INTERRUPT(211) \
571	DECLARE_INTERRUPT(212) \
572	DECLARE_INTERRUPT(213) \
573	DECLARE_INTERRUPT(214) \
574	DECLARE_INTERRUPT(215) \
575	DECLARE_INTERRUPT(216) \
576	DECLARE_INTERRUPT(217) \
577	DECLARE_INTERRUPT(218) \
578	DECLARE_INTERRUPT(219) \
579	DECLARE_INTERRUPT(220) \
580	DECLARE_INTERRUPT(221) \
581	DECLARE_INTERRUPT(222) \
582	DECLARE_INTERRUPT(223) \
583	DECLARE_INTERRUPT(224) \
584	DECLARE_INTERRUPT(225) \
585	DECLARE_INTERRUPT(226) \
586	DECLARE_INTERRUPT(227) \
587	DECLARE_INTERRUPT(228) \
588	DECLARE_INTERRUPT(229) \
589	DECLARE_INTERRUPT(230) \
590	DECLARE_INTERRUPT(231) \
591	DECLARE_INTERRUPT(232) \
592	DECLARE_INTERRUPT(233) \
593	DECLARE_INTERRUPT(234) \
594	DECLARE_INTERRUPT(235) \
595	DECLARE_INTERRUPT(236) \
596	DECLARE_INTERRUPT(237) \
597	DECLARE_INTERRUPT(238) \
598	DECLARE_INTERRUPT(239) \
599	DECLARE_INTERRUPT(240) \
600	DECLARE_INTERRUPT(241) \
601	DECLARE_INTERRUPT(242) \
602	DECLARE_INTERRUPT(243) \
603	DECLARE_INTERRUPT(244) \
604	DECLARE_INTERRUPT(245) \
605	DECLARE_INTERRUPT(246) \
606	DECLARE_INTERRUPT(247) \
607	DECLARE_INTERRUPT(248) \
608	DECLARE_INTERRUPT(249) \
609	DECLARE_INTERRUPT(250) \
610	DECLARE_INTERRUPT(251) \
611	DECLARE_INTERRUPT(252) \
612	DECLARE_INTERRUPT(253) \
613	DECLARE_INTERRUPT(254) \
614	DECLARE_INTERRUPT(255));