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x86: Add a x86_ prefix to the x86-specific PCI functions
[people/ms/u-boot.git] / arch / x86 / cpu / ivybridge / gma.c
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effcf067
SG		 1/*
2 * From Coreboot file of the same name
3 *
4 * Copyright (C) 2011 Chromium OS Authors
5 *
6 * SPDX-License-Identifier: GPL-2.0
7 */
8
9#include <common.h>
10#include <bios_emul.h>
11#include <errno.h>
12#include <fdtdec.h>
13#include <pci_rom.h>
14#include <asm/io.h>
9818a00e 15#include <asm/mtrr.h>
effcf067
SG		 16#include <asm/pci.h>
17#include <asm/arch/pch.h>
18#include <asm/arch/sandybridge.h>
d19ee5c2 19#include <linux/kconfig.h>
effcf067
SG		 20
21struct gt_powermeter {
22 u16 reg;
23 u32 value;
24};
25
26static const struct gt_powermeter snb_pm_gt1[] = {
27 { 0xa200, 0xcc000000 },
28 { 0xa204, 0x07000040 },
29 { 0xa208, 0x0000fe00 },
30 { 0xa20c, 0x00000000 },
31 { 0xa210, 0x17000000 },
32 { 0xa214, 0x00000021 },
33 { 0xa218, 0x0817fe19 },
34 { 0xa21c, 0x00000000 },
35 { 0xa220, 0x00000000 },
36 { 0xa224, 0xcc000000 },
37 { 0xa228, 0x07000040 },
38 { 0xa22c, 0x0000fe00 },
39 { 0xa230, 0x00000000 },
40 { 0xa234, 0x17000000 },
41 { 0xa238, 0x00000021 },
42 { 0xa23c, 0x0817fe19 },
43 { 0xa240, 0x00000000 },
44 { 0xa244, 0x00000000 },
45 { 0xa248, 0x8000421e },
46 { 0 }
47};
48
49static const struct gt_powermeter snb_pm_gt2[] = {
50 { 0xa200, 0x330000a6 },
51 { 0xa204, 0x402d0031 },
52 { 0xa208, 0x00165f83 },
53 { 0xa20c, 0xf1000000 },
54 { 0xa210, 0x00000000 },
55 { 0xa214, 0x00160016 },
56 { 0xa218, 0x002a002b },
57 { 0xa21c, 0x00000000 },
58 { 0xa220, 0x00000000 },
59 { 0xa224, 0x330000a6 },
60 { 0xa228, 0x402d0031 },
61 { 0xa22c, 0x00165f83 },
62 { 0xa230, 0xf1000000 },
63 { 0xa234, 0x00000000 },
64 { 0xa238, 0x00160016 },
65 { 0xa23c, 0x002a002b },
66 { 0xa240, 0x00000000 },
67 { 0xa244, 0x00000000 },
68 { 0xa248, 0x8000421e },
69 { 0 }
70};
71
72static const struct gt_powermeter ivb_pm_gt1[] = {
73 { 0xa800, 0x00000000 },
74 { 0xa804, 0x00021c00 },
75 { 0xa808, 0x00000403 },
76 { 0xa80c, 0x02001700 },
77 { 0xa810, 0x05000200 },
78 { 0xa814, 0x00000000 },
79 { 0xa818, 0x00690500 },
80 { 0xa81c, 0x0000007f },
81 { 0xa820, 0x01002501 },
82 { 0xa824, 0x00000300 },
83 { 0xa828, 0x01000331 },
84 { 0xa82c, 0x0000000c },
85 { 0xa830, 0x00010016 },
86 { 0xa834, 0x01100101 },
87 { 0xa838, 0x00010103 },
88 { 0xa83c, 0x00041300 },
89 { 0xa840, 0x00000b30 },
90 { 0xa844, 0x00000000 },
91 { 0xa848, 0x7f000000 },
92 { 0xa84c, 0x05000008 },
93 { 0xa850, 0x00000001 },
94 { 0xa854, 0x00000004 },
95 { 0xa858, 0x00000007 },
96 { 0xa85c, 0x00000000 },
97 { 0xa860, 0x00010000 },
98 { 0xa248, 0x0000221e },
99 { 0xa900, 0x00000000 },
100 { 0xa904, 0x00001c00 },
101 { 0xa908, 0x00000000 },
102 { 0xa90c, 0x06000000 },
103 { 0xa910, 0x09000200 },
104 { 0xa914, 0x00000000 },
105 { 0xa918, 0x00590000 },
106 { 0xa91c, 0x00000000 },
107 { 0xa920, 0x04002501 },
108 { 0xa924, 0x00000100 },
109 { 0xa928, 0x03000410 },
110 { 0xa92c, 0x00000000 },
111 { 0xa930, 0x00020000 },
112 { 0xa934, 0x02070106 },
113 { 0xa938, 0x00010100 },
114 { 0xa93c, 0x00401c00 },
115 { 0xa940, 0x00000000 },
116 { 0xa944, 0x00000000 },
117 { 0xa948, 0x10000e00 },
118 { 0xa94c, 0x02000004 },
119 { 0xa950, 0x00000001 },
120 { 0xa954, 0x00000004 },
121 { 0xa960, 0x00060000 },
122 { 0xaa3c, 0x00001c00 },
123 { 0xaa54, 0x00000004 },
124 { 0xaa60, 0x00060000 },
125 { 0 }
126};
127
128static const struct gt_powermeter ivb_pm_gt2[] = {
129 { 0xa800, 0x10000000 },
130 { 0xa804, 0x00033800 },
131 { 0xa808, 0x00000902 },
132 { 0xa80c, 0x0c002f00 },
133 { 0xa810, 0x12000400 },
134 { 0xa814, 0x00000000 },
135 { 0xa818, 0x00d20800 },
136 { 0xa81c, 0x00000002 },
137 { 0xa820, 0x03004b02 },
138 { 0xa824, 0x00000600 },
139 { 0xa828, 0x07000773 },
140 { 0xa82c, 0x00000000 },
141 { 0xa830, 0x00010032 },
142 { 0xa834, 0x1520040d },
143 { 0xa838, 0x00020105 },
144 { 0xa83c, 0x00083700 },
145 { 0xa840, 0x0000151d },
146 { 0xa844, 0x00000000 },
147 { 0xa848, 0x20001b00 },
148 { 0xa84c, 0x0a000010 },
149 { 0xa850, 0x00000000 },
150 { 0xa854, 0x00000008 },
151 { 0xa858, 0x00000008 },
152 { 0xa85c, 0x00000000 },
153 { 0xa860, 0x00020000 },
154 { 0xa248, 0x0000221e },
155 { 0xa900, 0x00000000 },
156 { 0xa904, 0x00003500 },
157 { 0xa908, 0x00000000 },
158 { 0xa90c, 0x0c000000 },
159 { 0xa910, 0x12000500 },
160 { 0xa914, 0x00000000 },
161 { 0xa918, 0x00b20000 },
162 { 0xa91c, 0x00000000 },
163 { 0xa920, 0x08004b02 },
164 { 0xa924, 0x00000200 },
165 { 0xa928, 0x07000820 },
166 { 0xa92c, 0x00000000 },
167 { 0xa930, 0x00030000 },
168 { 0xa934, 0x050f020d },
169 { 0xa938, 0x00020300 },
170 { 0xa93c, 0x00903900 },
171 { 0xa940, 0x00000000 },
172 { 0xa944, 0x00000000 },
173 { 0xa948, 0x20001b00 },
174 { 0xa94c, 0x0a000010 },
175 { 0xa950, 0x00000000 },
176 { 0xa954, 0x00000008 },
177 { 0xa960, 0x00110000 },
178 { 0xaa3c, 0x00003900 },
179 { 0xaa54, 0x00000008 },
180 { 0xaa60, 0x00110000 },
181 { 0 }
182};
183
184static const struct gt_powermeter ivb_pm_gt2_17w[] = {
185 { 0xa800, 0x20000000 },
186 { 0xa804, 0x000e3800 },
187 { 0xa808, 0x00000806 },
188 { 0xa80c, 0x0c002f00 },
189 { 0xa810, 0x0c000800 },
190 { 0xa814, 0x00000000 },
191 { 0xa818, 0x00d20d00 },
192 { 0xa81c, 0x000000ff },
193 { 0xa820, 0x03004b02 },
194 { 0xa824, 0x00000600 },
195 { 0xa828, 0x07000773 },
196 { 0xa82c, 0x00000000 },
197 { 0xa830, 0x00020032 },
198 { 0xa834, 0x1520040d },
199 { 0xa838, 0x00020105 },
200 { 0xa83c, 0x00083700 },
201 { 0xa840, 0x000016ff },
202 { 0xa844, 0x00000000 },
203 { 0xa848, 0xff000000 },
204 { 0xa84c, 0x0a000010 },
205 { 0xa850, 0x00000002 },
206 { 0xa854, 0x00000008 },
207 { 0xa858, 0x0000000f },
208 { 0xa85c, 0x00000000 },
209 { 0xa860, 0x00020000 },
210 { 0xa248, 0x0000221e },
211 { 0xa900, 0x00000000 },
212 { 0xa904, 0x00003800 },
213 { 0xa908, 0x00000000 },
214 { 0xa90c, 0x0c000000 },
215 { 0xa910, 0x12000800 },
216 { 0xa914, 0x00000000 },
217 { 0xa918, 0x00b20000 },
218 { 0xa91c, 0x00000000 },
219 { 0xa920, 0x08004b02 },
220 { 0xa924, 0x00000300 },
221 { 0xa928, 0x01000820 },
222 { 0xa92c, 0x00000000 },
223 { 0xa930, 0x00030000 },
224 { 0xa934, 0x15150406 },
225 { 0xa938, 0x00020300 },
226 { 0xa93c, 0x00903900 },
227 { 0xa940, 0x00000000 },
228 { 0xa944, 0x00000000 },
229 { 0xa948, 0x20001b00 },
230 { 0xa94c, 0x0a000010 },
231 { 0xa950, 0x00000000 },
232 { 0xa954, 0x00000008 },
233 { 0xa960, 0x00110000 },
234 { 0xaa3c, 0x00003900 },
235 { 0xaa54, 0x00000008 },
236 { 0xaa60, 0x00110000 },
237 { 0 }
238};
239
240static const struct gt_powermeter ivb_pm_gt2_35w[] = {
241 { 0xa800, 0x00000000 },
242 { 0xa804, 0x00030400 },
243 { 0xa808, 0x00000806 },
244 { 0xa80c, 0x0c002f00 },
245 { 0xa810, 0x0c000300 },
246 { 0xa814, 0x00000000 },
247 { 0xa818, 0x00d20d00 },
248 { 0xa81c, 0x000000ff },
249 { 0xa820, 0x03004b02 },
250 { 0xa824, 0x00000600 },
251 { 0xa828, 0x07000773 },
252 { 0xa82c, 0x00000000 },
253 { 0xa830, 0x00020032 },
254 { 0xa834, 0x1520040d },
255 { 0xa838, 0x00020105 },
256 { 0xa83c, 0x00083700 },
257 { 0xa840, 0x000016ff },
258 { 0xa844, 0x00000000 },
259 { 0xa848, 0xff000000 },
260 { 0xa84c, 0x0a000010 },
261 { 0xa850, 0x00000001 },
262 { 0xa854, 0x00000008 },
263 { 0xa858, 0x00000008 },
264 { 0xa85c, 0x00000000 },
265 { 0xa860, 0x00020000 },
266 { 0xa248, 0x0000221e },
267 { 0xa900, 0x00000000 },
268 { 0xa904, 0x00003800 },
269 { 0xa908, 0x00000000 },
270 { 0xa90c, 0x0c000000 },
271 { 0xa910, 0x12000800 },
272 { 0xa914, 0x00000000 },
273 { 0xa918, 0x00b20000 },
274 { 0xa91c, 0x00000000 },
275 { 0xa920, 0x08004b02 },
276 { 0xa924, 0x00000300 },
277 { 0xa928, 0x01000820 },
278 { 0xa92c, 0x00000000 },
279 { 0xa930, 0x00030000 },
280 { 0xa934, 0x15150406 },
281 { 0xa938, 0x00020300 },
282 { 0xa93c, 0x00903900 },
283 { 0xa940, 0x00000000 },
284 { 0xa944, 0x00000000 },
285 { 0xa948, 0x20001b00 },
286 { 0xa94c, 0x0a000010 },
287 { 0xa950, 0x00000000 },
288 { 0xa954, 0x00000008 },
289 { 0xa960, 0x00110000 },
290 { 0xaa3c, 0x00003900 },
291 { 0xaa54, 0x00000008 },
292 { 0xaa60, 0x00110000 },
293 { 0 }
294};
295
296/*
297 * Some vga option roms are used for several chipsets but they only have one
298 * PCI ID in their header. If we encounter such an option rom, we need to do
299 * the mapping ourselves.
300 */
301
302u32 map_oprom_vendev(u32 vendev)
303{
304 u32 new_vendev = vendev;
305
306 switch (vendev) {
307 case 0x80860102: /* GT1 Desktop */
308 case 0x8086010a: /* GT1 Server */
309 case 0x80860112: /* GT2 Desktop */
310 case 0x80860116: /* GT2 Mobile */
311 case 0x80860122: /* GT2 Desktop >=1.3GHz */
312 case 0x80860126: /* GT2 Mobile >=1.3GHz */
313 case 0x80860156: /* IVB */
314 case 0x80860166: /* IVB */
315 /* Set to GT1 Mobile */
316 new_vendev = 0x80860106;
317 break;
318 }
319
320 return new_vendev;
321}
322
323static inline u32 gtt_read(void *bar, u32 reg)
324{
325 return readl(bar + reg);
326}
327
328static inline void gtt_write(void *bar, u32 reg, u32 data)
329{
330 writel(data, bar + reg);
331}
332
333static void gtt_write_powermeter(void *bar, const struct gt_powermeter *pm)
334{
335 for (; pm && pm->reg; pm++)
336 gtt_write(bar, pm->reg, pm->value);
337}
338
339#define GTT_RETRY 1000
340static int gtt_poll(void *bar, u32 reg, u32 mask, u32 value)
341{
342 unsigned try = GTT_RETRY;
343 u32 data;
344
345 while (try--) {
346 data = gtt_read(bar, reg);
347 if ((data & mask) == value)
348 return 1;
349 udelay(10);
350 }
351
352 printf("GT init timeout\n");
353 return 0;
354}
355
356static int gma_pm_init_pre_vbios(void *gtt_bar)
357{
358 u32 reg32;
359
360 debug("GT Power Management Init, silicon = %#x\n",
361 bridge_silicon_revision());
362
363 if (bridge_silicon_revision() < IVB_STEP_C0) {
364 /* 1: Enable force wake */
365 gtt_write(gtt_bar, 0xa18c, 0x00000001);
366 gtt_poll(gtt_bar, 0x130090, (1 << 0), (1 << 0));
367 } else {
368 gtt_write(gtt_bar, 0xa180, 1 << 5);
369 gtt_write(gtt_bar, 0xa188, 0xffff0001);
370 gtt_poll(gtt_bar, 0x130040, (1 << 0), (1 << 0));
371 }
372
373 if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
374 /* 1d: Set GTT+0x42004 [15:14]=11 (SnB C1+) */
375 reg32 = gtt_read(gtt_bar, 0x42004);
376 reg32 |= (1 << 14) | (1 << 15);
377 gtt_write(gtt_bar, 0x42004, reg32);
378 }
379
380 if (bridge_silicon_revision() >= IVB_STEP_A0) {
381 /* Display Reset Acknowledge Settings */
382 reg32 = gtt_read(gtt_bar, 0x45010);
383 reg32 |= (1 << 1) | (1 << 0);
384 gtt_write(gtt_bar, 0x45010, reg32);
385 }
386
387 /* 2: Get GT SKU from GTT+0x911c[13] */
388 reg32 = gtt_read(gtt_bar, 0x911c);
389 if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
390 if (reg32 & (1 << 13)) {
391 debug("SNB GT1 Power Meter Weights\n");
392 gtt_write_powermeter(gtt_bar, snb_pm_gt1);
393 } else {
394 debug("SNB GT2 Power Meter Weights\n");
395 gtt_write_powermeter(gtt_bar, snb_pm_gt2);
396 }
397 } else {
398 u32 unit = readl(MCHBAR_REG(0x5938)) & 0xf;
399
400 if (reg32 & (1 << 13)) {
401 /* GT1 SKU */
402 debug("IVB GT1 Power Meter Weights\n");
403 gtt_write_powermeter(gtt_bar, ivb_pm_gt1);
404 } else {
405 /* GT2 SKU */
406 u32 tdp = readl(MCHBAR_REG(0x5930)) & 0x7fff;
407 tdp /= (1 << unit);
408
409 if (tdp <= 17) {
410 /* <=17W ULV */
411 debug("IVB GT2 17W Power Meter Weights\n");
412 gtt_write_powermeter(gtt_bar, ivb_pm_gt2_17w);
413 } else if ((tdp >= 25) && (tdp <= 35)) {
414 /* 25W-35W */
415 debug("IVB GT2 25W-35W Power Meter Weights\n");
416 gtt_write_powermeter(gtt_bar, ivb_pm_gt2_35w);
417 } else {
418 /* All others */
419 debug("IVB GT2 35W Power Meter Weights\n");
420 gtt_write_powermeter(gtt_bar, ivb_pm_gt2_35w);
421 }
422 }
423 }
424
425 /* 3: Gear ratio map */
426 gtt_write(gtt_bar, 0xa004, 0x00000010);
427
428 /* 4: GFXPAUSE */
429 gtt_write(gtt_bar, 0xa000, 0x00070020);
430
431 /* 5: Dynamic EU trip control */
432 gtt_write(gtt_bar, 0xa080, 0x00000004);
433
434 /* 6: ECO bits */
435 reg32 = gtt_read(gtt_bar, 0xa180);
436 reg32 |= (1 << 26) | (1 << 31);
437 /* (bit 20=1 for SNB step D1+ / IVB A0+) */
438 if (bridge_silicon_revision() >= SNB_STEP_D1)
439 reg32 |= (1 << 20);
440 gtt_write(gtt_bar, 0xa180, reg32);
441
442 /* 6a: for SnB step D2+ only */
443 if (((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) &&
444 (bridge_silicon_revision() >= SNB_STEP_D2)) {
445 reg32 = gtt_read(gtt_bar, 0x9400);
446 reg32 |= (1 << 7);
447 gtt_write(gtt_bar, 0x9400, reg32);
448
449 reg32 = gtt_read(gtt_bar, 0x941c);
450 reg32 &= 0xf;
451 reg32 |= (1 << 1);
452 gtt_write(gtt_bar, 0x941c, reg32);
453 gtt_poll(gtt_bar, 0x941c, (1 << 1), (0 << 1));
454 }
455
456 if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) {
457 reg32 = gtt_read(gtt_bar, 0x907c);
458 reg32 |= (1 << 16);
459 gtt_write(gtt_bar, 0x907c, reg32);
460
461 /* 6b: Clocking reset controls */
462 gtt_write(gtt_bar, 0x9424, 0x00000001);
463 } else {
464 /* 6b: Clocking reset controls */
465 gtt_write(gtt_bar, 0x9424, 0x00000000);
466 }
467
468 /* 7 */
469 if (gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31))) {
470 gtt_write(gtt_bar, 0x138128, 0x00000029); /* Mailbox Data */
471 /* Mailbox Cmd for RC6 VID */
472 gtt_write(gtt_bar, 0x138124, 0x80000004);
473 if (gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31)))
474 gtt_write(gtt_bar, 0x138124, 0x8000000a);
475 gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31));
476 }
477
478 /* 8 */
479 gtt_write(gtt_bar, 0xa090, 0x00000000); /* RC Control */
480 gtt_write(gtt_bar, 0xa098, 0x03e80000); /* RC1e Wake Rate Limit */
481 gtt_write(gtt_bar, 0xa09c, 0x0028001e); /* RC6/6p Wake Rate Limit */
482 gtt_write(gtt_bar, 0xa0a0, 0x0000001e); /* RC6pp Wake Rate Limit */
483 gtt_write(gtt_bar, 0xa0a8, 0x0001e848); /* RC Evaluation Interval */
484 gtt_write(gtt_bar, 0xa0ac, 0x00000019); /* RC Idle Hysteresis */
485
486 /* 9 */
487 gtt_write(gtt_bar, 0x2054, 0x0000000a); /* Render Idle Max Count */
488 gtt_write(gtt_bar, 0x12054, 0x0000000a); /* Video Idle Max Count */
489 gtt_write(gtt_bar, 0x22054, 0x0000000a); /* Blitter Idle Max Count */
490
491 /* 10 */
492 gtt_write(gtt_bar, 0xa0b0, 0x00000000); /* Unblock Ack to Busy */
493 gtt_write(gtt_bar, 0xa0b4, 0x000003e8); /* RC1e Threshold */
494 gtt_write(gtt_bar, 0xa0b8, 0x0000c350); /* RC6 Threshold */
495 gtt_write(gtt_bar, 0xa0bc, 0x000186a0); /* RC6p Threshold */
496 gtt_write(gtt_bar, 0xa0c0, 0x0000fa00); /* RC6pp Threshold */
497
498 /* 11 */
499 gtt_write(gtt_bar, 0xa010, 0x000f4240); /* RP Down Timeout */
500 gtt_write(gtt_bar, 0xa014, 0x12060000); /* RP Interrupt Limits */
501 gtt_write(gtt_bar, 0xa02c, 0x00015f90); /* RP Up Threshold */
502 gtt_write(gtt_bar, 0xa030, 0x000186a0); /* RP Down Threshold */
503 gtt_write(gtt_bar, 0xa068, 0x000186a0); /* RP Up EI */
504 gtt_write(gtt_bar, 0xa06c, 0x000493e0); /* RP Down EI */
505 gtt_write(gtt_bar, 0xa070, 0x0000000a); /* RP Idle Hysteresis */
506
507 /* 11a: Enable Render Standby (RC6) */
508 if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) {
509 /*
510 * IvyBridge should also support DeepRenderStandby.
511 *
512 * Unfortunately it does not work reliably on all SKUs so
513 * disable it here and it can be enabled by the kernel.
514 */
515 gtt_write(gtt_bar, 0xa090, 0x88040000); /* HW RC Control */
516 } else {
517 gtt_write(gtt_bar, 0xa090, 0x88040000); /* HW RC Control */
518 }
519
520 /* 12: Normal Frequency Request */
521 /* RPNFREQ_VAL comes from MCHBAR 0x5998 23:16 (8 bits!? use 7) */
522 reg32 = readl(MCHBAR_REG(0x5998));
523 reg32 >>= 16;
524 reg32 &= 0xef;
525 reg32 <<= 25;
526 gtt_write(gtt_bar, 0xa008, reg32);
527
528 /* 13: RP Control */
529 gtt_write(gtt_bar, 0xa024, 0x00000592);
530
531 /* 14: Enable PM Interrupts */
532 gtt_write(gtt_bar, 0x4402c, 0x03000076);
533
534 /* Clear 0x6c024 [8:6] */
535 reg32 = gtt_read(gtt_bar, 0x6c024);
536 reg32 &= ~0x000001c0;
537 gtt_write(gtt_bar, 0x6c024, reg32);
538
539 return 0;
540}
541
542int gma_pm_init_post_vbios(void *gtt_bar, const void *blob, int node)
543{
544 u32 reg32, cycle_delay;
545
546 debug("GT Power Management Init (post VBIOS)\n");
547
548 /* 15: Deassert Force Wake */
549 if (bridge_silicon_revision() < IVB_STEP_C0) {
550 gtt_write(gtt_bar, 0xa18c, gtt_read(gtt_bar, 0xa18c) & ~1);
551 gtt_poll(gtt_bar, 0x130090, (1 << 0), (0 << 0));
552 } else {
553 gtt_write(gtt_bar, 0xa188, 0x1fffe);
554 if (gtt_poll(gtt_bar, 0x130040, (1 << 0), (0 << 0))) {
555 gtt_write(gtt_bar, 0xa188,
556 gtt_read(gtt_bar, 0xa188) | 1);
557 }
558 }
559
560 /* 16: SW RC Control */
561 gtt_write(gtt_bar, 0xa094, 0x00060000);
562
563 /* Setup Digital Port Hotplug */
564 reg32 = gtt_read(gtt_bar, 0xc4030);
565 if (!reg32) {
566 u32 dp_hotplug[3];
567
568 if (fdtdec_get_int_array(blob, node, "intel,dp_hotplug",
569 dp_hotplug, ARRAY_SIZE(dp_hotplug)))
570 return -EINVAL;
571
572 reg32 = (dp_hotplug[0] & 0x7) << 2;
573 reg32 |= (dp_hotplug[0] & 0x7) << 10;
574 reg32 |= (dp_hotplug[0] & 0x7) << 18;
575 gtt_write(gtt_bar, 0xc4030, reg32);
576 }
577
578 /* Setup Panel Power On Delays */
579 reg32 = gtt_read(gtt_bar, 0xc7208);
580 if (!reg32) {
581 reg32 = (unsigned)fdtdec_get_int(blob, node,
582 "panel-port-select", 0) << 30;
583 reg32 |= fdtdec_get_int(blob, node, "panel-power-up-delay", 0)
584 << 16;
585 reg32 |= fdtdec_get_int(blob, node,
586 "panel-power-backlight-on-delay", 0);
587 gtt_write(gtt_bar, 0xc7208, reg32);
588 }
589
590 /* Setup Panel Power Off Delays */
591 reg32 = gtt_read(gtt_bar, 0xc720c);
592 if (!reg32) {
593 reg32 = fdtdec_get_int(blob, node, "panel-power-down-delay", 0)
594 << 16;
595 reg32 |= fdtdec_get_int(blob, node,
596 "panel-power-backlight-off-delay", 0);
597 gtt_write(gtt_bar, 0xc720c, reg32);
598 }
599
600 /* Setup Panel Power Cycle Delay */
601 cycle_delay = fdtdec_get_int(blob, node,
602 "intel,panel-power-cycle-delay", 0);
603 if (cycle_delay) {
604 reg32 = gtt_read(gtt_bar, 0xc7210);
605 reg32 &= ~0xff;
606 reg32 |= cycle_delay;
607 gtt_write(gtt_bar, 0xc7210, reg32);
608 }
609
610 /* Enable Backlight if needed */
611 reg32 = fdtdec_get_int(blob, node, "intel,cpu-backlight", 0);
612 if (reg32) {
613 gtt_write(gtt_bar, 0x48250, (1 << 31));
614 gtt_write(gtt_bar, 0x48254, reg32);
615 }
616 reg32 = fdtdec_get_int(blob, node, "intel,pch-backlight", 0);
617 if (reg32) {
618 gtt_write(gtt_bar, 0xc8250, (1 << 31));
619 gtt_write(gtt_bar, 0xc8254, reg32);
620 }
621
622 return 0;
623}
624
625/*
626 * Some vga option roms are used for several chipsets but they only have one
627 * PCI ID in their header. If we encounter such an option rom, we need to do
628 * the mapping ourselves.
629 */
630
631uint32_t board_map_oprom_vendev(uint32_t vendev)
632{
633 switch (vendev) {
634 case 0x80860102: /* GT1 Desktop */
635 case 0x8086010a: /* GT1 Server */
636 case 0x80860112: /* GT2 Desktop */
637 case 0x80860116: /* GT2 Mobile */
638 case 0x80860122: /* GT2 Desktop >=1.3GHz */
639 case 0x80860126: /* GT2 Mobile >=1.3GHz */
640 case 0x80860156: /* IVB */
641 case 0x80860166: /* IVB */
642 return 0x80860106; /* GT1 Mobile */
643 }
644
645 return vendev;
646}
647
648static int int15_handler(void)
649{
650 int res = 0;
651
652 debug("%s: INT15 function %04x!\n", __func__, M.x86.R_AX);
653
654 switch (M.x86.R_AX) {
655 case 0x5f34:
656 /*
657 * Set Panel Fitting Hook:
658 * bit 2 = Graphics Stretching
659 * bit 1 = Text Stretching
660 * bit 0 = Centering (do not set with bit1 or bit2)
661 * 0 = video bios default
662 */
663 M.x86.R_AX = 0x005f;
664 M.x86.R_CL = 0x00; /* Use video bios default */
665 res = 1;
666 break;
667 case 0x5f35:
668 /*
669 * Boot Display Device Hook:
670 * bit 0 = CRT
671 * bit 1 = TV (eDP)
672 * bit 2 = EFP
673 * bit 3 = LFP
674 * bit 4 = CRT2
675 * bit 5 = TV2 (eDP)
676 * bit 6 = EFP2
677 * bit 7 = LFP2
678 */
679 M.x86.R_AX = 0x005f;
680 M.x86.R_CX = 0x0000; /* Use video bios default */
681 res = 1;
682 break;
683 case 0x5f51:
684 /*
685 * Hook to select active LFP configuration:
686 * 00h = No LVDS, VBIOS does not enable LVDS
687 * 01h = Int-LVDS, LFP driven by integrated LVDS decoder
688 * 02h = SVDO-LVDS, LFP driven by SVDO decoder
689 * 03h = eDP, LFP Driven by Int-DisplayPort encoder
690 */
691 M.x86.R_AX = 0x005f;
692 M.x86.R_CX = 0x0003; /* eDP */
693 res = 1;
694 break;
695 case 0x5f70:
696 switch (M.x86.R_CH) {
697 case 0:
698 /* Get Mux */
699 M.x86.R_AX = 0x005f;
700 M.x86.R_CX = 0x0000;
701 res = 1;
702 break;
703 case 1:
704 /* Set Mux */
705 M.x86.R_AX = 0x005f;
706 M.x86.R_CX = 0x0000;
707 res = 1;
708 break;
709 case 2:
710 /* Get SG/Non-SG mode */
711 M.x86.R_AX = 0x005f;
712 M.x86.R_CX = 0x0000;
713 res = 1;
714 break;
715 default:
716 /* Interrupt was not handled */
717 debug("Unknown INT15 5f70 function: 0x%02x\n",
718 M.x86.R_CH);
719 break;
720 }
721 break;
722 case 0x5fac:
723 res = 1;
724 break;
725 default:
726 debug("Unknown INT15 function %04x!\n", M.x86.R_AX);
727 break;
728 }
729 return res;
730}
731
732int gma_func0_init(pci_dev_t dev, struct pci_controller *hose,
733 const void *blob, int node)
734{
d19ee5c2
SG		 735#ifdef CONFIG_VIDEO
736 ulong start;
737#endif
effcf067 738 void *gtt_bar;
9818a00e 739 ulong base;
effcf067
SG		 740 u32 reg32;
741 int ret;
742
743 /* IGD needs to be Bus Master */
31f57c28 744 reg32 = x86_pci_read_config32(dev, PCI_COMMAND);
effcf067 745 reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
31f57c28 746 x86_pci_write_config32(dev, PCI_COMMAND, reg32);
effcf067 747
9818a00e
SG		 748 /* Use write-combining for the graphics memory, 256MB */
749 base = pci_read_bar32(hose, dev, 2);
750 mtrr_add_request(MTRR_TYPE_WRCOMB, base, 256 << 20);
751 mtrr_commit(true);
752
effcf067
SG		 753 gtt_bar = (void *)pci_read_bar32(pci_bus_to_hose(0), dev, 0);
754 debug("GT bar %p\n", gtt_bar);
755 ret = gma_pm_init_pre_vbios(gtt_bar);
756 if (ret)
757 return ret;
758
d19ee5c2
SG		 759#ifdef CONFIG_VIDEO
760 start = get_timer(0);
bc17d8f4
SG		 761 ret = pci_run_vga_bios(dev, int15_handler, PCI_ROM_USE_NATIVE |
762 PCI_ROM_ALLOW_FALLBACK);
d19ee5c2
SG		 763 debug("BIOS ran in %lums\n", get_timer(start));
764#endif
effcf067
SG		 765 /* Post VBIOS init */
766 ret = gma_pm_init_post_vbios(gtt_bar, blob, node);
767 if (ret)
768 return ret;
769
770 return 0;
771}
"Das U-Boot" Source Tree