[people/ms/u-boot.git] / arch / x86 / cpu / ivybridge / usb_xhci.c

/*
 * From Coreboot
 * Copyright (C) 2008-2009 coresystems GmbH
 *
 * SPDX-License-Identifier:	GPL-2.0
 */

#include <common.h>
#include <asm/pci.h>
#include <asm/arch/pch.h>

void bd82x6x_usb_xhci_init(pci_dev_t dev)
{
	u32 reg32;

	debug("XHCI: Setting up controller.. ");

	/* lock overcurrent map */
	reg32 = x86_pci_read_config32(dev, 0x44);
	reg32 |= 1;
	x86_pci_write_config32(dev, 0x44, reg32);

	/* Enable clock gating */
	reg32 = x86_pci_read_config32(dev, 0x40);
	reg32 &= ~((1 << 20) | (1 << 21));
	reg32 |= (1 << 19) | (1 << 18) | (1 << 17);
	reg32 |= (1 << 10) | (1 << 9) | (1 << 8);
	reg32 |= (1 << 31); /* lock */
	x86_pci_write_config32(dev, 0x40, reg32);

	debug("done.\n");
}
Commit	Line	Data
a6d4c453 SG	1	/*
	2	* From Coreboot
	3	* Copyright (C) 2008-2009 coresystems GmbH
	4	*
	5	* SPDX-License-Identifier: GPL-2.0
	6	*/
	7
	8	#include <common.h>
	9	#include <asm/pci.h>
	10	#include <asm/arch/pch.h>
	11
	12	void bd82x6x_usb_xhci_init(pci_dev_t dev)
	13	{
	14	u32 reg32;
	15
	16	debug("XHCI: Setting up controller.. ");
	17
	18	/* lock overcurrent map */
31f57c28	19	reg32 = x86_pci_read_config32(dev, 0x44);
a6d4c453	20	reg32 \|= 1;
31f57c28	21	x86_pci_write_config32(dev, 0x44, reg32);
a6d4c453 SG	22
a6d4c453 SG	23	/* Enable clock gating */
31f57c28	24	reg32 = x86_pci_read_config32(dev, 0x40);
a6d4c453 SG	25	reg32 &= ~((1 << 20) \| (1 << 21));
	26	reg32 \|= (1 << 19) \| (1 << 18) \| (1 << 17);
	27	reg32 \|= (1 << 10) \| (1 << 9) \| (1 << 8);
	28	reg32 \|= (1 << 31); /* lock */
31f57c28	29	x86_pci_write_config32(dev, 0x40, reg32);
a6d4c453 SG	30
	31	debug("done.\n");
	32	}