[people/ms/u-boot.git] / arch / x86 / cpu / quark / quark.c

/*
 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <mmc.h>
#include <netdev.h>
#include <phy.h>
#include <asm/io.h>
#include <asm/pci.h>
#include <asm/post.h>
#include <asm/processor.h>
#include <asm/arch/device.h>
#include <asm/arch/msg_port.h>
#include <asm/arch/quark.h>

static struct pci_device_id mmc_supported[] = {
	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_SDIO },
};

/*
 * TODO:
 *
 * This whole routine should be removed until we fully convert the ICH SPI
 * driver to DM and make use of DT to pass the bios control register offset
 */
static void unprotect_spi_flash(void)
{
	u32 bc;

	bc = x86_pci_read_config32(QUARK_LEGACY_BRIDGE, 0xd8);
	bc |= 0x1;	/* unprotect the flash */
	x86_pci_write_config32(QUARK_LEGACY_BRIDGE, 0xd8, bc);
}

static void quark_setup_bars(void)
{
	/* GPIO - D31:F0:R44h */
	pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA,
			       CONFIG_GPIO_BASE | IO_BAR_EN);

	/* ACPI PM1 Block - D31:F0:R48h */
	pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_PM1BLK,
			       CONFIG_ACPI_PM1_BASE | IO_BAR_EN);

	/* GPE0 - D31:F0:R4Ch */
	pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GPE0BLK,
			       CONFIG_ACPI_GPE0_BASE | IO_BAR_EN);

	/* WDT - D31:F0:R84h */
	pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_WDTBA,
			       CONFIG_WDT_BASE | IO_BAR_EN);

	/* RCBA - D31:F0:RF0h */
	pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA,
			       CONFIG_RCBA_BASE | MEM_BAR_EN);

	/* ACPI P Block - Msg Port 04:R70h */
	msg_port_write(MSG_PORT_RMU, PBLK_BA,
		       CONFIG_ACPI_PBLK_BASE | IO_BAR_EN);

	/* SPI DMA - Msg Port 04:R7Ah */
	msg_port_write(MSG_PORT_RMU, SPI_DMA_BA,
		       CONFIG_SPI_DMA_BASE | IO_BAR_EN);

	/* PCIe ECAM */
	msg_port_write(MSG_PORT_MEM_ARBITER, AEC_CTRL,
		       CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN);
	msg_port_write(MSG_PORT_HOST_BRIDGE, HEC_REG,
		       CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN);
}

static void quark_enable_legacy_seg(void)
{
	u32 hmisc2;

	hmisc2 = msg_port_read(MSG_PORT_HOST_BRIDGE, HMISC2);
	hmisc2 |= (HMISC2_SEGE | HMISC2_SEGF | HMISC2_SEGAB);
	msg_port_write(MSG_PORT_HOST_BRIDGE, HMISC2, hmisc2);
}

int arch_cpu_init(void)
{
	struct pci_controller *hose;
	int ret;

	post_code(POST_CPU_INIT);
#ifdef CONFIG_SYS_X86_TSC_TIMER
	timer_set_base(rdtsc());
#endif

	ret = x86_cpu_init_f();
	if (ret)
		return ret;

	ret = pci_early_init_hose(&hose);
	if (ret)
		return ret;

	/*
	 * Quark SoC has some non-standard BARs (excluding PCI standard BARs)
	 * which need be initialized with suggested values
	 */
	quark_setup_bars();

	/* Turn on legacy segments (A/B/E/F) decode to system RAM */
	quark_enable_legacy_seg();

	unprotect_spi_flash();

	return 0;
}

int print_cpuinfo(void)
{
	post_code(POST_CPU_INFO);
	return default_print_cpuinfo();
}

void reset_cpu(ulong addr)
{
	/* cold reset */
	outb(0x08, PORT_RESET);
}

int cpu_mmc_init(bd_t *bis)
{
	return pci_mmc_init("Quark SDHCI", mmc_supported,
			    ARRAY_SIZE(mmc_supported));
}

int cpu_eth_init(bd_t *bis)
{
	u32 base;
	int ret0, ret1;

	pci_read_config_dword(QUARK_EMAC0, PCI_BASE_ADDRESS_0, &base);
	ret0 = designware_initialize(base, PHY_INTERFACE_MODE_RMII);

	pci_read_config_dword(QUARK_EMAC1, PCI_BASE_ADDRESS_0, &base);
	ret1 = designware_initialize(base, PHY_INTERFACE_MODE_RMII);

	if (ret0 < 0 && ret1 < 0)
		return -1;
	else
		return 0;
}
Commit	Line	Data
828d9af5 BM	1	/*
	2	* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#include <common.h>
6df7ffea	8	#include <mmc.h>
e4ad6031 BM	9	#include <netdev.h>
e4ad6031 BM	10	#include <phy.h>
828d9af5 BM	11	#include <asm/io.h>
	12	#include <asm/pci.h>
	13	#include <asm/post.h>
	14	#include <asm/processor.h>
b162257d BM	15	#include <asm/arch/device.h>
	16	#include <asm/arch/msg_port.h>
	17	#include <asm/arch/quark.h>
	18
6df7ffea BM	19	static struct pci_device_id mmc_supported[] = {
	20	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_SDIO },
	21	};
	22
728b393f BM	23	/*
	24	* TODO:
	25	*
	26	* This whole routine should be removed until we fully convert the ICH SPI
	27	* driver to DM and make use of DT to pass the bios control register offset
	28	*/
	29	static void unprotect_spi_flash(void)
	30	{
	31	u32 bc;
	32
31f57c28	33	bc = x86_pci_read_config32(QUARK_LEGACY_BRIDGE, 0xd8);
728b393f	34	bc \|= 0x1; /* unprotect the flash */
31f57c28	35	x86_pci_write_config32(QUARK_LEGACY_BRIDGE, 0xd8, bc);
728b393f BM	36	}
728b393f BM	37
b162257d BM	38	static void quark_setup_bars(void)
	39	{
	40	/* GPIO - D31:F0:R44h */
	41	pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA,
	42	CONFIG_GPIO_BASE \| IO_BAR_EN);
	43
	44	/* ACPI PM1 Block - D31:F0:R48h */
	45	pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_PM1BLK,
	46	CONFIG_ACPI_PM1_BASE \| IO_BAR_EN);
	47
	48	/* GPE0 - D31:F0:R4Ch */
	49	pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GPE0BLK,
	50	CONFIG_ACPI_GPE0_BASE \| IO_BAR_EN);
	51
	52	/* WDT - D31:F0:R84h */
	53	pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_WDTBA,
	54	CONFIG_WDT_BASE \| IO_BAR_EN);
	55
	56	/* RCBA - D31:F0:RF0h */
	57	pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA,
	58	CONFIG_RCBA_BASE \| MEM_BAR_EN);
	59
	60	/* ACPI P Block - Msg Port 04:R70h */
	61	msg_port_write(MSG_PORT_RMU, PBLK_BA,
	62	CONFIG_ACPI_PBLK_BASE \| IO_BAR_EN);
	63
	64	/* SPI DMA - Msg Port 04:R7Ah */
	65	msg_port_write(MSG_PORT_RMU, SPI_DMA_BA,
	66	CONFIG_SPI_DMA_BASE \| IO_BAR_EN);
	67
	68	/* PCIe ECAM */
	69	msg_port_write(MSG_PORT_MEM_ARBITER, AEC_CTRL,
	70	CONFIG_PCIE_ECAM_BASE \| MEM_BAR_EN);
	71	msg_port_write(MSG_PORT_HOST_BRIDGE, HEC_REG,
	72	CONFIG_PCIE_ECAM_BASE \| MEM_BAR_EN);
	73	}
828d9af5	74
f82a7840 BM	75	static void quark_enable_legacy_seg(void)
	76	{
	77	u32 hmisc2;
	78
	79	hmisc2 = msg_port_read(MSG_PORT_HOST_BRIDGE, HMISC2);
	80	hmisc2 \|= (HMISC2_SEGE \| HMISC2_SEGF \| HMISC2_SEGAB);
	81	msg_port_write(MSG_PORT_HOST_BRIDGE, HMISC2, hmisc2);
	82	}
	83
828d9af5 BM	84	int arch_cpu_init(void)
	85	{
	86	struct pci_controller *hose;
	87	int ret;
	88
	89	post_code(POST_CPU_INIT);
	90	#ifdef CONFIG_SYS_X86_TSC_TIMER
	91	timer_set_base(rdtsc());
	92	#endif
	93
	94	ret = x86_cpu_init_f();
	95	if (ret)
	96	return ret;
	97
	98	ret = pci_early_init_hose(&hose);
	99	if (ret)
	100	return ret;
	101
b162257d BM	102	/*
	103	* Quark SoC has some non-standard BARs (excluding PCI standard BARs)
	104	* which need be initialized with suggested values
	105	*/
	106	quark_setup_bars();
	107
f82a7840 BM	108	/* Turn on legacy segments (A/B/E/F) decode to system RAM */
	109	quark_enable_legacy_seg();
	110
728b393f BM	111	unprotect_spi_flash();
728b393f BM	112
828d9af5 BM	113	return 0;
	114	}
	115
	116	int print_cpuinfo(void)
	117	{
	118	post_code(POST_CPU_INFO);
	119	return default_print_cpuinfo();
	120	}
	121
	122	void reset_cpu(ulong addr)
	123	{
	124	/* cold reset */
	125	outb(0x08, PORT_RESET);
	126	}
6df7ffea BM	127
	128	int cpu_mmc_init(bd_t *bis)
	129	{
	130	return pci_mmc_init("Quark SDHCI", mmc_supported,
	131	ARRAY_SIZE(mmc_supported));
	132	}
e4ad6031 BM	133
	134	int cpu_eth_init(bd_t *bis)
	135	{
	136	u32 base;
	137	int ret0, ret1;
	138
	139	pci_read_config_dword(QUARK_EMAC0, PCI_BASE_ADDRESS_0, &base);
	140	ret0 = designware_initialize(base, PHY_INTERFACE_MODE_RMII);
	141
	142	pci_read_config_dword(QUARK_EMAC1, PCI_BASE_ADDRESS_0, &base);
	143	ret1 = designware_initialize(base, PHY_INTERFACE_MODE_RMII);
	144
	145	if (ret0 < 0 && ret1 < 0)
	146	return -1;
	147	else
	148	return 0;
	149	}