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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
93031595 SG |
2 | /* |
3 | * (C) Copyright 2016 Google, Inc | |
4 | * Written by Simon Glass <sjg@chromium.org> | |
93031595 SG |
5 | */ |
6 | ||
7 | #include <common.h> | |
30c7c434 | 8 | #include <cpu_func.h> |
a160092a | 9 | #include <debug_uart.h> |
691d719d | 10 | #include <init.h> |
8ebca32b | 11 | #include <asm/cpu.h> |
9c297a3d | 12 | #include <asm/global_data.h> |
93031595 | 13 | |
8ebca32b SG |
14 | DECLARE_GLOBAL_DATA_PTR; |
15 | ||
93031595 SG |
16 | int cpu_has_64bit(void) |
17 | { | |
18 | return true; | |
19 | } | |
20 | ||
21 | void enable_caches(void) | |
22 | { | |
23 | /* Not implemented */ | |
24 | } | |
25 | ||
26 | void disable_caches(void) | |
27 | { | |
28 | /* Not implemented */ | |
29 | } | |
30 | ||
31 | int dcache_status(void) | |
32 | { | |
33 | return true; | |
34 | } | |
35 | ||
36 | int x86_mp_init(void) | |
37 | { | |
38 | /* Not implemented */ | |
39 | return 0; | |
40 | } | |
1b408630 | 41 | |
c0069e9a SG |
42 | int x86_cpu_reinit_f(void) |
43 | { | |
8ebca32b SG |
44 | /* set the vendor to Intel so that native_calibrate_tsc() works */ |
45 | gd->arch.x86_vendor = X86_VENDOR_INTEL; | |
46 | gd->arch.has_mtrr = true; | |
47 | ||
c0069e9a SG |
48 | return 0; |
49 | } | |
aec7c1c5 SG |
50 | |
51 | int cpu_phys_address_size(void) | |
52 | { | |
53 | return CONFIG_CPU_ADDR_BITS; | |
54 | } | |
450ce56a SG |
55 | |
56 | int x86_cpu_init_f(void) | |
57 | { | |
58 | return 0; | |
59 | } | |
afa3d90c SG |
60 | |
61 | #ifdef CONFIG_DEBUG_UART_BOARD_INIT | |
62 | void board_debug_uart_init(void) | |
63 | { | |
64 | /* this was already done in SPL */ | |
65 | } | |
66 | #endif |