[thirdparty/u-boot.git] / arch / x86 / dts / galileo.dts

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
 */

/dts-v1/;

#include <dt-bindings/mrc/quark.h>
#include <dt-bindings/interrupt-router/intel-irq.h>

/include/ "skeleton.dtsi"
/include/ "reset.dtsi"
/include/ "rtc.dtsi"

#include "tsc_timer.dtsi"

/ {
	model = "Intel Galileo";
	compatible = "intel,galileo", "intel,quark";

	aliases {
		spi0 = &spi;
	};

	config {
		silent_console = <0>;
	};

	chosen {
		stdout-path = &pciuart0;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "cpu-x86";
			reg = <0>;
			intel,apic-id = <0>;
		};
	};

	mrc {
		compatible = "intel,quark-mrc";
		flags = <MRC_FLAG_SCRAMBLE_EN>;
		dram-width = <DRAM_WIDTH_X8>;
		dram-speed = <DRAM_FREQ_800>;
		dram-type = <DRAM_TYPE_DDR3>;
		rank-mask = <DRAM_RANK(0)>;
		chan-mask = <DRAM_CHANNEL(0)>;
		chan-width = <DRAM_CHANNEL_WIDTH_X16>;
		addr-mode = <DRAM_ADDR_MODE0>;
		refresh-rate = <DRAM_REFRESH_RATE_785US>;
		sr-temp-range = <DRAM_SRT_RANGE_NORMAL>;
		ron-value = <DRAM_RON_34OHM>;
		rtt-nom-value = <DRAM_RTT_NOM_120OHM>;
		rd-odt-value = <DRAM_RD_ODT_OFF>;
		dram-density = <DRAM_DENSITY_1G>;
		dram-cl = <6>;
		dram-ras = <0x0000927c>;
		dram-wtr = <0x00002710>;
		dram-rrd = <0x00002710>;
		dram-faw = <0x00009c40>;
	};

	pci {
		#address-cells = <3>;
		#size-cells = <2>;
		compatible = "pci-x86";
		bootph-all;
		ranges = <0x02000000 0x0 0x90000000 0x90000000 0 0x20000000
			  0x42000000 0x0 0xb0000000 0xb0000000 0 0x20000000
			  0x01000000 0x0 0x2000 0x2000 0 0xe000>;

		pciuart0: uart@14,5 {
			compatible = "pci8086,0936.00",
					"pci8086,0936",
					"pciclass,070002",
					"pciclass,0700",
					"ns16550";
			bootph-all;
			reg = <0x0000a500 0x0 0x0 0x0 0x0
			       0x0200a510 0x0 0x0 0x0 0x0>;
			reg-shift = <2>;
			clock-frequency = <44236800>;
			current-speed = <115200>;
		};

		pch@1f,0 {
			reg = <0x0000f800 0 0 0 0>;
			compatible = "intel,pch7";
			#address-cells = <1>;
			#size-cells = <1>;

			irq-router {
				compatible = "intel,irq-router";
				intel,pirq-config = "pci";
				intel,actl-addr = <0x58>;
				intel,pirq-link = <0x60 8>;
				intel,pirq-mask = <0xdef8>;
				intel,pirq-routing = <
					PCI_BDF(0, 20, 0) INTA PIRQE
					PCI_BDF(0, 20, 1) INTB PIRQF
					PCI_BDF(0, 20, 2) INTC PIRQG
					PCI_BDF(0, 20, 3) INTD PIRQH
					PCI_BDF(0, 20, 4) INTA PIRQE
					PCI_BDF(0, 20, 5) INTB PIRQF
					PCI_BDF(0, 20, 6) INTC PIRQG
					PCI_BDF(0, 20, 7) INTD PIRQH
					PCI_BDF(0, 21, 0) INTA PIRQE
					PCI_BDF(0, 21, 1) INTB PIRQF
					PCI_BDF(0, 21, 2) INTC PIRQG
					PCI_BDF(0, 23, 0) INTA PIRQA
					PCI_BDF(0, 23, 1) INTB PIRQB

					/* PCIe root ports downstream interrupts */
					PCI_BDF(1, 0, 0) INTA PIRQA
					PCI_BDF(1, 0, 0) INTB PIRQB
					PCI_BDF(1, 0, 0) INTC PIRQC
					PCI_BDF(1, 0, 0) INTD PIRQD
					PCI_BDF(2, 0, 0) INTA PIRQB
					PCI_BDF(2, 0, 0) INTB PIRQC
					PCI_BDF(2, 0, 0) INTC PIRQD
					PCI_BDF(2, 0, 0) INTD PIRQA
				>;
			};

			spi: spi {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "intel,ich7-spi";
				spi-flash@0 {
					#size-cells = <1>;
					#address-cells = <1>;
					reg = <0>;
					compatible = "winbond,w25q64",
						"jedec,spi-nor";
					memory-map = <0xff800000 0x00800000>;
					rw-mrc-cache {
						label = "rw-mrc-cache";
						reg = <0x00010000 0x00010000>;
					};
				};
			};

			gpioa {
				compatible = "intel,ich6-gpio";
				bootph-all;
				reg = <0 0x20>;
				bank-name = "A";
			};

			gpiob {
				compatible = "intel,ich6-gpio";
				bootph-all;
				reg = <0x20 0x20>;
				bank-name = "B";
			};
		};
	};

	smbios {
		compatible = "u-boot,sysinfo-smbios";

		/*
		 * Override the default product name U-Boot reports in the
		 * SMBIOS table, to be compatible with the Intel provided UEFI
		 * BIOS, as Linux kernel drivers
		 * (drivers/mfd/intel_quark_i2c_gpio.c and
		 * drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c) make use of
		 * it to do different board level configuration.
		 *
		 * This can be "Galileo" for GEN1 Galileo board.
		 */
		smbios {
			system {
				product = "GalileoGen2";
			};

			baseboard {
				product = "GalileoGen2";
			};

			chassis {
				product = "GalileoGen2";
			};
		};
	};

};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
afee3fb8 BM	2	/*
afee3fb8 BM	3	* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
afee3fb8 BM	4	*/
	5
	6	/dts-v1/;
	7
20c34115	8	#include <dt-bindings/mrc/quark.h>
05b98ec3	9	#include <dt-bindings/interrupt-router/intel-irq.h>
20c34115	10
afee3fb8	11	/include/ "skeleton.dtsi"
b37b7b20	12	/include/ "reset.dtsi"
93f8a311	13	/include/ "rtc.dtsi"
c79cbb59 BM	14
c79cbb59 BM	15	#include "tsc_timer.dtsi"
afee3fb8 BM	16
	17	/ {
	18	model = "Intel Galileo";
	19	compatible = "intel,galileo", "intel,quark";
	20
0a9bb489	21	aliases {
81aaa3d9	22	spi0 = &spi;
0a9bb489 BM	23	};
0a9bb489 BM	24
afee3fb8 BM	25	config {
	26	silent_console = <0>;
	27	};
	28
	29	chosen {
	30	stdout-path = &pciuart0;
	31	};
	32
0ac8d5e5 BM	33	cpus {
	34	#address-cells = <1>;
	35	#size-cells = <0>;
	36
	37	cpu@0 {
	38	device_type = "cpu";
	39	compatible = "cpu-x86";
	40	reg = <0>;
	41	intel,apic-id = <0>;
	42	};
	43	};
	44
20c34115 BM	45	mrc {
	46	compatible = "intel,quark-mrc";
	47	flags = <MRC_FLAG_SCRAMBLE_EN>;
	48	dram-width = <DRAM_WIDTH_X8>;
	49	dram-speed = <DRAM_FREQ_800>;
	50	dram-type = <DRAM_TYPE_DDR3>;
	51	rank-mask = <DRAM_RANK(0)>;
	52	chan-mask = <DRAM_CHANNEL(0)>;
	53	chan-width = <DRAM_CHANNEL_WIDTH_X16>;
	54	addr-mode = <DRAM_ADDR_MODE0>;
	55	refresh-rate = <DRAM_REFRESH_RATE_785US>;
	56	sr-temp-range = <DRAM_SRT_RANGE_NORMAL>;
	57	ron-value = <DRAM_RON_34OHM>;
	58	rtt-nom-value = <DRAM_RTT_NOM_120OHM>;
	59	rd-odt-value = <DRAM_RD_ODT_OFF>;
	60	dram-density = <DRAM_DENSITY_1G>;
	61	dram-cl = <6>;
	62	dram-ras = <0x0000927c>;
	63	dram-wtr = <0x00002710>;
	64	dram-rrd = <0x00002710>;
	65	dram-faw = <0x00009c40>;
	66	};
	67
afee3fb8 BM	68	pci {
	69	#address-cells = <3>;
	70	#size-cells = <2>;
31b5aebd	71	compatible = "pci-x86";
8c103c33	72	bootph-all;
31b5aebd BM	73	ranges = <0x02000000 0x0 0x90000000 0x90000000 0 0x20000000
	74	0x42000000 0x0 0xb0000000 0xb0000000 0 0x20000000
	75	0x01000000 0x0 0x2000 0x2000 0 0xe000>;
afee3fb8 BM	76
	77	pciuart0: uart@14,5 {
	78	compatible = "pci8086,0936.00",
	79	"pci8086,0936",
	80	"pciclass,070002",
	81	"pciclass,0700",
c5c5c201	82	"ns16550";
8c103c33	83	bootph-all;
afee3fb8 BM	84	reg = <0x0000a500 0x0 0x0 0x0 0x0
	85	0x0200a510 0x0 0x0 0x0 0x0>;
	86	reg-shift = <2>;
	87	clock-frequency = <44236800>;
	88	current-speed = <115200>;
	89	};
05b98ec3	90
f2b85ab5	91	pch@1f,0 {
05b98ec3	92	reg = <0x0000f800 0 0 0 0>;
f2b85ab5	93	compatible = "intel,pch7";
3ddc1c7b BM	94	#address-cells = <1>;
3ddc1c7b BM	95	#size-cells = <1>;
f2b85ab5 SG	96
f2b85ab5 SG	97	irq-router {
bc728b1b	98	compatible = "intel,irq-router";
f2b85ab5	99	intel,pirq-config = "pci";
ce8dd77d	100	intel,actl-addr = <0x58>;
f2b85ab5 SG	101	intel,pirq-link = <0x60 8>;
	102	intel,pirq-mask = <0xdef8>;
	103	intel,pirq-routing = <
	104	PCI_BDF(0, 20, 0) INTA PIRQE
	105	PCI_BDF(0, 20, 1) INTB PIRQF
	106	PCI_BDF(0, 20, 2) INTC PIRQG
	107	PCI_BDF(0, 20, 3) INTD PIRQH
	108	PCI_BDF(0, 20, 4) INTA PIRQE
	109	PCI_BDF(0, 20, 5) INTB PIRQF
	110	PCI_BDF(0, 20, 6) INTC PIRQG
	111	PCI_BDF(0, 20, 7) INTD PIRQH
	112	PCI_BDF(0, 21, 0) INTA PIRQE
	113	PCI_BDF(0, 21, 1) INTB PIRQF
	114	PCI_BDF(0, 21, 2) INTC PIRQG
	115	PCI_BDF(0, 23, 0) INTA PIRQA
	116	PCI_BDF(0, 23, 1) INTB PIRQB
	117
	118	/* PCIe root ports downstream interrupts */
	119	PCI_BDF(1, 0, 0) INTA PIRQA
	120	PCI_BDF(1, 0, 0) INTB PIRQB
	121	PCI_BDF(1, 0, 0) INTC PIRQC
	122	PCI_BDF(1, 0, 0) INTD PIRQD
	123	PCI_BDF(2, 0, 0) INTA PIRQB
	124	PCI_BDF(2, 0, 0) INTB PIRQC
	125	PCI_BDF(2, 0, 0) INTC PIRQD
	126	PCI_BDF(2, 0, 0) INTD PIRQA
	127	>;
	128	};
	129
81aaa3d9	130	spi: spi {
f2b85ab5 SG	131	#address-cells = <1>;
f2b85ab5 SG	132	#size-cells = <0>;
1f9eb59d	133	compatible = "intel,ich7-spi";
f2b85ab5 SG	134	spi-flash@0 {
	135	#size-cells = <1>;
	136	#address-cells = <1>;
	137	reg = <0>;
	138	compatible = "winbond,w25q64",
51e4e3e5	139	"jedec,spi-nor";
f2b85ab5 SG	140	memory-map = <0xff800000 0x00800000>;
	141	rw-mrc-cache {
	142	label = "rw-mrc-cache";
	143	reg = <0x00010000 0x00010000>;
	144	};
	145	};
	146	};
afee3fb8	147
3ddc1c7b BM	148	gpioa {
3ddc1c7b BM	149	compatible = "intel,ich6-gpio";
8c103c33	150	bootph-all;
3ddc1c7b BM	151	reg = <0 0x20>;
	152	bank-name = "A";
	153	};
d8b1d225	154
3ddc1c7b BM	155	gpiob {
3ddc1c7b BM	156	compatible = "intel,ich6-gpio";
8c103c33	157	bootph-all;
3ddc1c7b BM	158	reg = <0x20 0x20>;
	159	bank-name = "B";
	160	};
	161	};
d8b1d225 BM	162	};
d8b1d225 BM	163
8f1f374f SG	164	smbios {
	165	compatible = "u-boot,sysinfo-smbios";
	166
	167	/*
	168	* Override the default product name U-Boot reports in the
	169	* SMBIOS table, to be compatible with the Intel provided UEFI
	170	* BIOS, as Linux kernel drivers
	171	* (drivers/mfd/intel_quark_i2c_gpio.c and
	172	* drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c) make use of
	173	* it to do different board level configuration.
	174	*
	175	* This can be "Galileo" for GEN1 Galileo board.
	176	*/
	177	smbios {
	178	system {
	179	product = "GalileoGen2";
	180	};
	181
	182	baseboard {
	183	product = "GalileoGen2";
	184	};
	185
	186	chassis {
	187	product = "GalileoGen2";
	188	};
	189	};
	190	};
	191
afee3fb8	192	};