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83d290c5 | 1 | /* SPDX-License-Identifier: Intel */ |
3a1a18ff SG |
2 | /* |
3 | * Copyright (C) 2013, Intel Corporation | |
4 | * Copyright (C) 2015 Google, Inc | |
3a1a18ff SG |
5 | */ |
6 | ||
7 | #ifndef __FSP_VPD_H | |
8 | #define __FSP_VPD_H | |
9 | ||
10 | struct memory_down_data { | |
11 | uint8_t enable_memory_down; | |
12 | uint8_t dram_speed; | |
13 | uint8_t dram_type; | |
14 | uint8_t dimm_0_enable; | |
15 | uint8_t dimm_1_enable; | |
16 | uint8_t dimm_width; | |
17 | uint8_t dimm_density; | |
18 | uint8_t dimm_bus_width; | |
19 | uint8_t dimm_sides; /* Ranks Per dimm_ */ | |
20 | uint8_t dimm_tcl; /* tCL */ | |
21 | /* tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc. */ | |
22 | uint8_t dimm_trpt_rcd; | |
23 | uint8_t dimm_twr; /* tWR in DRAM clk */ | |
24 | uint8_t dimm_twtr; /* tWTR in DRAM clk */ | |
25 | uint8_t dimm_trrd; /* tRRD in DRAM clk */ | |
26 | uint8_t dimm_trtp; /* tRTP in DRAM clk */ | |
27 | uint8_t dimm_tfaw; /* tFAW in DRAM clk */ | |
28 | }; | |
29 | ||
30 | struct __packed upd_region { | |
31 | uint64_t signature; /* Offset 0x0000 */ | |
32 | uint8_t reserved0[24]; /* Offset 0x0008 */ | |
33 | uint16_t mrc_init_tseg_size; /* Offset 0x0020 */ | |
34 | uint16_t mrc_init_mmio_size; /* Offset 0x0022 */ | |
35 | uint8_t mrc_init_spd_addr1; /* Offset 0x0024 */ | |
36 | uint8_t mrc_init_spd_addr2; /* Offset 0x0025 */ | |
37 | uint8_t emmc_boot_mode; /* Offset 0x0026 */ | |
38 | uint8_t enable_sdio; /* Offset 0x0027 */ | |
39 | uint8_t enable_sdcard; /* Offset 0x0028 */ | |
40 | uint8_t enable_hsuart0; /* Offset 0x0029 */ | |
41 | uint8_t enable_hsuart1; /* Offset 0x002a */ | |
42 | uint8_t enable_spi; /* Offset 0x002b */ | |
43 | uint8_t reserved1; /* Offset 0x002c */ | |
44 | uint8_t enable_sata; /* Offset 0x002d */ | |
45 | uint8_t sata_mode; /* Offset 0x002e */ | |
46 | uint8_t enable_azalia; /* Offset 0x002f */ | |
f6859558 | 47 | struct azalia_config *azalia_cfg_ptr; /* Offset 0x0030 */ |
3a1a18ff | 48 | uint8_t enable_xhci; /* Offset 0x0034 */ |
f8f291b0 BM |
49 | uint8_t lpe_mode; /* Offset 0x0035 */ |
50 | uint8_t lpss_sio_mode; /* Offset 0x0036 */ | |
3a1a18ff SG |
51 | uint8_t enable_dma0; /* Offset 0x0037 */ |
52 | uint8_t enable_dma1; /* Offset 0x0038 */ | |
53 | uint8_t enable_i2_c0; /* Offset 0x0039 */ | |
54 | uint8_t enable_i2_c1; /* Offset 0x003a */ | |
55 | uint8_t enable_i2_c2; /* Offset 0x003b */ | |
56 | uint8_t enable_i2_c3; /* Offset 0x003c */ | |
57 | uint8_t enable_i2_c4; /* Offset 0x003d */ | |
58 | uint8_t enable_i2_c5; /* Offset 0x003e */ | |
59 | uint8_t enable_i2_c6; /* Offset 0x003f */ | |
60 | uint8_t enable_pwm0; /* Offset 0x0040 */ | |
61 | uint8_t enable_pwm1; /* Offset 0x0041 */ | |
62 | uint8_t enable_hsi; /* Offset 0x0042 */ | |
63 | uint8_t igd_dvmt50_pre_alloc; /* Offset 0x0043 */ | |
64 | uint8_t aperture_size; /* Offset 0x0044 */ | |
65 | uint8_t gtt_size; /* Offset 0x0045 */ | |
6702488c | 66 | uint8_t reserved2[5]; /* Offset 0x0046 */ |
3a1a18ff SG |
67 | uint8_t mrc_debug_msg; /* Offset 0x004b */ |
68 | uint8_t isp_enable; /* Offset 0x004c */ | |
f8f291b0 | 69 | uint8_t scc_mode; /* Offset 0x004d */ |
3a1a18ff SG |
70 | uint8_t igd_render_standby; /* Offset 0x004e */ |
71 | uint8_t txe_uma_enable; /* Offset 0x004f */ | |
72 | uint8_t os_selection; /* Offset 0x0050 */ | |
73 | uint8_t emmc45_ddr50_enabled; /* Offset 0x0051 */ | |
74 | uint8_t emmc45_hs200_enabled; /* Offset 0x0052 */ | |
75 | uint8_t emmc45_retune_timer_value; /* Offset 0x0053 */ | |
3e79a4ab BM |
76 | uint8_t enable_igd; /* Offset 0x0054 */ |
77 | uint8_t unused_upd_space1[155]; /* Offset 0x0055 */ | |
3a1a18ff SG |
78 | struct memory_down_data memory_params; /* Offset 0x00f0 */ |
79 | uint16_t terminator; /* Offset 0x0100 */ | |
80 | }; | |
81 | ||
82 | #define VPD_IMAGE_ID 0x3157454956594C56 /* 'VLYVIEW1' */ | |
3a1a18ff SG |
83 | |
84 | struct __packed vpd_region { | |
85 | uint64_t sign; /* Offset 0x0000 */ | |
86 | uint32_t img_rev; /* Offset 0x0008 */ | |
87 | uint32_t upd_offset; /* Offset 0x000c */ | |
88 | uint8_t unused[16]; /* Offset 0x0010 */ | |
89 | uint32_t fsp_res_memlen; /* Offset 0x0020 */ | |
90 | uint8_t platform_type; /* Offset 0x0024 */ | |
91 | uint8_t enable_secure_boot; /* Offset 0x0025 */ | |
92 | }; | |
93 | #endif |