projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| de9ac9a1 BM |
2 | /* |
| 3 | * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> | |
| de9ac9a1 BM |
4 | */ |
| 5 | ||
| 6 | #ifndef _BRASWELL_IOMAP_H_ | |
| 7 | #define _BRASWELL_IOMAP_H_ | |
| 8 | ||
| 9 | /* Memory Mapped IO bases */ | |
| 10 | ||
| 11 | /* Power Management Controller */ | |
| 12 | #define PMC_BASE_ADDRESS 0xfed03000 | |
| 13 | #define PMC_BASE_SIZE 0x400 | |
| 14 | ||
| 15 | /* Power Management Unit */ | |
| 16 | #define PUNIT_BASE_ADDRESS 0xfed05000 | |
| 17 | #define PUNIT_BASE_SIZE 0x800 | |
| 18 | ||
| 19 | /* Intel Legacy Block */ | |
| 20 | #define ILB_BASE_ADDRESS 0xfed08000 | |
| 21 | #define ILB_BASE_SIZE 0x400 | |
| 22 | ||
| 23 | /* SPI Bus */ | |
| 24 | #define SPI_BASE_ADDRESS 0xfed01000 | |
| 25 | #define SPI_BASE_SIZE 0x400 | |
| 26 | ||
| 27 | /* Root Complex Base Address */ | |
| 28 | #define RCBA_BASE_ADDRESS 0xfed1c000 | |
| 29 | #define RCBA_BASE_SIZE 0x400 | |
| 30 | ||
| 31 | /* IO Memory */ | |
| 32 | #define IO_BASE_ADDRESS 0xfed80000 | |
| 33 | #define IO_BASE_SIZE 0x4000 | |
| 34 | ||
| 35 | /* MODPHY */ | |
| 36 | #define MPHY_BASE_ADDRESS 0xfef00000 | |
| 37 | #define MPHY_BASE_SIZE 0x100000 | |
| 38 | ||
| 39 | /* IO Port bases */ | |
| 40 | ||
| 41 | #define ACPI_BASE_ADDRESS 0x400 | |
| 42 | #define ACPI_BASE_SIZE 0x80 | |
| 43 | ||
| 44 | #define GPIO_BASE_ADDRESS 0x500 | |
| 45 | #define GPIO_BASE_SIZE 0x100 | |
| 46 | ||
| 47 | #define SMBUS_BASE_ADDRESS 0xefa0 | |
| 48 | ||
| 49 | #endif /* _BRASWELL_IOMAP_H_ */ |