[thirdparty/u-boot.git] / arch / x86 / include / asm / arch-ivybridge / pch.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2014 Google, Inc
 *
 * From Coreboot src/southbridge/intel/bd82x6x/pch.h
 *
 * Copyright (C) 2008-2009 coresystems GmbH
 * Copyright (C) 2012 The Chromium OS Authors.  All rights reserved.
 */

#ifndef _ASM_ARCH_PCH_H
#define _ASM_ARCH_PCH_H

#include <pci.h>

/* PCH types */
#define PCH_TYPE_CPT	0x1c /* CougarPoint */
#define PCH_TYPE_PPT	0x1e /* IvyBridge */

/* PCH stepping values for LPC device */
#define PCH_STEP_A0	0
#define PCH_STEP_A1	1
#define PCH_STEP_B0	2
#define PCH_STEP_B1	3
#define PCH_STEP_B2	4
#define PCH_STEP_B3	5
#define DEFAULT_GPIOBASE	0x0480
#define DEFAULT_PMBASE		0x0500

#define SMBUS_IO_BASE		0x0400

#define MAINBOARD_POWER_OFF	0
#define MAINBOARD_POWER_ON	1
#define MAINBOARD_POWER_KEEP	2

/* PCI Configuration Space (D30:F0): PCI2PCI */
#define PSTS	0x06
#define SMLT	0x1b
#define SECSTS	0x1e
#define INTR	0x3c
#define BCTRL	0x3e
#define   SBR	(1 << 6)
#define   SEE	(1 << 1)
#define   PERE	(1 << 0)

#define PCH_EHCI1_DEV		PCI_BDF(0, 0x1d, 0)
#define PCH_EHCI2_DEV		PCI_BDF(0, 0x1a, 0)
#define PCH_XHCI_DEV		PCI_BDF(0, 0x14, 0)
#define PCH_ME_DEV		PCI_BDF(0, 0x16, 0)
#define PCH_PCIE_DEV_SLOT	28

#define PCH_DEV			PCI_BDF(0, 0, 0)
#define PCH_VIDEO_DEV		PCI_BDF(0, 2, 0)

/* PCI Configuration Space (D31:F0): LPC */
#define PCH_LPC_DEV		PCI_BDF(0, 0x1f, 0)
#define SERIRQ_CNTL		0x64

#define GEN_PMCON_1		0xa0
#define GEN_PMCON_2		0xa2
#define GEN_PMCON_3		0xa4
#define ETR3			0xac
#define  ETR3_CWORWRE		(1 << 18)
#define  ETR3_CF9GR		(1 << 20)

/* GEN_PMCON_3 bits */
#define RTC_BATTERY_DEAD	(1 << 2)
#define RTC_POWER_FAILED	(1 << 1)
#define SLEEP_AFTER_POWER_FAIL	(1 << 0)

#define BIOS_CNTL		0xDC
#define GPIO_BASE		0x48 /* LPC GPIO Base Address Register */
#define GPIO_CNTL		0x4C /* LPC GPIO Control Register */
#define GPIO_ROUT		0xb8

#define PIRQA_ROUT		0x60
#define PIRQB_ROUT		0x61
#define PIRQC_ROUT		0x62
#define PIRQD_ROUT		0x63
#define PIRQE_ROUT		0x68
#define PIRQF_ROUT		0x69
#define PIRQG_ROUT		0x6A
#define PIRQH_ROUT		0x6B

#define GEN_PMCON_1		0xa0
#define GEN_PMCON_2		0xa2
#define GEN_PMCON_3		0xa4
#define ETR3			0xac
#define  ETR3_CWORWRE		(1 << 18)
#define  ETR3_CF9GR		(1 << 20)

#define PMBASE			0x40
#define ACPI_CNTL		0x44
#define BIOS_CNTL		0xDC
#define GPIO_BASE		0x48 /* LPC GPIO Base Address Register */
#define GPIO_CNTL		0x4C /* LPC GPIO Control Register */
#define GPIO_ROUT		0xb8

/* PCI Configuration Space (D31:F1): IDE */
#define PCH_IDE_DEV		PCI_BDF(0, 0x1f, 1)
#define PCH_SATA_DEV		PCI_BDF(0, 0x1f, 2)
#define PCH_SATA2_DEV		PCI_BDF(0, 0x1f, 5)

#define IDE_SDMA_CNT		0x48	/* Synchronous DMA control */
#define   IDE_SSDE1		(1 <<  3)
#define   IDE_SSDE0		(1 <<  2)
#define   IDE_PSDE1		(1 <<  1)
#define   IDE_PSDE0		(1 <<  0)

#define IDE_SDMA_TIM		0x4a

#define IDE_CONFIG		0x54	/* IDE I/O Configuration Register */
#define   SIG_MODE_SEC_NORMAL	(0 << 18)
#define   SIG_MODE_SEC_TRISTATE	(1 << 18)
#define   SIG_MODE_SEC_DRIVELOW	(2 << 18)
#define   SIG_MODE_PRI_NORMAL	(0 << 16)
#define   SIG_MODE_PRI_TRISTATE	(1 << 16)
#define   SIG_MODE_PRI_DRIVELOW	(2 << 16)
#define   FAST_SCB1		(1 << 15)
#define   FAST_SCB0		(1 << 14)
#define   FAST_PCB1		(1 << 13)
#define   FAST_PCB0		(1 << 12)
#define   SCB1			(1 <<  3)
#define   SCB0			(1 <<  2)
#define   PCB1			(1 <<  1)
#define   PCB0			(1 <<  0)

#define SATA_SIRI		0xa0 /* SATA Indexed Register Index */
#define SATA_SIRD		0xa4 /* SATA Indexed Register Data */
#define SATA_SP			0xd0 /* Scratchpad */

/* SATA IOBP Registers */
#define SATA_IOBP_SP0G3IR	0xea000151
#define SATA_IOBP_SP1G3IR	0xea000051

#define VCH		0x0000	/* 32bit */
#define VCAP1		0x0004	/* 32bit */
#define VCAP2		0x0008	/* 32bit */
#define PVC		0x000c	/* 16bit */
#define PVS		0x000e	/* 16bit */

#define V0CAP		0x0010	/* 32bit */
#define V0CTL		0x0014	/* 32bit */
#define V0STS		0x001a	/* 16bit */

#define V1CAP		0x001c	/* 32bit */
#define V1CTL		0x0020	/* 32bit */
#define V1STS		0x0026	/* 16bit */

#define RCTCL		0x0100	/* 32bit */
#define ESD		0x0104	/* 32bit */
#define ULD		0x0110	/* 32bit */
#define ULBA		0x0118	/* 64bit */

#define RP1D		0x0120	/* 32bit */
#define RP1BA		0x0128	/* 64bit */
#define RP2D		0x0130	/* 32bit */
#define RP2BA		0x0138	/* 64bit */
#define RP3D		0x0140	/* 32bit */
#define RP3BA		0x0148	/* 64bit */
#define RP4D		0x0150	/* 32bit */
#define RP4BA		0x0158	/* 64bit */
#define HDD		0x0160	/* 32bit */
#define HDBA		0x0168	/* 64bit */
#define RP5D		0x0170	/* 32bit */
#define RP5BA		0x0178	/* 64bit */
#define RP6D		0x0180	/* 32bit */
#define RP6BA		0x0188	/* 64bit */

#define RPC		0x0400	/* 32bit */
#define RPFN		0x0404	/* 32bit */

#define TRSR		0x1e00	/*  8bit */
#define TRCR		0x1e10	/* 64bit */
#define TWDR		0x1e18	/* 64bit */

#define IOTR0		0x1e80	/* 64bit */
#define IOTR1		0x1e88	/* 64bit */
#define IOTR2		0x1e90	/* 64bit */
#define IOTR3		0x1e98	/* 64bit */

#define TCTL		0x3000	/*  8bit */

#define NOINT		0
#define INTA		1
#define INTB		2
#define INTC		3
#define INTD		4

#define DIR_IDR		12	/* Interrupt D Pin Offset */
#define DIR_ICR		8	/* Interrupt C Pin Offset */
#define DIR_IBR		4	/* Interrupt B Pin Offset */
#define DIR_IAR		0	/* Interrupt A Pin Offset */

#define PIRQA		0
#define PIRQB		1
#define PIRQC		2
#define PIRQD		3
#define PIRQE		4
#define PIRQF		5
#define PIRQG		6
#define PIRQH		7

/* IO Buffer Programming */
#define IOBPIRI		0x2330
#define IOBPD		0x2334
#define IOBPS		0x2338
#define  IOBPS_RW_BX    ((1 << 9)|(1 << 10))
#define  IOBPS_WRITE_AX	((1 << 9)|(1 << 10))
#define  IOBPS_READ_AX	((1 << 8)|(1 << 9)|(1 << 10))

#define D31IP		0x3100	/* 32bit */
#define D31IP_TTIP	24	/* Thermal Throttle Pin */
#define D31IP_SIP2	20	/* SATA Pin 2 */
#define D31IP_SMIP	12	/* SMBUS Pin */
#define D31IP_SIP	8	/* SATA Pin */
#define D30IP		0x3104	/* 32bit */
#define D30IP_PIP	0	/* PCI Bridge Pin */
#define D29IP		0x3108	/* 32bit */
#define D29IP_E1P	0	/* EHCI #1 Pin */
#define D28IP		0x310c	/* 32bit */
#define D28IP_P8IP	28	/* PCI Express Port 8 */
#define D28IP_P7IP	24	/* PCI Express Port 7 */
#define D28IP_P6IP	20	/* PCI Express Port 6 */
#define D28IP_P5IP	16	/* PCI Express Port 5 */
#define D28IP_P4IP	12	/* PCI Express Port 4 */
#define D28IP_P3IP	8	/* PCI Express Port 3 */
#define D28IP_P2IP	4	/* PCI Express Port 2 */
#define D28IP_P1IP	0	/* PCI Express Port 1 */
#define D27IP		0x3110	/* 32bit */
#define D27IP_ZIP	0	/* HD Audio Pin */
#define D26IP		0x3114	/* 32bit */
#define D26IP_E2P	0	/* EHCI #2 Pin */
#define D25IP		0x3118	/* 32bit */
#define D25IP_LIP	0	/* GbE LAN Pin */
#define D22IP		0x3124	/* 32bit */
#define D22IP_KTIP	12	/* KT Pin */
#define D22IP_IDERIP	8	/* IDE-R Pin */
#define D22IP_MEI2IP	4	/* MEI #2 Pin */
#define D22IP_MEI1IP	0	/* MEI #1 Pin */
#define D20IP		0x3128  /* 32bit */
#define D20IP_XHCIIP	0
#define D31IR		0x3140	/* 16bit */
#define D30IR		0x3142	/* 16bit */
#define D29IR		0x3144	/* 16bit */
#define D28IR		0x3146	/* 16bit */
#define D27IR		0x3148	/* 16bit */
#define D26IR		0x314c	/* 16bit */
#define D25IR		0x3150	/* 16bit */
#define D22IR		0x315c	/* 16bit */
#define D20IR		0x3160	/* 16bit */
#define OIC		0x31fe	/* 16bit */

#define SPI_FREQ_SWSEQ	0x3893
#define SPI_DESC_COMP0	0x38b0
#define SPI_FREQ_WR_ERA	0x38b4

#define DIR_ROUTE(a, b, c, d) \
		(((d) << DIR_IDR) | ((c) << DIR_ICR) | \
			((b) << DIR_IBR) | ((a) << DIR_IAR))

#define HPTC		0x3404	/* 32bit */
#define BUC		0x3414	/* 32bit */
#define PCH_DISABLE_GBE		(1 << 5)
#define FD		0x3418	/* 32bit */
#define DISPBDF		0x3424  /* 16bit */
#define FD2		0x3428	/* 32bit */
#define CG		0x341c	/* 32bit */

/* Function Disable 1 RCBA 0x3418 */
#define PCH_DISABLE_ALWAYS	((1 << 0)|(1 << 26))
#define PCH_DISABLE_P2P		(1 << 1)
#define PCH_DISABLE_SATA1	(1 << 2)
#define PCH_DISABLE_SMBUS	(1 << 3)
#define PCH_DISABLE_HD_AUDIO	(1 << 4)
#define PCH_DISABLE_EHCI2	(1 << 13)
#define PCH_DISABLE_LPC		(1 << 14)
#define PCH_DISABLE_EHCI1	(1 << 15)
#define PCH_DISABLE_PCIE(x)	(1 << (16 + x))
#define PCH_DISABLE_THERMAL	(1 << 24)
#define PCH_DISABLE_SATA2	(1 << 25)
#define PCH_DISABLE_XHCI	(1 << 27)

/* Function Disable 2 RCBA 0x3428 */
#define PCH_DISABLE_KT		(1 << 4)
#define PCH_DISABLE_IDER	(1 << 3)
#define PCH_DISABLE_MEI2	(1 << 2)
#define PCH_DISABLE_MEI1	(1 << 1)
#define PCH_ENABLE_DBDF		(1 << 0)

/* ICH7 GPIOBASE */
#define GPIO_USE_SEL	0x00
#define GP_IO_SEL	0x04
#define GP_LVL		0x0c
#define GPO_BLINK	0x18
#define GPI_INV		0x2c
#define GPIO_USE_SEL2	0x30
#define GP_IO_SEL2	0x34
#define GP_LVL2		0x38
#define GPIO_USE_SEL3	0x40
#define GP_IO_SEL3	0x44
#define GP_LVL3		0x48
#define GP_RST_SEL1	0x60
#define GP_RST_SEL2	0x64
#define GP_RST_SEL3	0x68

/* ICH7 PMBASE */
#define PM1_STS		0x00
#define   WAK_STS	(1 << 15)
#define   PCIEXPWAK_STS	(1 << 14)
#define   PRBTNOR_STS	(1 << 11)
#define   RTC_STS	(1 << 10)
#define   PWRBTN_STS	(1 << 8)
#define   GBL_STS	(1 << 5)
#define   BM_STS	(1 << 4)
#define   TMROF_STS	(1 << 0)
#define PM1_EN		0x02
#define   PCIEXPWAK_DIS	(1 << 14)
#define   RTC_EN	(1 << 10)
#define   PWRBTN_EN	(1 << 8)
#define   GBL_EN	(1 << 5)
#define   TMROF_EN	(1 << 0)
#define PM1_CNT		0x04
#define   SLP_EN	(1 << 13)
#define   SLP_TYP	(7 << 10)
#define    SLP_TYP_S0	0
#define    SLP_TYP_S1	1
#define    SLP_TYP_S3	5
#define    SLP_TYP_S4	6
#define    SLP_TYP_S5	7
#define   GBL_RLS	(1 << 2)
#define   BM_RLD	(1 << 1)
#define   SCI_EN	(1 << 0)
#define PM1_TMR		0x08
#define PROC_CNT	0x10
#define LV2		0x14
#define LV3		0x15
#define LV4		0x16
#define PM2_CNT		0x50 /* mobile only */
#define GPE0_STS	0x20
#define   PME_B0_STS	(1 << 13)
#define   PME_STS	(1 << 11)
#define   BATLOW_STS	(1 << 10)
#define   PCI_EXP_STS	(1 << 9)
#define   RI_STS	(1 << 8)
#define   SMB_WAK_STS	(1 << 7)
#define   TCOSCI_STS	(1 << 6)
#define   SWGPE_STS	(1 << 2)
#define   HOT_PLUG_STS	(1 << 1)
#define GPE0_EN		0x28
#define   PME_B0_EN	(1 << 13)
#define   PME_EN	(1 << 11)
#define   TCOSCI_EN	(1 << 6)
#define SMI_EN		0x30
#define   INTEL_USB2_EN	 (1 << 18) /* Intel-Specific USB2 SMI logic */
#define   LEGACY_USB2_EN (1 << 17) /* Legacy USB2 SMI logic */
#define   PERIODIC_EN	 (1 << 14) /* SMI on PERIODIC_STS in SMI_STS */
#define   TCO_EN	 (1 << 13) /* Enable TCO Logic (BIOSWE et al) */
#define   MCSMI_EN	 (1 << 11) /* Trap microcontroller range access */
#define   BIOS_RLS	 (1 <<  7) /* asserts SCI on bit set */
#define   SWSMI_TMR_EN	 (1 <<  6) /* start software smi timer on bit set */
#define   APMC_EN	 (1 <<  5) /* Writes to APM_CNT cause SMI# */
#define   SLP_SMI_EN	 (1 <<  4) /* Write SLP_EN in PM1_CNT asserts SMI# */
#define   LEGACY_USB_EN  (1 <<  3) /* Legacy USB circuit SMI logic */
#define   BIOS_EN	 (1 <<  2) /* Assert SMI# on setting GBL_RLS bit */
#define   EOS		 (1 <<  1) /* End of SMI (deassert SMI#) */
#define   GBL_SMI_EN	 (1 <<  0) /* SMI# generation at all? */
#define SMI_STS		0x34
#define ALT_GP_SMI_EN	0x38
#define ALT_GP_SMI_STS	0x3a
#define GPE_CNTL	0x42
#define DEVACT_STS	0x44
#define SS_CNT		0x50
#define C3_RES		0x54
#define TCO1_STS	0x64
#define   DMISCI_STS	(1 << 9)
#define TCO2_STS	0x66

/**
 * pch_silicon_revision() - Read silicon device ID from the PCH
 *
 * @dev:	PCH device
 * @return silicon device ID
 */
int pch_silicon_type(struct udevice *dev);

/**
 * pch_pch_iobp_update() - Update a pch register
 *
 * @dev:	PCH device
 * @address:	Address to update
 * @andvalue:	Value to AND with existing value
 * @orvalue:	Value to OR with existing value
 */
void pch_iobp_update(struct udevice *dev, u32 address, u32 andvalue,
			     u32 orvalue);

#endif
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0 */
2b605154 SG	2	/*
	3	* Copyright (c) 2014 Google, Inc
	4	*
	5	* From Coreboot src/southbridge/intel/bd82x6x/pch.h
	6	*
	7	* Copyright (C) 2008-2009 coresystems GmbH
	8	* Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
2b605154 SG	9	*/
	10
	11	#ifndef _ASM_ARCH_PCH_H
	12	#define _ASM_ARCH_PCH_H
	13
	14	#include <pci.h>
	15
8c74a573 SG	16	/* PCH types */
	17	#define PCH_TYPE_CPT 0x1c /* CougarPoint */
	18	#define PCH_TYPE_PPT 0x1e /* IvyBridge */
	19
	20	/* PCH stepping values for LPC device */
	21	#define PCH_STEP_A0 0
	22	#define PCH_STEP_A1 1
	23	#define PCH_STEP_B0 2
	24	#define PCH_STEP_B1 3
	25	#define PCH_STEP_B2 4
	26	#define PCH_STEP_B3 5
8e0df066 SG	27	#define DEFAULT_GPIOBASE 0x0480
	28	#define DEFAULT_PMBASE 0x0500
	29
	30	#define SMBUS_IO_BASE 0x0400
	31
8c74a573 SG	32	#define MAINBOARD_POWER_OFF 0
	33	#define MAINBOARD_POWER_ON 1
	34	#define MAINBOARD_POWER_KEEP 2
	35
4e7a6aca SG	36	/* PCI Configuration Space (D30:F0): PCI2PCI */
	37	#define PSTS 0x06
	38	#define SMLT 0x1b
	39	#define SECSTS 0x1e
	40	#define INTR 0x3c
	41	#define BCTRL 0x3e
	42	#define SBR (1 << 6)
	43	#define SEE (1 << 1)
	44	#define PERE (1 << 0)
	45
8e0df066 SG	46	#define PCH_EHCI1_DEV PCI_BDF(0, 0x1d, 0)
	47	#define PCH_EHCI2_DEV PCI_BDF(0, 0x1a, 0)
	48	#define PCH_XHCI_DEV PCI_BDF(0, 0x14, 0)
	49	#define PCH_ME_DEV PCI_BDF(0, 0x16, 0)
	50	#define PCH_PCIE_DEV_SLOT 28
	51
	52	#define PCH_DEV PCI_BDF(0, 0, 0)
	53	#define PCH_VIDEO_DEV PCI_BDF(0, 2, 0)
	54
2b605154 SG	55	/* PCI Configuration Space (D31:F0): LPC */
2b605154 SG	56	#define PCH_LPC_DEV PCI_BDF(0, 0x1f, 0)
8c74a573 SG	57	#define SERIRQ_CNTL 0x64
	58
	59	#define GEN_PMCON_1 0xa0
	60	#define GEN_PMCON_2 0xa2
	61	#define GEN_PMCON_3 0xa4
	62	#define ETR3 0xac
	63	#define ETR3_CWORWRE (1 << 18)
	64	#define ETR3_CF9GR (1 << 20)
	65
	66	/* GEN_PMCON_3 bits */
	67	#define RTC_BATTERY_DEAD (1 << 2)
	68	#define RTC_POWER_FAILED (1 << 1)
	69	#define SLEEP_AFTER_POWER_FAIL (1 << 0)
	70
8c74a573 SG	71	#define BIOS_CNTL 0xDC
	72	#define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */
	73	#define GPIO_CNTL 0x4C /* LPC GPIO Control Register */
	74	#define GPIO_ROUT 0xb8
	75
	76	#define PIRQA_ROUT 0x60
	77	#define PIRQB_ROUT 0x61
	78	#define PIRQC_ROUT 0x62
	79	#define PIRQD_ROUT 0x63
	80	#define PIRQE_ROUT 0x68
	81	#define PIRQF_ROUT 0x69
	82	#define PIRQG_ROUT 0x6A
	83	#define PIRQH_ROUT 0x6B
2b605154	84
65dd74a6 SG	85	#define GEN_PMCON_1 0xa0
	86	#define GEN_PMCON_2 0xa2
	87	#define GEN_PMCON_3 0xa4
	88	#define ETR3 0xac
	89	#define ETR3_CWORWRE (1 << 18)
	90	#define ETR3_CF9GR (1 << 20)
	91
8e0df066 SG	92	#define PMBASE 0x40
	93	#define ACPI_CNTL 0x44
	94	#define BIOS_CNTL 0xDC
	95	#define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */
	96	#define GPIO_CNTL 0x4C /* LPC GPIO Control Register */
	97	#define GPIO_ROUT 0xb8
	98
3ac83935 SG	99	/* PCI Configuration Space (D31:F1): IDE */
	100	#define PCH_IDE_DEV PCI_BDF(0, 0x1f, 1)
	101	#define PCH_SATA_DEV PCI_BDF(0, 0x1f, 2)
	102	#define PCH_SATA2_DEV PCI_BDF(0, 0x1f, 5)
	103
3ac83935 SG	104	#define IDE_SDMA_CNT 0x48 /* Synchronous DMA control */
	105	#define IDE_SSDE1 (1 << 3)
	106	#define IDE_SSDE0 (1 << 2)
	107	#define IDE_PSDE1 (1 << 1)
	108	#define IDE_PSDE0 (1 << 0)
	109
	110	#define IDE_SDMA_TIM 0x4a
	111
	112	#define IDE_CONFIG 0x54 /* IDE I/O Configuration Register */
	113	#define SIG_MODE_SEC_NORMAL (0 << 18)
	114	#define SIG_MODE_SEC_TRISTATE (1 << 18)
	115	#define SIG_MODE_SEC_DRIVELOW (2 << 18)
	116	#define SIG_MODE_PRI_NORMAL (0 << 16)
	117	#define SIG_MODE_PRI_TRISTATE (1 << 16)
	118	#define SIG_MODE_PRI_DRIVELOW (2 << 16)
	119	#define FAST_SCB1 (1 << 15)
	120	#define FAST_SCB0 (1 << 14)
	121	#define FAST_PCB1 (1 << 13)
	122	#define FAST_PCB0 (1 << 12)
	123	#define SCB1 (1 << 3)
	124	#define SCB0 (1 << 2)
	125	#define PCB1 (1 << 1)
	126	#define PCB0 (1 << 0)
	127
	128	#define SATA_SIRI 0xa0 /* SATA Indexed Register Index */
	129	#define SATA_SIRD 0xa4 /* SATA Indexed Register Data */
	130	#define SATA_SP 0xd0 /* Scratchpad */
	131
	132	/* SATA IOBP Registers */
	133	#define SATA_IOBP_SP0G3IR 0xea000151
	134	#define SATA_IOBP_SP1G3IR 0xea000051
	135
f5fbbe95 SG	136	#define VCH 0x0000 /* 32bit */
	137	#define VCAP1 0x0004 /* 32bit */
	138	#define VCAP2 0x0008 /* 32bit */
	139	#define PVC 0x000c /* 16bit */
	140	#define PVS 0x000e /* 16bit */
	141
	142	#define V0CAP 0x0010 /* 32bit */
	143	#define V0CTL 0x0014 /* 32bit */
	144	#define V0STS 0x001a /* 16bit */
	145
	146	#define V1CAP 0x001c /* 32bit */
	147	#define V1CTL 0x0020 /* 32bit */
	148	#define V1STS 0x0026 /* 16bit */
	149
	150	#define RCTCL 0x0100 /* 32bit */
	151	#define ESD 0x0104 /* 32bit */
	152	#define ULD 0x0110 /* 32bit */
	153	#define ULBA 0x0118 /* 64bit */
	154
	155	#define RP1D 0x0120 /* 32bit */
	156	#define RP1BA 0x0128 /* 64bit */
	157	#define RP2D 0x0130 /* 32bit */
	158	#define RP2BA 0x0138 /* 64bit */
	159	#define RP3D 0x0140 /* 32bit */
	160	#define RP3BA 0x0148 /* 64bit */
	161	#define RP4D 0x0150 /* 32bit */
	162	#define RP4BA 0x0158 /* 64bit */
	163	#define HDD 0x0160 /* 32bit */
	164	#define HDBA 0x0168 /* 64bit */
	165	#define RP5D 0x0170 /* 32bit */
	166	#define RP5BA 0x0178 /* 64bit */
	167	#define RP6D 0x0180 /* 32bit */
	168	#define RP6BA 0x0188 /* 64bit */
	169
	170	#define RPC 0x0400 /* 32bit */
	171	#define RPFN 0x0404 /* 32bit */
	172
65dd74a6 SG	173	#define TRSR 0x1e00 /* 8bit */
	174	#define TRCR 0x1e10 /* 64bit */
	175	#define TWDR 0x1e18 /* 64bit */
	176
	177	#define IOTR0 0x1e80 /* 64bit */
	178	#define IOTR1 0x1e88 /* 64bit */
	179	#define IOTR2 0x1e90 /* 64bit */
	180	#define IOTR3 0x1e98 /* 64bit */
	181
	182	#define TCTL 0x3000 /* 8bit */
	183
	184	#define NOINT 0
	185	#define INTA 1
	186	#define INTB 2
	187	#define INTC 3
	188	#define INTD 4
	189
	190	#define DIR_IDR 12 /* Interrupt D Pin Offset */
	191	#define DIR_ICR 8 /* Interrupt C Pin Offset */
	192	#define DIR_IBR 4 /* Interrupt B Pin Offset */
	193	#define DIR_IAR 0 /* Interrupt A Pin Offset */
	194
	195	#define PIRQA 0
	196	#define PIRQB 1
	197	#define PIRQC 2
	198	#define PIRQD 3
	199	#define PIRQE 4
	200	#define PIRQF 5
	201	#define PIRQG 6
	202	#define PIRQH 7
	203
	204	/* IO Buffer Programming */
	205	#define IOBPIRI 0x2330
	206	#define IOBPD 0x2334
	207	#define IOBPS 0x2338
	208	#define IOBPS_RW_BX ((1 << 9)\|(1 << 10))
	209	#define IOBPS_WRITE_AX ((1 << 9)\|(1 << 10))
	210	#define IOBPS_READ_AX ((1 << 8)\|(1 << 9)\|(1 << 10))
	211
	212	#define D31IP 0x3100 /* 32bit */
	213	#define D31IP_TTIP 24 /* Thermal Throttle Pin */
	214	#define D31IP_SIP2 20 /* SATA Pin 2 */
	215	#define D31IP_SMIP 12 /* SMBUS Pin */
	216	#define D31IP_SIP 8 /* SATA Pin */
	217	#define D30IP 0x3104 /* 32bit */
	218	#define D30IP_PIP 0 /* PCI Bridge Pin */
	219	#define D29IP 0x3108 /* 32bit */
	220	#define D29IP_E1P 0 /* EHCI #1 Pin */
	221	#define D28IP 0x310c /* 32bit */
	222	#define D28IP_P8IP 28 /* PCI Express Port 8 */
	223	#define D28IP_P7IP 24 /* PCI Express Port 7 */
	224	#define D28IP_P6IP 20 /* PCI Express Port 6 */
	225	#define D28IP_P5IP 16 /* PCI Express Port 5 */
	226	#define D28IP_P4IP 12 /* PCI Express Port 4 */
	227	#define D28IP_P3IP 8 /* PCI Express Port 3 */
	228	#define D28IP_P2IP 4 /* PCI Express Port 2 */
	229	#define D28IP_P1IP 0 /* PCI Express Port 1 */
	230	#define D27IP 0x3110 /* 32bit */
	231	#define D27IP_ZIP 0 /* HD Audio Pin */
	232	#define D26IP 0x3114 /* 32bit */
	233	#define D26IP_E2P 0 /* EHCI #2 Pin */
	234	#define D25IP 0x3118 /* 32bit */
	235	#define D25IP_LIP 0 /* GbE LAN Pin */
	236	#define D22IP 0x3124 /* 32bit */
237	#define D22IP_KTIP 12 /* KT Pin */
238	#define D22IP_IDERIP 8 /* IDE-R Pin */
239	#define D22IP_MEI2IP 4 /* MEI #2 Pin */
240	#define D22IP_MEI1IP 0 /* MEI #1 Pin */
241	#define D20IP 0x3128 /* 32bit */
242	#define D20IP_XHCIIP 0
243	#define D31IR 0x3140 /* 16bit */
244	#define D30IR 0x3142 /* 16bit */
245	#define D29IR 0x3144 /* 16bit */
246	#define D28IR 0x3146 /* 16bit */
247	#define D27IR 0x3148 /* 16bit */
248	#define D26IR 0x314c /* 16bit */
249	#define D25IR 0x3150 /* 16bit */
250	#define D22IR 0x315c /* 16bit */
251	#define D20IR 0x3160 /* 16bit */
252	#define OIC 0x31fe /* 16bit */
253
f5fbbe95 SG	254	#define SPI_FREQ_SWSEQ 0x3893
	255	#define SPI_DESC_COMP0 0x38b0
	256	#define SPI_FREQ_WR_ERA 0x38b4
f5fbbe95	257
65dd74a6 SG	258	#define DIR_ROUTE(a, b, c, d) \
	259	(((d) << DIR_IDR) \| ((c) << DIR_ICR) \| \
	260	((b) << DIR_IBR) \| ((a) << DIR_IAR))
	261
f5fbbe95	262	#define HPTC 0x3404 /* 32bit */
f5fbbe95 SG	263	#define BUC 0x3414 /* 32bit */
	264	#define PCH_DISABLE_GBE (1 << 5)
	265	#define FD 0x3418 /* 32bit */
	266	#define DISPBDF 0x3424 /* 16bit */
	267	#define FD2 0x3428 /* 32bit */
	268	#define CG 0x341c /* 32bit */
	269
65dd74a6 SG	270	/* Function Disable 1 RCBA 0x3418 */
	271	#define PCH_DISABLE_ALWAYS ((1 << 0)\|(1 << 26))
	272	#define PCH_DISABLE_P2P (1 << 1)
	273	#define PCH_DISABLE_SATA1 (1 << 2)
	274	#define PCH_DISABLE_SMBUS (1 << 3)
	275	#define PCH_DISABLE_HD_AUDIO (1 << 4)
	276	#define PCH_DISABLE_EHCI2 (1 << 13)
	277	#define PCH_DISABLE_LPC (1 << 14)
	278	#define PCH_DISABLE_EHCI1 (1 << 15)
	279	#define PCH_DISABLE_PCIE(x) (1 << (16 + x))
	280	#define PCH_DISABLE_THERMAL (1 << 24)
	281	#define PCH_DISABLE_SATA2 (1 << 25)
	282	#define PCH_DISABLE_XHCI (1 << 27)
	283
	284	/* Function Disable 2 RCBA 0x3428 */
	285	#define PCH_DISABLE_KT (1 << 4)
	286	#define PCH_DISABLE_IDER (1 << 3)
	287	#define PCH_DISABLE_MEI2 (1 << 2)
	288	#define PCH_DISABLE_MEI1 (1 << 1)
	289	#define PCH_ENABLE_DBDF (1 << 0)
	290
1b4f25ff SG	291	/* ICH7 GPIOBASE */
	292	#define GPIO_USE_SEL 0x00
	293	#define GP_IO_SEL 0x04
	294	#define GP_LVL 0x0c
	295	#define GPO_BLINK 0x18
	296	#define GPI_INV 0x2c
	297	#define GPIO_USE_SEL2 0x30
	298	#define GP_IO_SEL2 0x34
	299	#define GP_LVL2 0x38
	300	#define GPIO_USE_SEL3 0x40
	301	#define GP_IO_SEL3 0x44
	302	#define GP_LVL3 0x48
	303	#define GP_RST_SEL1 0x60
	304	#define GP_RST_SEL2 0x64
	305	#define GP_RST_SEL3 0x68
	306
8e0df066 SG	307	/* ICH7 PMBASE */
	308	#define PM1_STS 0x00
	309	#define WAK_STS (1 << 15)
	310	#define PCIEXPWAK_STS (1 << 14)
	311	#define PRBTNOR_STS (1 << 11)
	312	#define RTC_STS (1 << 10)
	313	#define PWRBTN_STS (1 << 8)
	314	#define GBL_STS (1 << 5)
	315	#define BM_STS (1 << 4)
	316	#define TMROF_STS (1 << 0)
	317	#define PM1_EN 0x02
	318	#define PCIEXPWAK_DIS (1 << 14)
	319	#define RTC_EN (1 << 10)
	320	#define PWRBTN_EN (1 << 8)
	321	#define GBL_EN (1 << 5)
	322	#define TMROF_EN (1 << 0)
	323	#define PM1_CNT 0x04
	324	#define SLP_EN (1 << 13)
	325	#define SLP_TYP (7 << 10)
	326	#define SLP_TYP_S0 0
	327	#define SLP_TYP_S1 1
	328	#define SLP_TYP_S3 5
	329	#define SLP_TYP_S4 6
	330	#define SLP_TYP_S5 7
	331	#define GBL_RLS (1 << 2)
	332	#define BM_RLD (1 << 1)
	333	#define SCI_EN (1 << 0)
	334	#define PM1_TMR 0x08
	335	#define PROC_CNT 0x10
	336	#define LV2 0x14
	337	#define LV3 0x15
	338	#define LV4 0x16
	339	#define PM2_CNT 0x50 /* mobile only */
	340	#define GPE0_STS 0x20
	341	#define PME_B0_STS (1 << 13)
	342	#define PME_STS (1 << 11)
	343	#define BATLOW_STS (1 << 10)
	344	#define PCI_EXP_STS (1 << 9)
	345	#define RI_STS (1 << 8)
	346	#define SMB_WAK_STS (1 << 7)
	347	#define TCOSCI_STS (1 << 6)
	348	#define SWGPE_STS (1 << 2)
	349	#define HOT_PLUG_STS (1 << 1)
	350	#define GPE0_EN 0x28
	351	#define PME_B0_EN (1 << 13)
	352	#define PME_EN (1 << 11)
	353	#define TCOSCI_EN (1 << 6)
	354	#define SMI_EN 0x30
	355	#define INTEL_USB2_EN (1 << 18) /* Intel-Specific USB2 SMI logic */
	356	#define LEGACY_USB2_EN (1 << 17) /* Legacy USB2 SMI logic */
	357	#define PERIODIC_EN (1 << 14) /* SMI on PERIODIC_STS in SMI_STS */
	358	#define TCO_EN (1 << 13) /* Enable TCO Logic (BIOSWE et al) */
	359	#define MCSMI_EN (1 << 11) /* Trap microcontroller range access */
	360	#define BIOS_RLS (1 << 7) /* asserts SCI on bit set */
	361	#define SWSMI_TMR_EN (1 << 6) /* start software smi timer on bit set */
	362	#define APMC_EN (1 << 5) /* Writes to APM_CNT cause SMI# */
	363	#define SLP_SMI_EN (1 << 4) /* Write SLP_EN in PM1_CNT asserts SMI# */
	364	#define LEGACY_USB_EN (1 << 3) /* Legacy USB circuit SMI logic */
	365	#define BIOS_EN (1 << 2) /* Assert SMI# on setting GBL_RLS bit */
	366	#define EOS (1 << 1) /* End of SMI (deassert SMI#) */
	367	#define GBL_SMI_EN (1 << 0) /* SMI# generation at all? */
	368	#define SMI_STS 0x34
	369	#define ALT_GP_SMI_EN 0x38
	370	#define ALT_GP_SMI_STS 0x3a
371	#define GPE_CNTL 0x42
372	#define DEVACT_STS 0x44
373	#define SS_CNT 0x50
374	#define C3_RES 0x54
375	#define TCO1_STS 0x64
376	#define DMISCI_STS (1 << 9)
377	#define TCO2_STS 0x66
378
9434c7a3 SG	379	/**
	380	* pch_silicon_revision() - Read silicon device ID from the PCH
	381	*
	382	* @dev: PCH device
	383	* @return silicon device ID
	384	*/
	385	int pch_silicon_type(struct udevice *dev);
	386
9434c7a3 SG	387	/**
	388	* pch_pch_iobp_update() - Update a pch register
	389	*
	390	* @dev: PCH device
	391	* @address: Address to update
	392	* @andvalue: Value to AND with existing value
	393	* @orvalue: Value to OR with existing value
	394	*/
	395	void pch_iobp_update(struct udevice *dev, u32 address, u32 andvalue,
	396	u32 orvalue);
	397
2b605154	398	#endif