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83d290c5 1/* SPDX-License-Identifier: GPL-2.0+ */
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2/*
3 * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
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4 */
5
6#ifndef _QUARK_IOMAP_H_
7#define _QUARK_IOMAP_H_
8
9/* Memory Mapped IO bases */
10
11/* ESRAM */
12#define ESRAM_BASE_ADDRESS CONFIG_ESRAM_BASE
13#define ESRAM_BASE_SIZE ESRAM_SIZE
14
15/* PCI Configuration Space */
16#define MCFG_BASE_ADDRESS CONFIG_PCIE_ECAM_BASE
17#define MCFG_BASE_SIZE 0x10000000
18
19/* High Performance Event Timer */
20#define HPET_BASE_ADDRESS 0xfed00000
21#define HPET_BASE_SIZE 0x400
22
23/* Root Complex Base Address */
24#define RCBA_BASE_ADDRESS CONFIG_RCBA_BASE
25#define RCBA_BASE_SIZE 0x4000
26
27/* IO Port bases */
28#define ACPI_PM1_BASE_ADDRESS CONFIG_ACPI_PM1_BASE
29#define ACPI_PM1_BASE_SIZE 0x10
30
31#define ACPI_PBLK_BASE_ADDRESS CONFIG_ACPI_PBLK_BASE
32#define ACPI_PBLK_BASE_SIZE 0x10
33
34#define SPI_DMA_BASE_ADDRESS CONFIG_SPI_DMA_BASE
35#define SPI_DMA_BASE_SIZE 0x10
36
37#define GPIO_BASE_ADDRESS CONFIG_GPIO_BASE
38#define GPIO_BASE_SIZE 0x80
39
40#define ACPI_GPE0_BASE_ADDRESS CONFIG_ACPI_GPE0_BASE
41#define ACPI_GPE0_BASE_SIZE 0x40
42
43#define WDT_BASE_ADDRESS CONFIG_WDT_BASE
44#define WDT_BASE_SIZE 0x40
45
46#endif /* _QUARK_IOMAP_H_ */