]> git.ipfire.org Git - thirdparty/u-boot.git/blame - arch/x86/include/asm/coreboot_tables.h
SPDX: Convert all of our single license tags to Linux Kernel style
[thirdparty/u-boot.git] / arch / x86 / include / asm / coreboot_tables.h
CommitLineData
83d290c5 1/* SPDX-License-Identifier: BSD-3-Clause */
63f559cd
GB
2/*
3 * This file is part of the libpayload project.
4 *
5 * Copyright (C) 2008 Advanced Micro Devices, Inc.
63f559cd
GB
6 */
7
8#ifndef _COREBOOT_TABLES_H
9#define _COREBOOT_TABLES_H
10
63f559cd
GB
11struct cbuint64 {
12 u32 lo;
13 u32 hi;
14};
15
16struct cb_header {
17 u8 signature[4];
18 u32 header_bytes;
19 u32 header_checksum;
20 u32 table_bytes;
21 u32 table_checksum;
22 u32 table_entries;
23};
24
25struct cb_record {
26 u32 tag;
27 u32 size;
28};
29
f2d0690e
BM
30#define CB_TAG_UNUSED 0x0000
31#define CB_TAG_MEMORY 0x0001
63f559cd
GB
32
33struct cb_memory_range {
34 struct cbuint64 start;
35 struct cbuint64 size;
36 u32 type;
37};
38
f2d0690e
BM
39#define CB_MEM_RAM 1
40#define CB_MEM_RESERVED 2
41#define CB_MEM_ACPI 3
42#define CB_MEM_NVS 4
43#define CB_MEM_UNUSABLE 5
44#define CB_MEM_VENDOR_RSVD 6
45#define CB_MEM_TABLE 16
63f559cd
GB
46
47struct cb_memory {
48 u32 tag;
49 u32 size;
50 struct cb_memory_range map[0];
51};
52
f2d0690e 53#define CB_TAG_HWRPB 0x0002
63f559cd
GB
54
55struct cb_hwrpb {
56 u32 tag;
57 u32 size;
58 u64 hwrpb;
59};
60
f2d0690e 61#define CB_TAG_MAINBOARD 0x0003
63f559cd
GB
62
63struct cb_mainboard {
64 u32 tag;
65 u32 size;
66 u8 vendor_idx;
67 u8 part_number_idx;
68 u8 strings[0];
69};
70
f2d0690e
BM
71#define CB_TAG_VERSION 0x0004
72#define CB_TAG_EXTRA_VERSION 0x0005
73#define CB_TAG_BUILD 0x0006
74#define CB_TAG_COMPILE_TIME 0x0007
75#define CB_TAG_COMPILE_BY 0x0008
76#define CB_TAG_COMPILE_HOST 0x0009
77#define CB_TAG_COMPILE_DOMAIN 0x000a
78#define CB_TAG_COMPILER 0x000b
79#define CB_TAG_LINKER 0x000c
80#define CB_TAG_ASSEMBLER 0x000d
63f559cd
GB
81
82struct cb_string {
83 u32 tag;
84 u32 size;
85 u8 string[0];
86};
87
f2d0690e 88#define CB_TAG_SERIAL 0x000f
63f559cd
GB
89
90struct cb_serial {
91 u32 tag;
92 u32 size;
f2d0690e
BM
93#define CB_SERIAL_TYPE_IO_MAPPED 1
94#define CB_SERIAL_TYPE_MEMORY_MAPPED 2
63f559cd
GB
95 u32 type;
96 u32 baseaddr;
97 u32 baud;
98};
99
f2d0690e 100#define CB_TAG_CONSOLE 0x0010
63f559cd
GB
101
102struct cb_console {
103 u32 tag;
104 u32 size;
105 u16 type;
106};
107
f2d0690e
BM
108#define CB_TAG_CONSOLE_SERIAL8250 0
109#define CB_TAG_CONSOLE_VGA 1 /* OBSOLETE */
110#define CB_TAG_CONSOLE_BTEXT 2 /* OBSOLETE */
111#define CB_TAG_CONSOLE_LOGBUF 3
112#define CB_TAG_CONSOLE_SROM 4 /* OBSOLETE */
113#define CB_TAG_CONSOLE_EHCI 5
63f559cd 114
f2d0690e 115#define CB_TAG_FORWARD 0x0011
63f559cd
GB
116
117struct cb_forward {
118 u32 tag;
119 u32 size;
120 u64 forward;
121};
122
f2d0690e
BM
123#define CB_TAG_FRAMEBUFFER 0x0012
124
63f559cd
GB
125struct cb_framebuffer {
126 u32 tag;
127 u32 size;
63f559cd
GB
128 u64 physical_address;
129 u32 x_resolution;
130 u32 y_resolution;
131 u32 bytes_per_line;
132 u8 bits_per_pixel;
133 u8 red_mask_pos;
134 u8 red_mask_size;
135 u8 green_mask_pos;
136 u8 green_mask_size;
137 u8 blue_mask_pos;
138 u8 blue_mask_size;
139 u8 reserved_mask_pos;
140 u8 reserved_mask_size;
141};
142
f2d0690e
BM
143#define CB_TAG_GPIO 0x0013
144#define GPIO_MAX_NAME_LENGTH 16
145
402ed004
SG
146struct cb_gpio {
147 u32 port;
148 u32 polarity;
149 u32 value;
150 u8 name[GPIO_MAX_NAME_LENGTH];
151};
152
153struct cb_gpios {
154 u32 tag;
155 u32 size;
402ed004
SG
156 u32 count;
157 struct cb_gpio gpios[0];
158};
159
f2d0690e
BM
160#define CB_TAG_FDT 0x0014
161
402ed004
SG
162struct cb_fdt {
163 uint32_t tag;
164 uint32_t size; /* size of the entire entry */
165 /* the actual FDT gets placed here */
166};
167
f2d0690e
BM
168#define CB_TAG_VDAT 0x0015
169
402ed004
SG
170struct cb_vdat {
171 uint32_t tag;
172 uint32_t size; /* size of the entire entry */
f2d0690e 173 void *vdat_addr;
402ed004
SG
174 uint32_t vdat_size;
175};
176
f2d0690e
BM
177#define CB_TAG_TIMESTAMPS 0x0016
178#define CB_TAG_CBMEM_CONSOLE 0x0017
179#define CB_TAG_MRC_CACHE 0x0018
180
402ed004
SG
181struct cb_cbmem_tab {
182 uint32_t tag;
183 uint32_t size;
f2d0690e 184 void *cbmem_tab;
402ed004
SG
185};
186
f2d0690e
BM
187#define CB_TAG_VBNV 0x0019
188
402ed004
SG
189struct cb_vbnv {
190 uint32_t tag;
191 uint32_t size;
192 uint32_t vbnv_start;
193 uint32_t vbnv_size;
194};
195
f2d0690e
BM
196#define CB_TAG_CMOS_OPTION_TABLE 0x00c8
197
63f559cd
GB
198struct cb_cmos_option_table {
199 u32 tag;
200 u32 size;
201 u32 header_length;
202};
203
f2d0690e
BM
204#define CB_TAG_OPTION 0x00c9
205
206#define CMOS_MAX_NAME_LENGTH 32
207
63f559cd
GB
208struct cb_cmos_entries {
209 u32 tag;
210 u32 size;
211 u32 bit;
212 u32 length;
213 u32 config;
214 u32 config_id;
215 u8 name[CMOS_MAX_NAME_LENGTH];
216};
217
f2d0690e
BM
218#define CB_TAG_OPTION_ENUM 0x00ca
219#define CMOS_MAX_TEXT_LENGTH 32
63f559cd 220
63f559cd
GB
221struct cb_cmos_enums {
222 u32 tag;
223 u32 size;
224 u32 config_id;
225 u32 value;
226 u8 text[CMOS_MAX_TEXT_LENGTH];
227};
228
f2d0690e
BM
229#define CB_TAG_OPTION_DEFAULTS 0x00cb
230#define CMOS_IMAGE_BUFFER_SIZE 128
231
63f559cd
GB
232struct cb_cmos_defaults {
233 u32 tag;
234 u32 size;
235 u32 name_length;
236 u8 name[CMOS_MAX_NAME_LENGTH];
237 u8 default_set[CMOS_IMAGE_BUFFER_SIZE];
238};
239
f2d0690e
BM
240#define CB_TAG_OPTION_CHECKSUM 0x00cc
241#define CHECKSUM_NONE 0
242#define CHECKSUM_PCBIOS 1
243
63f559cd
GB
244struct cb_cmos_checksum {
245 u32 tag;
246 u32 size;
247 u32 range_start;
248 u32 range_end;
249 u32 location;
250 u32 type;
251};
252
253/* Helpful macros */
254
255#define MEM_RANGE_COUNT(_rec) \
256 (((_rec)->size - sizeof(*(_rec))) / sizeof((_rec)->map[0]))
257
258#define MEM_RANGE_PTR(_rec, _idx) \
259 (((u8 *) (_rec)) + sizeof(*(_rec)) \
260 + (sizeof((_rec)->map[0]) * (_idx)))
261
262#define MB_VENDOR_STRING(_mb) \
263 (((unsigned char *) ((_mb)->strings)) + (_mb)->vendor_idx)
264
265#define MB_PART_STRING(_mb) \
266 (((unsigned char *) ((_mb)->strings)) + (_mb)->part_number_idx)
267
268#define UNPACK_CB64(_in) \
269 ((((u64) _in.hi) << 32) | _in.lo)
270
f2d0690e
BM
271#define CBMEM_TOC_RESERVED 512
272#define MAX_CBMEM_ENTRIES 16
273#define CBMEM_MAGIC 0x434f5245
402ed004
SG
274
275struct cbmem_entry {
276 u32 magic;
277 u32 id;
278 u64 base;
279 u64 size;
280} __packed;
281
f2d0690e
BM
282#define CBMEM_ID_FREESPACE 0x46524545
283#define CBMEM_ID_GDT 0x4c474454
284#define CBMEM_ID_ACPI 0x41435049
285#define CBMEM_ID_CBTABLE 0x43425442
286#define CBMEM_ID_PIRQ 0x49525154
287#define CBMEM_ID_MPTABLE 0x534d5054
288#define CBMEM_ID_RESUME 0x5245534d
289#define CBMEM_ID_RESUME_SCRATCH 0x52455343
290#define CBMEM_ID_SMBIOS 0x534d4254
291#define CBMEM_ID_TIMESTAMP 0x54494d45
292#define CBMEM_ID_MRCDATA 0x4d524344
293#define CBMEM_ID_CONSOLE 0x434f4e53
294#define CBMEM_ID_NONE 0x00000000
402ed004 295
789b6dce
BM
296/**
297 * high_table_reserve() - reserve configuration table in high memory
298 *
299 * This reserves configuration table in high memory.
300 *
301 * @return: always 0
302 */
303int high_table_reserve(void);
304
305/**
306 * high_table_malloc() - allocate configuration table in high memory
307 *
308 * This allocates configuration table in high memory.
309 *
310 * @bytes: size of configuration table to be allocated
311 * @return: pointer to configuration table in high memory
312 */
313void *high_table_malloc(size_t bytes);
314
26f9a9b7
BM
315/**
316 * write_coreboot_table() - write coreboot table
317 *
318 * This writes coreboot table at a given address.
319 *
320 * @addr: start address to write coreboot table
321 * @cfg_tables: pointer to configuration table memory area
322 */
323void write_coreboot_table(u32 addr, struct memory_area *cfg_tables);
324
63f559cd 325#endif