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f60df20a MY |
1 | /* |
2 | * (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com> | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | #ifndef __FW_CFG__ | |
8 | #define __FW_CFG__ | |
9 | ||
10 | #define FW_CONTROL_PORT 0x510 | |
11 | #define FW_DATA_PORT 0x511 | |
12 | #define FW_DMA_PORT_LOW 0x514 | |
13 | #define FW_DMA_PORT_HIGH 0x518 | |
14 | ||
25757220 MY |
15 | #include <linux/list.h> |
16 | ||
f60df20a MY |
17 | enum qemu_fwcfg_items { |
18 | FW_CFG_SIGNATURE = 0x00, | |
19 | FW_CFG_ID = 0x01, | |
20 | FW_CFG_UUID = 0x02, | |
21 | FW_CFG_RAM_SIZE = 0x03, | |
22 | FW_CFG_NOGRAPHIC = 0x04, | |
23 | FW_CFG_NB_CPUS = 0x05, | |
24 | FW_CFG_MACHINE_ID = 0x06, | |
25 | FW_CFG_KERNEL_ADDR = 0x07, | |
26 | FW_CFG_KERNEL_SIZE = 0x08, | |
27 | FW_CFG_KERNEL_CMDLINE = 0x09, | |
28 | FW_CFG_INITRD_ADDR = 0x0a, | |
29 | FW_CFG_INITRD_SIZE = 0x0b, | |
30 | FW_CFG_BOOT_DEVICE = 0x0c, | |
31 | FW_CFG_NUMA = 0x0d, | |
32 | FW_CFG_BOOT_MENU = 0x0e, | |
33 | FW_CFG_MAX_CPUS = 0x0f, | |
34 | FW_CFG_KERNEL_ENTRY = 0x10, | |
35 | FW_CFG_KERNEL_DATA = 0x11, | |
36 | FW_CFG_INITRD_DATA = 0x12, | |
37 | FW_CFG_CMDLINE_ADDR = 0x13, | |
38 | FW_CFG_CMDLINE_SIZE = 0x14, | |
39 | FW_CFG_CMDLINE_DATA = 0x15, | |
40 | FW_CFG_SETUP_ADDR = 0x16, | |
41 | FW_CFG_SETUP_SIZE = 0x17, | |
42 | FW_CFG_SETUP_DATA = 0x18, | |
43 | FW_CFG_FILE_DIR = 0x19, | |
44 | FW_CFG_FILE_FIRST = 0x20, | |
45 | FW_CFG_WRITE_CHANNEL = 0x4000, | |
46 | FW_CFG_ARCH_LOCAL = 0x8000, | |
47 | FW_CFG_INVALID = 0xffff, | |
48 | }; | |
49 | ||
50 | #define FW_CFG_FILE_SLOTS 0x10 | |
51 | #define FW_CFG_MAX_ENTRY (FW_CFG_FILE_FIRST + FW_CFG_FILE_SLOTS) | |
52 | #define FW_CFG_ENTRY_MASK ~(FW_CFG_WRITE_CHANNEL | FW_CFG_ARCH_LOCAL) | |
53 | ||
54 | #define FW_CFG_MAX_FILE_PATH 56 | |
55 | ||
56 | #define QEMU_FW_CFG_SIGNATURE (('Q' << 24) | ('E' << 16) | ('M' << 8) | 'U') | |
57 | ||
58 | #define FW_CFG_DMA_ERROR (1 << 0) | |
59 | #define FW_CFG_DMA_READ (1 << 1) | |
60 | #define FW_CFG_DMA_SKIP (1 << 2) | |
61 | #define FW_CFG_DMA_SELECT (1 << 3) | |
62 | ||
63 | #define FW_CFG_DMA_ENABLED (1 << 1) | |
64 | ||
65 | struct fw_cfg_file { | |
66 | __be32 size; | |
67 | __be16 select; | |
68 | __be16 reserved; | |
69 | char name[FW_CFG_MAX_FILE_PATH]; | |
70 | }; | |
71 | ||
25757220 MY |
72 | struct fw_file { |
73 | struct fw_cfg_file cfg; /* firmware file information */ | |
74 | unsigned long addr; /* firmware file in-memory address */ | |
75 | struct list_head list; /* list node to link to fw_list */ | |
f60df20a MY |
76 | }; |
77 | ||
78 | struct fw_cfg_dma_access { | |
79 | __be32 control; | |
80 | __be32 length; | |
81 | __be64 address; | |
82 | }; | |
83 | ||
84 | /** | |
85 | * Initialize QEMU fw_cfg interface | |
86 | */ | |
87 | void qemu_fwcfg_init(void); | |
88 | ||
89 | /** | |
90 | * Get system cpu number | |
91 | * | |
92 | * @return: cpu number in system | |
93 | */ | |
94 | int qemu_fwcfg_online_cpus(void); | |
95 | ||
96 | #endif |