[people/arne_f/kernel.git] / arch / x86 / include / asm / mce.h

#ifndef _ASM_X86_MCE_H
#define _ASM_X86_MCE_H

#include <uapi/asm/mce.h>

/*
 * Machine Check support for x86
 */

/* MCG_CAP register defines */
#define MCG_BANKCNT_MASK	0xff         /* Number of Banks */
#define MCG_CTL_P		(1ULL<<8)    /* MCG_CTL register available */
#define MCG_EXT_P		(1ULL<<9)    /* Extended registers available */
#define MCG_CMCI_P		(1ULL<<10)   /* CMCI supported */
#define MCG_EXT_CNT_MASK	0xff0000     /* Number of Extended registers */
#define MCG_EXT_CNT_SHIFT	16
#define MCG_EXT_CNT(c)		(((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
#define MCG_SER_P		(1ULL<<24)   /* MCA recovery/new status bits */
#define MCG_ELOG_P		(1ULL<<26)   /* Extended error log supported */
#define MCG_LMCE_P		(1ULL<<27)   /* Local machine check supported */

/* MCG_STATUS register defines */
#define MCG_STATUS_RIPV  (1ULL<<0)   /* restart ip valid */
#define MCG_STATUS_EIPV  (1ULL<<1)   /* ip points to correct instruction */
#define MCG_STATUS_MCIP  (1ULL<<2)   /* machine check in progress */
#define MCG_STATUS_LMCES (1ULL<<3)   /* LMCE signaled */

/* MCG_EXT_CTL register defines */
#define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Enable LMCE */

/* MCi_STATUS register defines */
#define MCI_STATUS_VAL   (1ULL<<63)  /* valid error */
#define MCI_STATUS_OVER  (1ULL<<62)  /* previous errors lost */
#define MCI_STATUS_UC    (1ULL<<61)  /* uncorrected error */
#define MCI_STATUS_EN    (1ULL<<60)  /* error enabled */
#define MCI_STATUS_MISCV (1ULL<<59)  /* misc error reg. valid */
#define MCI_STATUS_ADDRV (1ULL<<58)  /* addr reg. valid */
#define MCI_STATUS_PCC   (1ULL<<57)  /* processor context corrupt */
#define MCI_STATUS_S	 (1ULL<<56)  /* Signaled machine check */
#define MCI_STATUS_AR	 (1ULL<<55)  /* Action required */

/* AMD-specific bits */
#define MCI_STATUS_TCC		(1ULL<<55)  /* Task context corrupt */
#define MCI_STATUS_SYNDV	(1ULL<<53)  /* synd reg. valid */
#define MCI_STATUS_DEFERRED	(1ULL<<44)  /* uncorrected error, deferred exception */
#define MCI_STATUS_POISON	(1ULL<<43)  /* access poisonous data */

/*
 * McaX field if set indicates a given bank supports MCA extensions:
 *  - Deferred error interrupt type is specifiable by bank.
 *  - MCx_MISC0[BlkPtr] field indicates presence of extended MISC registers,
 *    But should not be used to determine MSR numbers.
 *  - TCC bit is present in MCx_STATUS.
 */
#define MCI_CONFIG_MCAX		0x1
#define MCI_IPID_MCATYPE	0xFFFF0000
#define MCI_IPID_HWID		0xFFF

/*
 * Note that the full MCACOD field of IA32_MCi_STATUS MSR is
 * bits 15:0.  But bit 12 is the 'F' bit, defined for corrected
 * errors to indicate that errors are being filtered by hardware.
 * We should mask out bit 12 when looking for specific signatures
 * of uncorrected errors - so the F bit is deliberately skipped
 * in this #define.
 */
#define MCACOD		  0xefff     /* MCA Error Code */

/* Architecturally defined codes from SDM Vol. 3B Chapter 15 */
#define MCACOD_SCRUB	0x00C0	/* 0xC0-0xCF Memory Scrubbing */
#define MCACOD_SCRUBMSK	0xeff0	/* Skip bit 12 ('F' bit) */
#define MCACOD_L3WB	0x017A	/* L3 Explicit Writeback */
#define MCACOD_DATA	0x0134	/* Data Load */
#define MCACOD_INSTR	0x0150	/* Instruction Fetch */

/* MCi_MISC register defines */
#define MCI_MISC_ADDR_LSB(m)	((m) & 0x3f)
#define MCI_MISC_ADDR_MODE(m)	(((m) >> 6) & 7)
#define  MCI_MISC_ADDR_SEGOFF	0	/* segment offset */
#define  MCI_MISC_ADDR_LINEAR	1	/* linear address */
#define  MCI_MISC_ADDR_PHYS	2	/* physical address */
#define  MCI_MISC_ADDR_MEM	3	/* memory address */
#define  MCI_MISC_ADDR_GENERIC	7	/* generic */

/* CTL2 register defines */
#define MCI_CTL2_CMCI_EN		(1ULL << 30)
#define MCI_CTL2_CMCI_THRESHOLD_MASK	0x7fffULL

#define MCJ_CTX_MASK		3
#define MCJ_CTX(flags)		((flags) & MCJ_CTX_MASK)
#define MCJ_CTX_RANDOM		0    /* inject context: random */
#define MCJ_CTX_PROCESS		0x1  /* inject context: process */
#define MCJ_CTX_IRQ		0x2  /* inject context: IRQ */
#define MCJ_NMI_BROADCAST	0x4  /* do NMI broadcasting */
#define MCJ_EXCEPTION		0x8  /* raise as exception */
#define MCJ_IRQ_BROADCAST	0x10 /* do IRQ broadcasting */

#define MCE_OVERFLOW 0		/* bit 0 in flags means overflow */

#define MCE_LOG_LEN 32
#define MCE_LOG_SIGNATURE	"MACHINECHECK"

/* AMD Scalable MCA */
#define MSR_AMD64_SMCA_MC0_CTL		0xc0002000
#define MSR_AMD64_SMCA_MC0_STATUS	0xc0002001
#define MSR_AMD64_SMCA_MC0_ADDR		0xc0002002
#define MSR_AMD64_SMCA_MC0_MISC0	0xc0002003
#define MSR_AMD64_SMCA_MC0_CONFIG	0xc0002004
#define MSR_AMD64_SMCA_MC0_IPID		0xc0002005
#define MSR_AMD64_SMCA_MC0_SYND		0xc0002006
#define MSR_AMD64_SMCA_MC0_DESTAT	0xc0002008
#define MSR_AMD64_SMCA_MC0_DEADDR	0xc0002009
#define MSR_AMD64_SMCA_MC0_MISC1	0xc000200a
#define MSR_AMD64_SMCA_MCx_CTL(x)	(MSR_AMD64_SMCA_MC0_CTL + 0x10*(x))
#define MSR_AMD64_SMCA_MCx_STATUS(x)	(MSR_AMD64_SMCA_MC0_STATUS + 0x10*(x))
#define MSR_AMD64_SMCA_MCx_ADDR(x)	(MSR_AMD64_SMCA_MC0_ADDR + 0x10*(x))
#define MSR_AMD64_SMCA_MCx_MISC(x)	(MSR_AMD64_SMCA_MC0_MISC0 + 0x10*(x))
#define MSR_AMD64_SMCA_MCx_CONFIG(x)	(MSR_AMD64_SMCA_MC0_CONFIG + 0x10*(x))
#define MSR_AMD64_SMCA_MCx_IPID(x)	(MSR_AMD64_SMCA_MC0_IPID + 0x10*(x))
#define MSR_AMD64_SMCA_MCx_SYND(x)	(MSR_AMD64_SMCA_MC0_SYND + 0x10*(x))
#define MSR_AMD64_SMCA_MCx_DESTAT(x)	(MSR_AMD64_SMCA_MC0_DESTAT + 0x10*(x))
#define MSR_AMD64_SMCA_MCx_DEADDR(x)	(MSR_AMD64_SMCA_MC0_DEADDR + 0x10*(x))
#define MSR_AMD64_SMCA_MCx_MISCy(x, y)	((MSR_AMD64_SMCA_MC0_MISC1 + y) + (0x10*(x)))

/*
 * This structure contains all data related to the MCE log.  Also
 * carries a signature to make it easier to find from external
 * debugging tools.  Each entry is only valid when its finished flag
 * is set.
 */
struct mce_log {
	char signature[12]; /* "MACHINECHECK" */
	unsigned len;	    /* = MCE_LOG_LEN */
	unsigned next;
	unsigned flags;
	unsigned recordlen;	/* length of struct mce */
	struct mce entry[MCE_LOG_LEN];
};

struct mca_config {
	bool dont_log_ce;
	bool cmci_disabled;
	bool lmce_disabled;
	bool ignore_ce;
	bool disabled;
	bool ser;
	bool recovery;
	bool bios_cmci_threshold;
	u8 banks;
	s8 bootlog;
	int tolerant;
	int monarch_timeout;
	int panic_timeout;
	u32 rip_msr;
};

struct mce_vendor_flags {
	/*
	 * Indicates that overflow conditions are not fatal, when set.
	 */
	__u64 overflow_recov	: 1,

	/*
	 * (AMD) SUCCOR stands for S/W UnCorrectable error COntainment and
	 * Recovery. It indicates support for data poisoning in HW and deferred
	 * error interrupts.
	 */
	      succor		: 1,

	/*
	 * (AMD) SMCA: This bit indicates support for Scalable MCA which expands
	 * the register space for each MCA bank and also increases number of
	 * banks. Also, to accommodate the new banks and registers, the MCA
	 * register space is moved to a new MSR range.
	 */
	      smca		: 1,

	      __reserved_0	: 61;
};

struct mca_msr_regs {
	u32 (*ctl)	(int bank);
	u32 (*status)	(int bank);
	u32 (*addr)	(int bank);
	u32 (*misc)	(int bank);
};

extern struct mce_vendor_flags mce_flags;

extern struct mca_config mca_cfg;
extern struct mca_msr_regs msr_ops;
extern void mce_register_decode_chain(struct notifier_block *nb);
extern void mce_unregister_decode_chain(struct notifier_block *nb);

#include <linux/percpu.h>
#include <linux/atomic.h>

extern int mce_p5_enabled;

#ifdef CONFIG_X86_MCE
int mcheck_init(void);
void mcheck_cpu_init(struct cpuinfo_x86 *c);
void mcheck_cpu_clear(struct cpuinfo_x86 *c);
void mcheck_vendor_init_severity(void);
#else
static inline int mcheck_init(void) { return 0; }
static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {}
static inline void mcheck_cpu_clear(struct cpuinfo_x86 *c) {}
static inline void mcheck_vendor_init_severity(void) {}
#endif

#ifdef CONFIG_X86_ANCIENT_MCE
void intel_p5_mcheck_init(struct cpuinfo_x86 *c);
void winchip_mcheck_init(struct cpuinfo_x86 *c);
static inline void enable_p5_mce(void) { mce_p5_enabled = 1; }
#else
static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {}
static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {}
static inline void enable_p5_mce(void) {}
#endif

void mce_setup(struct mce *m);
void mce_log(struct mce *m);
DECLARE_PER_CPU(struct device *, mce_device);

/*
 * Maximum banks number.
 * This is the limit of the current register layout on
 * Intel CPUs.
 */
#define MAX_NR_BANKS 32

#ifdef CONFIG_X86_MCE_INTEL
void mce_intel_feature_init(struct cpuinfo_x86 *c);
void mce_intel_feature_clear(struct cpuinfo_x86 *c);
void cmci_clear(void);
void cmci_reenable(void);
void cmci_rediscover(void);
void cmci_recheck(void);
#else
static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { }
static inline void mce_intel_feature_clear(struct cpuinfo_x86 *c) { }
static inline void cmci_clear(void) {}
static inline void cmci_reenable(void) {}
static inline void cmci_rediscover(void) {}
static inline void cmci_recheck(void) {}
#endif

#ifdef CONFIG_X86_MCE_AMD
void mce_amd_feature_init(struct cpuinfo_x86 *c);
int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr);
#else
static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { }
static inline int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) { return -EINVAL; };
#endif

int mce_available(struct cpuinfo_x86 *c);

DECLARE_PER_CPU(unsigned, mce_exception_count);
DECLARE_PER_CPU(unsigned, mce_poll_count);

typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS);
DECLARE_PER_CPU(mce_banks_t, mce_poll_banks);

enum mcp_flags {
	MCP_TIMESTAMP	= BIT(0),	/* log time stamp */
	MCP_UC		= BIT(1),	/* log uncorrected errors */
	MCP_DONTLOG	= BIT(2),	/* only clear, don't log */
};
bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b);

int mce_notify_irq(void);

DECLARE_PER_CPU(struct mce, injectm);

extern void register_mce_write_callback(ssize_t (*)(struct file *filp,
				    const char __user *ubuf,
				    size_t usize, loff_t *off));

/* Disable CMCI/polling for MCA bank claimed by firmware */
extern void mce_disable_bank(int bank);

/*
 * Exception handler
 */

/* Call the installed machine check handler for this CPU setup. */
extern void (*machine_check_vector)(struct pt_regs *, long error_code);
void do_machine_check(struct pt_regs *, long);

/*
 * Threshold handler
 */
extern void (*mce_threshold_vector)(void);

/* Deferred error interrupt handler */
extern void (*deferred_error_int_vector)(void);

/*
 * Thermal handler
 */

void intel_init_thermal(struct cpuinfo_x86 *c);

/* Interrupt Handler for core thermal thresholds */
extern int (*platform_thermal_notify)(__u64 msr_val);

/* Interrupt Handler for package thermal thresholds */
extern int (*platform_thermal_package_notify)(__u64 msr_val);

/* Callback support of rate control, return true, if
 * callback has rate control */
extern bool (*platform_thermal_package_rate_control)(void);

#ifdef CONFIG_X86_THERMAL_VECTOR
extern void mcheck_intel_therm_init(void);
#else
static inline void mcheck_intel_therm_init(void) { }
#endif

/*
 * Used by APEI to report memory error via /dev/mcelog
 */

struct cper_sec_mem_err;
extern void apei_mce_report_mem_error(int corrected,
				      struct cper_sec_mem_err *mem_err);

/*
 * Enumerate new IP types and HWID values in AMD processors which support
 * Scalable MCA.
 */
#ifdef CONFIG_X86_MCE_AMD

/* These may be used by multiple smca_hwid_mcatypes */
enum smca_bank_types {
	SMCA_LS = 0,	/* Load Store */
	SMCA_IF,	/* Instruction Fetch */
	SMCA_L2_CACHE,	/* L2 Cache */
	SMCA_DE,	/* Decoder Unit */
	SMCA_EX,	/* Execution Unit */
	SMCA_FP,	/* Floating Point */
	SMCA_L3_CACHE,	/* L3 Cache */
	SMCA_CS,	/* Coherent Slave */
	SMCA_PIE,	/* Power, Interrupts, etc. */
	SMCA_UMC,	/* Unified Memory Controller */
	SMCA_PB,	/* Parameter Block */
	SMCA_PSP,	/* Platform Security Processor */
	SMCA_SMU,	/* System Management Unit */
	N_SMCA_BANK_TYPES
};

#define HWID_MCATYPE(hwid, mcatype) (((hwid) << 16) | (mcatype))

struct smca_hwid {
	unsigned int bank_type;	/* Use with smca_bank_types for easy indexing. */
	u32 hwid_mcatype;	/* (hwid,mcatype) tuple */
	u32 xec_bitmap;		/* Bitmap of valid ExtErrorCodes; current max is 21. */
};

struct smca_bank {
	struct smca_hwid *hwid;
	/* Instance ID */
	u32 id;
};

extern struct smca_bank smca_banks[MAX_NR_BANKS];

extern const char *smca_get_long_name(enum smca_bank_types t);

extern int mce_threshold_create_device(unsigned int cpu);
extern int mce_threshold_remove_device(unsigned int cpu);

#else

static inline int mce_threshold_create_device(unsigned int cpu) { return 0; };
static inline int mce_threshold_remove_device(unsigned int cpu) { return 0; };

#endif

#endif /* _ASM_X86_MCE_H */
Commit	Line	Data
1965aae3 PA	1	#ifndef _ASM_X86_MCE_H
1965aae3 PA	2	#define _ASM_X86_MCE_H
e2f43029	3
af170c50	4	#include <uapi/asm/mce.h>
e2f43029	5
f51bde6f BP	6	/*
	7	* Machine Check support for x86
	8	*/
	9
	10	/* MCG_CAP register defines */
	11	#define MCG_BANKCNT_MASK 0xff /* Number of Banks */
	12	#define MCG_CTL_P (1ULL<<8) /* MCG_CTL register available */
	13	#define MCG_EXT_P (1ULL<<9) /* Extended registers available */
	14	#define MCG_CMCI_P (1ULL<<10) /* CMCI supported */
	15	#define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */
	16	#define MCG_EXT_CNT_SHIFT 16
	17	#define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
	18	#define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */
4b3db708	19	#define MCG_ELOG_P (1ULL<<26) /* Extended error log supported */
bc12edb8	20	#define MCG_LMCE_P (1ULL<<27) /* Local machine check supported */
f51bde6f BP	21
	22	/* MCG_STATUS register defines */
	23	#define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */
	24	#define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */
	25	#define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */
bc12edb8 AR	26	#define MCG_STATUS_LMCES (1ULL<<3) /* LMCE signaled */
	27
	28	/* MCG_EXT_CTL register defines */
	29	#define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Enable LMCE */
f51bde6f BP	30
	31	/* MCi_STATUS register defines */
	32	#define MCI_STATUS_VAL (1ULL<<63) /* valid error */
	33	#define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */
	34	#define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */
	35	#define MCI_STATUS_EN (1ULL<<60) /* error enabled */
	36	#define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */
	37	#define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */
	38	#define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */
	39	#define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */
	40	#define MCI_STATUS_AR (1ULL<<55) /* Action required */
0ca06c08	41
e3480271	42	/* AMD-specific bits */
db819d60 YG	43	#define MCI_STATUS_TCC (1ULL<<55) /* Task context corrupt */
db819d60 YG	44	#define MCI_STATUS_SYNDV (1ULL<<53) /* synd reg. valid */
2cd3b5f9	45	#define MCI_STATUS_DEFERRED (1ULL<<44) /* uncorrected error, deferred exception */
e3480271	46	#define MCI_STATUS_POISON (1ULL<<43) /* access poisonous data */
be0aec23 AG	47
	48	/*
	49	* McaX field if set indicates a given bank supports MCA extensions:
	50	* - Deferred error interrupt type is specifiable by bank.
	51	* - MCx_MISC0[BlkPtr] field indicates presence of extended MISC registers,
	52	* But should not be used to determine MSR numbers.
	53	* - TCC bit is present in MCx_STATUS.
	54	*/
	55	#define MCI_CONFIG_MCAX 0x1
	56	#define MCI_IPID_MCATYPE 0xFFFF0000
	57	#define MCI_IPID_HWID 0xFFF
e3480271	58
0ca06c08 TL	59	/*
	60	* Note that the full MCACOD field of IA32_MCi_STATUS MSR is
	61	* bits 15:0. But bit 12 is the 'F' bit, defined for corrected
	62	* errors to indicate that errors are being filtered by hardware.
	63	* We should mask out bit 12 when looking for specific signatures
	64	* of uncorrected errors - so the F bit is deliberately skipped
	65	* in this #define.
	66	*/
	67	#define MCACOD 0xefff /* MCA Error Code */
f51bde6f BP	68
	69	/* Architecturally defined codes from SDM Vol. 3B Chapter 15 */
	70	#define MCACOD_SCRUB 0x00C0 /* 0xC0-0xCF Memory Scrubbing */
0ca06c08	71	#define MCACOD_SCRUBMSK 0xeff0 /* Skip bit 12 ('F' bit) */
f51bde6f BP	72	#define MCACOD_L3WB 0x017A /* L3 Explicit Writeback */
	73	#define MCACOD_DATA 0x0134 /* Data Load */
	74	#define MCACOD_INSTR 0x0150 /* Instruction Fetch */
	75
	76	/* MCi_MISC register defines */
	77	#define MCI_MISC_ADDR_LSB(m) ((m) & 0x3f)
	78	#define MCI_MISC_ADDR_MODE(m) (((m) >> 6) & 7)
	79	#define MCI_MISC_ADDR_SEGOFF 0 /* segment offset */
	80	#define MCI_MISC_ADDR_LINEAR 1 /* linear address */
	81	#define MCI_MISC_ADDR_PHYS 2 /* physical address */
	82	#define MCI_MISC_ADDR_MEM 3 /* memory address */
	83	#define MCI_MISC_ADDR_GENERIC 7 /* generic */
	84
	85	/* CTL2 register defines */
	86	#define MCI_CTL2_CMCI_EN (1ULL << 30)
	87	#define MCI_CTL2_CMCI_THRESHOLD_MASK 0x7fffULL
	88
	89	#define MCJ_CTX_MASK 3
	90	#define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK)
	91	#define MCJ_CTX_RANDOM 0 /* inject context: random */
	92	#define MCJ_CTX_PROCESS 0x1 /* inject context: process */
	93	#define MCJ_CTX_IRQ 0x2 /* inject context: IRQ */
	94	#define MCJ_NMI_BROADCAST 0x4 /* do NMI broadcasting */
	95	#define MCJ_EXCEPTION 0x8 /* raise as exception */
a9093684	96	#define MCJ_IRQ_BROADCAST 0x10 /* do IRQ broadcasting */
f51bde6f BP	97
	98	#define MCE_OVERFLOW 0 /* bit 0 in flags means overflow */
	99
f51bde6f BP	100	#define MCE_LOG_LEN 32
	101	#define MCE_LOG_SIGNATURE "MACHINECHECK"
	102
adc53f2e	103	/* AMD Scalable MCA */
a9750a31 YG	104	#define MSR_AMD64_SMCA_MC0_CTL 0xc0002000
	105	#define MSR_AMD64_SMCA_MC0_STATUS 0xc0002001
	106	#define MSR_AMD64_SMCA_MC0_ADDR 0xc0002002
8dd1e17a	107	#define MSR_AMD64_SMCA_MC0_MISC0 0xc0002003
adc53f2e	108	#define MSR_AMD64_SMCA_MC0_CONFIG 0xc0002004
be0aec23	109	#define MSR_AMD64_SMCA_MC0_IPID 0xc0002005
db819d60	110	#define MSR_AMD64_SMCA_MC0_SYND 0xc0002006
34102009 YG	111	#define MSR_AMD64_SMCA_MC0_DESTAT 0xc0002008
34102009 YG	112	#define MSR_AMD64_SMCA_MC0_DEADDR 0xc0002009
8dd1e17a	113	#define MSR_AMD64_SMCA_MC0_MISC1 0xc000200a
a9750a31 YG	114	#define MSR_AMD64_SMCA_MCx_CTL(x) (MSR_AMD64_SMCA_MC0_CTL + 0x10*(x))
	115	#define MSR_AMD64_SMCA_MCx_STATUS(x) (MSR_AMD64_SMCA_MC0_STATUS + 0x10*(x))
	116	#define MSR_AMD64_SMCA_MCx_ADDR(x) (MSR_AMD64_SMCA_MC0_ADDR + 0x10*(x))
8dd1e17a	117	#define MSR_AMD64_SMCA_MCx_MISC(x) (MSR_AMD64_SMCA_MC0_MISC0 + 0x10*(x))
adc53f2e	118	#define MSR_AMD64_SMCA_MCx_CONFIG(x) (MSR_AMD64_SMCA_MC0_CONFIG + 0x10*(x))
be0aec23	119	#define MSR_AMD64_SMCA_MCx_IPID(x) (MSR_AMD64_SMCA_MC0_IPID + 0x10*(x))
db819d60	120	#define MSR_AMD64_SMCA_MCx_SYND(x) (MSR_AMD64_SMCA_MC0_SYND + 0x10*(x))
34102009 YG	121	#define MSR_AMD64_SMCA_MCx_DESTAT(x) (MSR_AMD64_SMCA_MC0_DESTAT + 0x10*(x))
34102009 YG	122	#define MSR_AMD64_SMCA_MCx_DEADDR(x) (MSR_AMD64_SMCA_MC0_DEADDR + 0x10*(x))
8dd1e17a	123	#define MSR_AMD64_SMCA_MCx_MISCy(x, y) ((MSR_AMD64_SMCA_MC0_MISC1 + y) + (0x10*(x)))
adc53f2e	124
f51bde6f BP	125	/*
	126	* This structure contains all data related to the MCE log. Also
	127	* carries a signature to make it easier to find from external
	128	* debugging tools. Each entry is only valid when its finished flag
	129	* is set.
	130	*/
	131	struct mce_log {
	132	char signature[12]; /* "MACHINECHECK" */
	133	unsigned len; /* = MCE_LOG_LEN */
	134	unsigned next;
	135	unsigned flags;
	136	unsigned recordlen; /* length of struct mce */
	137	struct mce entry[MCE_LOG_LEN];
	138	};
d203f0b8 BP	139
	140	struct mca_config {
	141	bool dont_log_ce;
7af19e4a	142	bool cmci_disabled;
88d53867	143	bool lmce_disabled;
7af19e4a	144	bool ignore_ce;
1462594b BP	145	bool disabled;
1462594b BP	146	bool ser;
0f68c088	147	bool recovery;
1462594b	148	bool bios_cmci_threshold;
d203f0b8	149	u8 banks;
84c2559d	150	s8 bootlog;
d203f0b8	151	int tolerant;
84c2559d	152	int monarch_timeout;
7af19e4a	153	int panic_timeout;
84c2559d	154	u32 rip_msr;
d203f0b8 BP	155	};
d203f0b8 BP	156
bf80bbd7	157	struct mce_vendor_flags {
c7f54d21 AG	158	/*
	159	* Indicates that overflow conditions are not fatal, when set.
	160	*/
	161	__u64 overflow_recov : 1,
	162
	163	/*
	164	* (AMD) SUCCOR stands for S/W UnCorrectable error COntainment and
	165	* Recovery. It indicates support for data poisoning in HW and deferred
	166	* error interrupts.
	167	*/
	168	succor : 1,
	169
	170	/*
	171	* (AMD) SMCA: This bit indicates support for Scalable MCA which expands
	172	* the register space for each MCA bank and also increases number of
	173	* banks. Also, to accommodate the new banks and registers, the MCA
	174	* register space is moved to a new MSR range.
	175	*/
	176	smca : 1,
	177
	178	__reserved_0 : 61;
bf80bbd7	179	};
a9750a31 YG	180
	181	struct mca_msr_regs {
	182	u32 (*ctl) (int bank);
	183	u32 (*status) (int bank);
	184	u32 (*addr) (int bank);
	185	u32 (*misc) (int bank);
	186	};
	187
bf80bbd7 AG	188	extern struct mce_vendor_flags mce_flags;
bf80bbd7 AG	189
7af19e4a	190	extern struct mca_config mca_cfg;
a9750a31	191	extern struct mca_msr_regs msr_ops;
eef4dfa0	192	extern void mce_register_decode_chain(struct notifier_block *nb);
3653ada5	193	extern void mce_unregister_decode_chain(struct notifier_block *nb);
df39a2e4	194
9e55e44e	195	#include <linux/percpu.h>
60063497	196	#include <linux/atomic.h>
9e55e44e	197
c6978369	198	extern int mce_p5_enabled;
e2f43029	199
58995d2d	200	#ifdef CONFIG_X86_MCE
a2202aa2	201	int mcheck_init(void);
5e09954a	202	void mcheck_cpu_init(struct cpuinfo_x86 *c);
8838eb6c	203	void mcheck_cpu_clear(struct cpuinfo_x86 *c);
43eaa2a1	204	void mcheck_vendor_init_severity(void);
58995d2d	205	#else
a2202aa2	206	static inline int mcheck_init(void) { return 0; }
5e09954a	207	static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {}
8838eb6c	208	static inline void mcheck_cpu_clear(struct cpuinfo_x86 *c) {}
43eaa2a1	209	static inline void mcheck_vendor_init_severity(void) {}
58995d2d HS	210	#endif
58995d2d HS	211
9e55e44e HS	212	#ifdef CONFIG_X86_ANCIENT_MCE
	213	void intel_p5_mcheck_init(struct cpuinfo_x86 *c);
	214	void winchip_mcheck_init(struct cpuinfo_x86 *c);
c6978369	215	static inline void enable_p5_mce(void) { mce_p5_enabled = 1; }
9e55e44e HS	216	#else
	217	static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {}
	218	static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {}
c6978369	219	static inline void enable_p5_mce(void) {}
9e55e44e HS	220	#endif
9e55e44e HS	221
b5f2fa4e	222	void mce_setup(struct mce *m);
e2f43029	223	void mce_log(struct mce *m);
d6126ef5	224	DECLARE_PER_CPU(struct device *, mce_device);
e2f43029	225
41fdff32	226	/*
3ccdccfa AK	227	* Maximum banks number.
	228	* This is the limit of the current register layout on
	229	* Intel CPUs.
41fdff32	230	*/
3ccdccfa	231	#define MAX_NR_BANKS 32
41fdff32	232
e2f43029 TG	233	#ifdef CONFIG_X86_MCE_INTEL
e2f43029 TG	234	void mce_intel_feature_init(struct cpuinfo_x86 *c);
8838eb6c	235	void mce_intel_feature_clear(struct cpuinfo_x86 *c);
88ccbedd AK	236	void cmci_clear(void);
88ccbedd AK	237	void cmci_reenable(void);
7a0c819d	238	void cmci_rediscover(void);
88ccbedd	239	void cmci_recheck(void);
e2f43029 TG	240	#else
e2f43029 TG	241	static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { }
8838eb6c	242	static inline void mce_intel_feature_clear(struct cpuinfo_x86 *c) { }
88ccbedd AK	243	static inline void cmci_clear(void) {}
88ccbedd AK	244	static inline void cmci_reenable(void) {}
7a0c819d	245	static inline void cmci_rediscover(void) {}
88ccbedd	246	static inline void cmci_recheck(void) {}
e2f43029 TG	247	#endif
	248
	249	#ifdef CONFIG_X86_MCE_AMD
	250	void mce_amd_feature_init(struct cpuinfo_x86 *c);
f5382de9	251	int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr);
e2f43029 TG	252	#else
e2f43029 TG	253	static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { }
f5382de9	254	static inline int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) { return -EINVAL; };
e2f43029 TG	255	#endif
e2f43029 TG	256
38736072	257	int mce_available(struct cpuinfo_x86 *c);
88ccbedd	258
01ca79f1	259	DECLARE_PER_CPU(unsigned, mce_exception_count);
ca84f696	260	DECLARE_PER_CPU(unsigned, mce_poll_count);
01ca79f1	261
ee031c31 AK	262	typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS);
	263	DECLARE_PER_CPU(mce_banks_t, mce_poll_banks);
	264
b79109c3	265	enum mcp_flags {
3f2f0680 BP	266	MCP_TIMESTAMP = BIT(0), /* log time stamp */
	267	MCP_UC = BIT(1), /* log uncorrected errors */
	268	MCP_DONTLOG = BIT(2), /* only clear, don't log */
b79109c3	269	};
3f2f0680	270	bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b);
b79109c3	271
9ff36ee9	272	int mce_notify_irq(void);
e2f43029	273
ea149b36	274	DECLARE_PER_CPU(struct mce, injectm);
66f5ddf3 LT	275
	276	extern void register_mce_write_callback(ssize_t ()(struct file filp,
	277	const char __user *ubuf,
	278	size_t usize, loff_t *off));
ea149b36	279
c3d1fb56 NR	280	/* Disable CMCI/polling for MCA bank claimed by firmware */
	281	extern void mce_disable_bank(int bank);
	282
58995d2d HS	283	/*
	284	* Exception handler
	285	*/
	286
	287	/* Call the installed machine check handler for this CPU setup. */
	288	extern void (machine_check_vector)(struct pt_regs , long error_code);
	289	void do_machine_check(struct pt_regs *, long);
	290
	291	/*
	292	* Threshold handler
	293	*/
b2762686 AK	294	extern void (*mce_threshold_vector)(void);
b2762686 AK	295
24fd78a8 AG	296	/* Deferred error interrupt handler */
	297	extern void (*deferred_error_int_vector)(void);
	298
e8ce2c5e HS	299	/*
	300	* Thermal handler
	301	*/
	302
e8ce2c5e HS	303	void intel_init_thermal(struct cpuinfo_x86 *c);
e8ce2c5e HS	304
9e76a97e D	305	/* Interrupt Handler for core thermal thresholds */
	306	extern int (*platform_thermal_notify)(__u64 msr_val);
	307
25cdce17 SP	308	/* Interrupt Handler for package thermal thresholds */
	309	extern int (*platform_thermal_package_notify)(__u64 msr_val);
	310
	311	/* Callback support of rate control, return true, if
	312	* callback has rate control */
	313	extern bool (*platform_thermal_package_rate_control)(void);
	314
a2202aa2 YW	315	#ifdef CONFIG_X86_THERMAL_VECTOR
	316	extern void mcheck_intel_therm_init(void);
	317	#else
	318	static inline void mcheck_intel_therm_init(void) { }
	319	#endif
	320
d334a491 HY	321	/*
	322	* Used by APEI to report memory error via /dev/mcelog
	323	*/
	324
	325	struct cper_sec_mem_err;
	326	extern void apei_mce_report_mem_error(int corrected,
	327	struct cper_sec_mem_err *mem_err);
	328
be0aec23 AG	329	/*
	330	* Enumerate new IP types and HWID values in AMD processors which support
	331	* Scalable MCA.
	332	*/
	333	#ifdef CONFIG_X86_MCE_AMD
be0aec23	334
5896820e YG	335	/* These may be used by multiple smca_hwid_mcatypes */
5896820e YG	336	enum smca_bank_types {
be0aec23 AG	337	SMCA_LS = 0, /* Load Store */
be0aec23 AG	338	SMCA_IF, /* Instruction Fetch */
5896820e YG	339	SMCA_L2_CACHE, /* L2 Cache */
	340	SMCA_DE, /* Decoder Unit */
	341	SMCA_EX, /* Execution Unit */
be0aec23	342	SMCA_FP, /* Floating Point */
5896820e YG	343	SMCA_L3_CACHE, /* L3 Cache */
	344	SMCA_CS, /* Coherent Slave */
	345	SMCA_PIE, /* Power, Interrupts, etc. */
	346	SMCA_UMC, /* Unified Memory Controller */
	347	SMCA_PB, /* Parameter Block */
	348	SMCA_PSP, /* Platform Security Processor */
	349	SMCA_SMU, /* System Management Unit */
	350	N_SMCA_BANK_TYPES
	351	};
	352
859af13a	353	#define HWID_MCATYPE(hwid, mcatype) (((hwid) << 16) \| (mcatype))
be0aec23	354
1ce9cd7f	355	struct smca_hwid {
5896820e YG	356	unsigned int bank_type; /* Use with smca_bank_types for easy indexing. */
	357	u32 hwid_mcatype; /* (hwid,mcatype) tuple */
	358	u32 xec_bitmap; /* Bitmap of valid ExtErrorCodes; current max is 21. */
be0aec23 AG	359	};
be0aec23 AG	360
79349f52	361	struct smca_bank {
1ce9cd7f	362	struct smca_hwid *hwid;
79349f52 BP	363	/* Instance ID */
79349f52 BP	364	u32 id;
5896820e YG	365	};
5896820e YG	366
79349f52	367	extern struct smca_bank smca_banks[MAX_NR_BANKS];
5896820e	368
c09a8c40	369	extern const char *smca_get_long_name(enum smca_bank_types t);
e71c3978	370
4d7b02d5 SAS	371	extern int mce_threshold_create_device(unsigned int cpu);
4d7b02d5 SAS	372	extern int mce_threshold_remove_device(unsigned int cpu);
e71c3978	373
4d7b02d5	374	#else
5896820e	375
4d7b02d5 SAS	376	static inline int mce_threshold_create_device(unsigned int cpu) { return 0; };
4d7b02d5 SAS	377	static inline int mce_threshold_remove_device(unsigned int cpu) { return 0; };
e71c3978	378
be0aec23 AG	379	#endif
be0aec23 AG	380
1965aae3	381	#endif /* _ASM_X86_MCE_H */