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[thirdparty/kernel/linux.git] / arch / x86 / include / asm / mpspec.h
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b2441318 1/* SPDX-License-Identifier: GPL-2.0 */
1965aae3
PA
2#ifndef _ASM_X86_MPSPEC_H
3#define _ASM_X86_MPSPEC_H
c2805aa1 4
86c9835b 5
c2805aa1 6#include <asm/mpspec_def.h>
b3f1b617 7#include <asm/x86_init.h>
cb2ded37 8#include <asm/apicdef.h>
c2805aa1 9
a1ae299d 10extern int pic_mode;
11494547 11
96a388de 12#ifdef CONFIG_X86_32
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13
14/*
15 * Summit or generic (i.e. installer) kernels need lots of bus entries.
16 * Maximum 256 PCI busses, plus 1 ISA bus in each of 4 cabinets.
17 */
18#if CONFIG_BASE_SMALL == 0
19# define MAX_MP_BUSSES 260
20#else
21# define MAX_MP_BUSSES 32
22#endif
23
24#define MAX_IRQ_SOURCES 256
c2805aa1 25
c2805aa1 26extern unsigned int def_to_bigsmp;
c2805aa1 27
b2af018f 28#else /* CONFIG_X86_64: */
c2805aa1 29
b2af018f 30#define MAX_MP_BUSSES 256
c2805aa1 31/* Each PCI slot may be a combo card with its own bus. 4 IRQ pins per slot. */
b2af018f 32#define MAX_IRQ_SOURCES (MAX_MP_BUSSES * 4)
c2805aa1 33
b2af018f 34#endif /* CONFIG_X86_64 */
ab530e1f 35
bb8187d3 36#ifdef CONFIG_EISA
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37extern int mp_bus_id_to_type[MAX_MP_BUSSES];
38#endif
39
a6333c3c 40extern DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
c0a282c2 41
c2805aa1 42extern unsigned int boot_cpu_physical_apicid;
cff9ab2b 43extern u8 boot_cpu_apic_version;
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44extern unsigned long mp_lapic_addr;
45
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46#ifdef CONFIG_X86_LOCAL_APIC
47extern int smp_found_config;
48#else
49# define smp_found_config 0
50#endif
51
52static inline void get_smp_config(void)
53{
54 x86_init.mpparse.get_smp_config(0);
55}
56
57static inline void early_get_smp_config(void)
58{
59 x86_init.mpparse.get_smp_config(1);
60}
61
62static inline void find_smp_config(void)
63{
b24c2a92 64 x86_init.mpparse.find_smp_config();
b3f1b617 65}
550fe4f1 66
af1cf204 67#ifdef CONFIG_X86_MPPARSE
5da217ca 68extern void e820__memblock_alloc_reserved_mpc_new(void);
abfe0af9 69extern int enable_update_mptable;
fd6c6661 70extern int default_mpc_apic_id(struct mpc_cpu *m);
72302142 71extern void default_smp_read_mpc_oem(struct mpc_table *mpc);
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72# ifdef CONFIG_X86_IO_APIC
73extern void default_mpc_oem_bus_info(struct mpc_bus *m, char *str);
74# else
75# define default_mpc_oem_bus_info NULL
76# endif
b24c2a92 77extern void default_find_smp_config(void);
b3f1b617 78extern void default_get_smp_config(unsigned int early);
af1cf204 79#else
5da217ca 80static inline void e820__memblock_alloc_reserved_mpc_new(void) { }
abfe0af9 81#define enable_update_mptable 0
fd6c6661 82#define default_mpc_apic_id NULL
72302142 83#define default_smp_read_mpc_oem NULL
90e1c696 84#define default_mpc_oem_bus_info NULL
b24c2a92 85#define default_find_smp_config x86_init_noop
b3f1b617 86#define default_get_smp_config x86_init_uint_noop
af1cf204 87#endif
c2805aa1 88
7e1f85f9 89int generic_processor_info(int apicid, int version);
c2805aa1 90
cb2ded37 91#define PHYSID_ARRAY_SIZE BITS_TO_LONGS(MAX_LOCAL_APIC)
c2805aa1 92
30971e17 93struct physid_mask {
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94 unsigned long mask[PHYSID_ARRAY_SIZE];
95};
96
97typedef struct physid_mask physid_mask_t;
98
99#define physid_set(physid, map) set_bit(physid, (map).mask)
100#define physid_clear(physid, map) clear_bit(physid, (map).mask)
101#define physid_isset(physid, map) test_bit(physid, (map).mask)
30971e17 102#define physid_test_and_set(physid, map) \
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103 test_and_set_bit(physid, (map).mask)
104
30971e17 105#define physids_and(dst, src1, src2) \
cb2ded37 106 bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_LOCAL_APIC)
c2805aa1 107
30971e17 108#define physids_or(dst, src1, src2) \
cb2ded37 109 bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_LOCAL_APIC)
c2805aa1 110
30971e17 111#define physids_clear(map) \
cb2ded37 112 bitmap_zero((map).mask, MAX_LOCAL_APIC)
c2805aa1 113
30971e17 114#define physids_complement(dst, src) \
cb2ded37 115 bitmap_complement((dst).mask, (src).mask, MAX_LOCAL_APIC)
c2805aa1 116
30971e17 117#define physids_empty(map) \
cb2ded37 118 bitmap_empty((map).mask, MAX_LOCAL_APIC)
c2805aa1 119
30971e17 120#define physids_equal(map1, map2) \
cb2ded37 121 bitmap_equal((map1).mask, (map2).mask, MAX_LOCAL_APIC)
c2805aa1 122
30971e17 123#define physids_weight(map) \
cb2ded37 124 bitmap_weight((map).mask, MAX_LOCAL_APIC)
c2805aa1 125
30971e17 126#define physids_shift_right(d, s, n) \
cb2ded37 127 bitmap_shift_right((d).mask, (s).mask, n, MAX_LOCAL_APIC)
c2805aa1 128
30971e17 129#define physids_shift_left(d, s, n) \
cb2ded37 130 bitmap_shift_left((d).mask, (s).mask, n, MAX_LOCAL_APIC)
c2805aa1 131
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132static inline unsigned long physids_coerce(physid_mask_t *map)
133{
134 return map->mask[0];
135}
c2805aa1 136
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137static inline void physids_promote(unsigned long physids, physid_mask_t *map)
138{
139 physids_clear(*map);
140 map->mask[0] = physids;
141}
c2805aa1 142
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143static inline void physid_set_mask_of_physid(int physid, physid_mask_t *map)
144{
145 physids_clear(*map);
146 physid_set(physid, *map);
147}
148
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149#define PHYSID_MASK_ALL { {[0 ... PHYSID_ARRAY_SIZE-1] = ~0UL} }
150#define PHYSID_MASK_NONE { {[0 ... PHYSID_ARRAY_SIZE-1] = 0UL} }
151
152extern physid_mask_t phys_cpu_present_map;
153
1965aae3 154#endif /* _ASM_X86_MPSPEC_H */