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Commit | Line | Data |
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f0fc4aff | 1 | #include <linux/bootmem.h> |
9766cdbc | 2 | #include <linux/linkage.h> |
f0fc4aff | 3 | #include <linux/bitops.h> |
9766cdbc | 4 | #include <linux/kernel.h> |
186f4360 | 5 | #include <linux/export.h> |
9766cdbc JSR |
6 | #include <linux/percpu.h> |
7 | #include <linux/string.h> | |
ee098e1a | 8 | #include <linux/ctype.h> |
1da177e4 | 9 | #include <linux/delay.h> |
68e21be2 | 10 | #include <linux/sched/mm.h> |
e6017571 | 11 | #include <linux/sched/clock.h> |
9164bb4a | 12 | #include <linux/sched/task.h> |
9766cdbc | 13 | #include <linux/init.h> |
0f46efeb | 14 | #include <linux/kprobes.h> |
9766cdbc | 15 | #include <linux/kgdb.h> |
1da177e4 | 16 | #include <linux/smp.h> |
9766cdbc | 17 | #include <linux/io.h> |
b51ef52d | 18 | #include <linux/syscore_ops.h> |
9766cdbc JSR |
19 | |
20 | #include <asm/stackprotector.h> | |
cdd6c482 | 21 | #include <asm/perf_event.h> |
1da177e4 | 22 | #include <asm/mmu_context.h> |
49d859d7 | 23 | #include <asm/archrandom.h> |
9766cdbc JSR |
24 | #include <asm/hypervisor.h> |
25 | #include <asm/processor.h> | |
1e02ce4c | 26 | #include <asm/tlbflush.h> |
f649e938 | 27 | #include <asm/debugreg.h> |
9766cdbc | 28 | #include <asm/sections.h> |
f40c3300 | 29 | #include <asm/vsyscall.h> |
8bdbd962 AC |
30 | #include <linux/topology.h> |
31 | #include <linux/cpumask.h> | |
9766cdbc | 32 | #include <asm/pgtable.h> |
60063497 | 33 | #include <linux/atomic.h> |
9766cdbc JSR |
34 | #include <asm/proto.h> |
35 | #include <asm/setup.h> | |
36 | #include <asm/apic.h> | |
37 | #include <asm/desc.h> | |
78f7f1e5 | 38 | #include <asm/fpu/internal.h> |
27b07da7 | 39 | #include <asm/mtrr.h> |
0274f955 | 40 | #include <asm/hwcap2.h> |
8bdbd962 | 41 | #include <linux/numa.h> |
9766cdbc | 42 | #include <asm/asm.h> |
0f6ff2bc | 43 | #include <asm/bugs.h> |
9766cdbc | 44 | #include <asm/cpu.h> |
a03a3e28 | 45 | #include <asm/mce.h> |
9766cdbc | 46 | #include <asm/msr.h> |
8d4a4300 | 47 | #include <asm/pat.h> |
d288e1cf FY |
48 | #include <asm/microcode.h> |
49 | #include <asm/microcode_intel.h> | |
d9b47a41 DW |
50 | #include <asm/intel-family.h> |
51 | #include <asm/cpu_device_id.h> | |
e641f5f5 IM |
52 | |
53 | #ifdef CONFIG_X86_LOCAL_APIC | |
bdbcdd48 | 54 | #include <asm/uv/uv.h> |
1da177e4 LT |
55 | #endif |
56 | ||
57 | #include "cpu.h" | |
58 | ||
0274f955 GA |
59 | u32 elf_hwcap2 __read_mostly; |
60 | ||
c2d1cec1 | 61 | /* all of these masks are initialized in setup_cpu_local_masks() */ |
c2d1cec1 | 62 | cpumask_var_t cpu_initialized_mask; |
9766cdbc JSR |
63 | cpumask_var_t cpu_callout_mask; |
64 | cpumask_var_t cpu_callin_mask; | |
c2d1cec1 MT |
65 | |
66 | /* representing cpus for which sibling maps can be computed */ | |
67 | cpumask_var_t cpu_sibling_setup_mask; | |
68 | ||
dc589e57 BP |
69 | /* Number of siblings per CPU package */ |
70 | int smp_num_siblings = 1; | |
71 | EXPORT_SYMBOL(smp_num_siblings); | |
72 | ||
73 | /* Last level cache ID of each logical CPU */ | |
74 | DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; | |
75 | ||
2f2f52ba | 76 | /* correctly size the local cpu masks */ |
4369f1fb | 77 | void __init setup_cpu_local_masks(void) |
2f2f52ba BG |
78 | { |
79 | alloc_bootmem_cpumask_var(&cpu_initialized_mask); | |
80 | alloc_bootmem_cpumask_var(&cpu_callin_mask); | |
81 | alloc_bootmem_cpumask_var(&cpu_callout_mask); | |
82 | alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); | |
83 | } | |
84 | ||
148f9bb8 | 85 | static void default_init(struct cpuinfo_x86 *c) |
e8055139 OZ |
86 | { |
87 | #ifdef CONFIG_X86_64 | |
27c13ece | 88 | cpu_detect_cache_sizes(c); |
e8055139 OZ |
89 | #else |
90 | /* Not much we can do here... */ | |
91 | /* Check if at least it has cpuid */ | |
92 | if (c->cpuid_level == -1) { | |
93 | /* No cpuid. It must be an ancient CPU */ | |
94 | if (c->x86 == 4) | |
95 | strcpy(c->x86_model_id, "486"); | |
96 | else if (c->x86 == 3) | |
97 | strcpy(c->x86_model_id, "386"); | |
98 | } | |
99 | #endif | |
100 | } | |
101 | ||
148f9bb8 | 102 | static const struct cpu_dev default_cpu = { |
e8055139 OZ |
103 | .c_init = default_init, |
104 | .c_vendor = "Unknown", | |
105 | .c_x86_vendor = X86_VENDOR_UNKNOWN, | |
106 | }; | |
107 | ||
148f9bb8 | 108 | static const struct cpu_dev *this_cpu = &default_cpu; |
0a488a53 | 109 | |
06deef89 | 110 | DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { |
950ad7ff | 111 | #ifdef CONFIG_X86_64 |
06deef89 BG |
112 | /* |
113 | * We need valid kernel segments for data and code in long mode too | |
114 | * IRET will check the segment types kkeil 2000/10/28 | |
115 | * Also sysret mandates a special GDT layout | |
116 | * | |
9766cdbc | 117 | * TLS descriptors are currently at a different place compared to i386. |
06deef89 BG |
118 | * Hopefully nobody expects them at a fixed place (Wine?) |
119 | */ | |
1e5de182 AM |
120 | [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), |
121 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), | |
122 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), | |
123 | [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), | |
124 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), | |
125 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), | |
950ad7ff | 126 | #else |
1e5de182 AM |
127 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), |
128 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
129 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), | |
130 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), | |
bf504672 RR |
131 | /* |
132 | * Segments used for calling PnP BIOS have byte granularity. | |
133 | * They code segments and data segments have fixed 64k limits, | |
134 | * the transfer segment sizes are set at run time. | |
135 | */ | |
6842ef0e | 136 | /* 32-bit code */ |
1e5de182 | 137 | [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), |
6842ef0e | 138 | /* 16-bit code */ |
1e5de182 | 139 | [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), |
6842ef0e | 140 | /* 16-bit data */ |
1e5de182 | 141 | [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), |
6842ef0e | 142 | /* 16-bit data */ |
1e5de182 | 143 | [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), |
6842ef0e | 144 | /* 16-bit data */ |
1e5de182 | 145 | [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), |
bf504672 RR |
146 | /* |
147 | * The APM segments have byte granularity and their bases | |
148 | * are set at run time. All have 64k limits. | |
149 | */ | |
6842ef0e | 150 | /* 32-bit code */ |
1e5de182 | 151 | [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), |
bf504672 | 152 | /* 16-bit code */ |
1e5de182 | 153 | [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), |
6842ef0e | 154 | /* data */ |
72c4d853 | 155 | [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), |
bf504672 | 156 | |
1e5de182 AM |
157 | [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), |
158 | [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
60a5317f | 159 | GDT_STACK_CANARY_INIT |
950ad7ff | 160 | #endif |
06deef89 | 161 | } }; |
7a61d35d | 162 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); |
ae1ee11b | 163 | |
8c3641e9 | 164 | static int __init x86_mpx_setup(char *s) |
0c752a93 | 165 | { |
8c3641e9 | 166 | /* require an exact match without trailing characters */ |
2cd3949f DH |
167 | if (strlen(s)) |
168 | return 0; | |
0c752a93 | 169 | |
8c3641e9 DH |
170 | /* do not emit a message if the feature is not present */ |
171 | if (!boot_cpu_has(X86_FEATURE_MPX)) | |
172 | return 1; | |
6bad06b7 | 173 | |
8c3641e9 DH |
174 | setup_clear_cpu_cap(X86_FEATURE_MPX); |
175 | pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n"); | |
b6f42a4a FY |
176 | return 1; |
177 | } | |
8c3641e9 | 178 | __setup("nompx", x86_mpx_setup); |
b6f42a4a | 179 | |
0790c9aa | 180 | #ifdef CONFIG_X86_64 |
c7ad5ad2 | 181 | static int __init x86_nopcid_setup(char *s) |
0790c9aa | 182 | { |
c7ad5ad2 AL |
183 | /* nopcid doesn't accept parameters */ |
184 | if (s) | |
185 | return -EINVAL; | |
0790c9aa AL |
186 | |
187 | /* do not emit a message if the feature is not present */ | |
188 | if (!boot_cpu_has(X86_FEATURE_PCID)) | |
c7ad5ad2 | 189 | return 0; |
0790c9aa AL |
190 | |
191 | setup_clear_cpu_cap(X86_FEATURE_PCID); | |
192 | pr_info("nopcid: PCID feature disabled\n"); | |
c7ad5ad2 | 193 | return 0; |
0790c9aa | 194 | } |
c7ad5ad2 | 195 | early_param("nopcid", x86_nopcid_setup); |
0790c9aa AL |
196 | #endif |
197 | ||
d12a72b8 AL |
198 | static int __init x86_noinvpcid_setup(char *s) |
199 | { | |
200 | /* noinvpcid doesn't accept parameters */ | |
201 | if (s) | |
202 | return -EINVAL; | |
203 | ||
204 | /* do not emit a message if the feature is not present */ | |
205 | if (!boot_cpu_has(X86_FEATURE_INVPCID)) | |
206 | return 0; | |
207 | ||
208 | setup_clear_cpu_cap(X86_FEATURE_INVPCID); | |
209 | pr_info("noinvpcid: INVPCID feature disabled\n"); | |
210 | return 0; | |
211 | } | |
212 | early_param("noinvpcid", x86_noinvpcid_setup); | |
213 | ||
ba51dced | 214 | #ifdef CONFIG_X86_32 |
148f9bb8 PG |
215 | static int cachesize_override = -1; |
216 | static int disable_x86_serial_nr = 1; | |
1da177e4 | 217 | |
0a488a53 YL |
218 | static int __init cachesize_setup(char *str) |
219 | { | |
220 | get_option(&str, &cachesize_override); | |
221 | return 1; | |
222 | } | |
223 | __setup("cachesize=", cachesize_setup); | |
224 | ||
0a488a53 YL |
225 | static int __init x86_sep_setup(char *s) |
226 | { | |
227 | setup_clear_cpu_cap(X86_FEATURE_SEP); | |
228 | return 1; | |
229 | } | |
230 | __setup("nosep", x86_sep_setup); | |
231 | ||
232 | /* Standard macro to see if a specific flag is changeable */ | |
233 | static inline int flag_is_changeable_p(u32 flag) | |
234 | { | |
235 | u32 f1, f2; | |
236 | ||
94f6bac1 KH |
237 | /* |
238 | * Cyrix and IDT cpus allow disabling of CPUID | |
239 | * so the code below may return different results | |
240 | * when it is executed before and after enabling | |
241 | * the CPUID. Add "volatile" to not allow gcc to | |
242 | * optimize the subsequent calls to this function. | |
243 | */ | |
0f3fa48a IM |
244 | asm volatile ("pushfl \n\t" |
245 | "pushfl \n\t" | |
246 | "popl %0 \n\t" | |
247 | "movl %0, %1 \n\t" | |
248 | "xorl %2, %0 \n\t" | |
249 | "pushl %0 \n\t" | |
250 | "popfl \n\t" | |
251 | "pushfl \n\t" | |
252 | "popl %0 \n\t" | |
253 | "popfl \n\t" | |
254 | ||
94f6bac1 KH |
255 | : "=&r" (f1), "=&r" (f2) |
256 | : "ir" (flag)); | |
0a488a53 YL |
257 | |
258 | return ((f1^f2) & flag) != 0; | |
259 | } | |
260 | ||
261 | /* Probe for the CPUID instruction */ | |
148f9bb8 | 262 | int have_cpuid_p(void) |
0a488a53 YL |
263 | { |
264 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
265 | } | |
266 | ||
148f9bb8 | 267 | static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
0a488a53 | 268 | { |
0f3fa48a IM |
269 | unsigned long lo, hi; |
270 | ||
271 | if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) | |
272 | return; | |
273 | ||
274 | /* Disable processor serial number: */ | |
275 | ||
276 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
277 | lo |= 0x200000; | |
278 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
279 | ||
1b74dde7 | 280 | pr_notice("CPU serial number disabled.\n"); |
0f3fa48a IM |
281 | clear_cpu_cap(c, X86_FEATURE_PN); |
282 | ||
283 | /* Disabling the serial number may affect the cpuid level */ | |
284 | c->cpuid_level = cpuid_eax(0); | |
0a488a53 YL |
285 | } |
286 | ||
287 | static int __init x86_serial_nr_setup(char *s) | |
288 | { | |
289 | disable_x86_serial_nr = 0; | |
290 | return 1; | |
291 | } | |
292 | __setup("serialnumber", x86_serial_nr_setup); | |
ba51dced | 293 | #else |
102bbe3a YL |
294 | static inline int flag_is_changeable_p(u32 flag) |
295 | { | |
296 | return 1; | |
297 | } | |
102bbe3a YL |
298 | static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
299 | { | |
300 | } | |
ba51dced | 301 | #endif |
0a488a53 | 302 | |
de5397ad FY |
303 | static __init int setup_disable_smep(char *arg) |
304 | { | |
b2cc2a07 | 305 | setup_clear_cpu_cap(X86_FEATURE_SMEP); |
0f6ff2bc DH |
306 | /* Check for things that depend on SMEP being enabled: */ |
307 | check_mpx_erratum(&boot_cpu_data); | |
de5397ad FY |
308 | return 1; |
309 | } | |
310 | __setup("nosmep", setup_disable_smep); | |
311 | ||
b2cc2a07 | 312 | static __always_inline void setup_smep(struct cpuinfo_x86 *c) |
de5397ad | 313 | { |
b2cc2a07 | 314 | if (cpu_has(c, X86_FEATURE_SMEP)) |
375074cc | 315 | cr4_set_bits(X86_CR4_SMEP); |
de5397ad FY |
316 | } |
317 | ||
52b6179a PA |
318 | static __init int setup_disable_smap(char *arg) |
319 | { | |
b2cc2a07 | 320 | setup_clear_cpu_cap(X86_FEATURE_SMAP); |
52b6179a PA |
321 | return 1; |
322 | } | |
323 | __setup("nosmap", setup_disable_smap); | |
324 | ||
b2cc2a07 PA |
325 | static __always_inline void setup_smap(struct cpuinfo_x86 *c) |
326 | { | |
581b7f15 | 327 | unsigned long eflags = native_save_fl(); |
b2cc2a07 PA |
328 | |
329 | /* This should have been cleared long ago */ | |
b2cc2a07 PA |
330 | BUG_ON(eflags & X86_EFLAGS_AC); |
331 | ||
03bbd596 PA |
332 | if (cpu_has(c, X86_FEATURE_SMAP)) { |
333 | #ifdef CONFIG_X86_SMAP | |
375074cc | 334 | cr4_set_bits(X86_CR4_SMAP); |
03bbd596 | 335 | #else |
375074cc | 336 | cr4_clear_bits(X86_CR4_SMAP); |
03bbd596 PA |
337 | #endif |
338 | } | |
de5397ad FY |
339 | } |
340 | ||
06976945 DH |
341 | /* |
342 | * Protection Keys are not available in 32-bit mode. | |
343 | */ | |
344 | static bool pku_disabled; | |
345 | ||
346 | static __always_inline void setup_pku(struct cpuinfo_x86 *c) | |
347 | { | |
e8df1a95 DH |
348 | /* check the boot processor, plus compile options for PKU: */ |
349 | if (!cpu_feature_enabled(X86_FEATURE_PKU)) | |
350 | return; | |
351 | /* checks the actual processor's cpuid bits: */ | |
06976945 DH |
352 | if (!cpu_has(c, X86_FEATURE_PKU)) |
353 | return; | |
354 | if (pku_disabled) | |
355 | return; | |
356 | ||
357 | cr4_set_bits(X86_CR4_PKE); | |
358 | /* | |
359 | * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE | |
360 | * cpuid bit to be set. We need to ensure that we | |
361 | * update that bit in this CPU's "cpu_info". | |
362 | */ | |
363 | get_cpu_cap(c); | |
364 | } | |
365 | ||
366 | #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS | |
367 | static __init int setup_disable_pku(char *arg) | |
368 | { | |
369 | /* | |
370 | * Do not clear the X86_FEATURE_PKU bit. All of the | |
371 | * runtime checks are against OSPKE so clearing the | |
372 | * bit does nothing. | |
373 | * | |
374 | * This way, we will see "pku" in cpuinfo, but not | |
375 | * "ospke", which is exactly what we want. It shows | |
376 | * that the CPU has PKU, but the OS has not enabled it. | |
377 | * This happens to be exactly how a system would look | |
378 | * if we disabled the config option. | |
379 | */ | |
380 | pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n"); | |
381 | pku_disabled = true; | |
382 | return 1; | |
383 | } | |
384 | __setup("nopku", setup_disable_pku); | |
385 | #endif /* CONFIG_X86_64 */ | |
386 | ||
b38b0665 PA |
387 | /* |
388 | * Some CPU features depend on higher CPUID levels, which may not always | |
389 | * be available due to CPUID level capping or broken virtualization | |
390 | * software. Add those features to this table to auto-disable them. | |
391 | */ | |
392 | struct cpuid_dependent_feature { | |
393 | u32 feature; | |
394 | u32 level; | |
395 | }; | |
0f3fa48a | 396 | |
148f9bb8 | 397 | static const struct cpuid_dependent_feature |
b38b0665 PA |
398 | cpuid_dependent_features[] = { |
399 | { X86_FEATURE_MWAIT, 0x00000005 }, | |
400 | { X86_FEATURE_DCA, 0x00000009 }, | |
401 | { X86_FEATURE_XSAVE, 0x0000000d }, | |
402 | { 0, 0 } | |
403 | }; | |
404 | ||
148f9bb8 | 405 | static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) |
b38b0665 PA |
406 | { |
407 | const struct cpuid_dependent_feature *df; | |
9766cdbc | 408 | |
b38b0665 | 409 | for (df = cpuid_dependent_features; df->feature; df++) { |
0f3fa48a IM |
410 | |
411 | if (!cpu_has(c, df->feature)) | |
412 | continue; | |
b38b0665 PA |
413 | /* |
414 | * Note: cpuid_level is set to -1 if unavailable, but | |
415 | * extended_extended_level is set to 0 if unavailable | |
416 | * and the legitimate extended levels are all negative | |
417 | * when signed; hence the weird messing around with | |
418 | * signs here... | |
419 | */ | |
0f3fa48a | 420 | if (!((s32)df->level < 0 ? |
f6db44df | 421 | (u32)df->level > (u32)c->extended_cpuid_level : |
0f3fa48a IM |
422 | (s32)df->level > (s32)c->cpuid_level)) |
423 | continue; | |
424 | ||
425 | clear_cpu_cap(c, df->feature); | |
426 | if (!warn) | |
427 | continue; | |
428 | ||
1b74dde7 CY |
429 | pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", |
430 | x86_cap_flag(df->feature), df->level); | |
b38b0665 | 431 | } |
f6db44df | 432 | } |
b38b0665 | 433 | |
102bbe3a YL |
434 | /* |
435 | * Naming convention should be: <Name> [(<Codename>)] | |
436 | * This table only is used unless init_<vendor>() below doesn't set it; | |
0f3fa48a IM |
437 | * in particular, if CPUID levels 0x80000002..4 are supported, this |
438 | * isn't used | |
102bbe3a YL |
439 | */ |
440 | ||
441 | /* Look up CPU names by table lookup. */ | |
148f9bb8 | 442 | static const char *table_lookup_model(struct cpuinfo_x86 *c) |
102bbe3a | 443 | { |
09dc68d9 JB |
444 | #ifdef CONFIG_X86_32 |
445 | const struct legacy_cpu_model_info *info; | |
102bbe3a YL |
446 | |
447 | if (c->x86_model >= 16) | |
448 | return NULL; /* Range check */ | |
449 | ||
450 | if (!this_cpu) | |
451 | return NULL; | |
452 | ||
09dc68d9 | 453 | info = this_cpu->legacy_models; |
102bbe3a | 454 | |
09dc68d9 | 455 | while (info->family) { |
102bbe3a YL |
456 | if (info->family == c->x86) |
457 | return info->model_names[c->x86_model]; | |
458 | info++; | |
459 | } | |
09dc68d9 | 460 | #endif |
102bbe3a YL |
461 | return NULL; /* Not found */ |
462 | } | |
463 | ||
8388d287 TG |
464 | __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS]; |
465 | __u32 cpu_caps_set[NCAPINTS + NBUGINTS]; | |
7d851c8d | 466 | |
11e3a840 JF |
467 | void load_percpu_segment(int cpu) |
468 | { | |
469 | #ifdef CONFIG_X86_32 | |
470 | loadsegment(fs, __KERNEL_PERCPU); | |
471 | #else | |
45e876f7 | 472 | __loadsegment_simple(gs, 0); |
11e3a840 JF |
473 | wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); |
474 | #endif | |
60a5317f | 475 | load_stack_canary_segment(); |
11e3a840 JF |
476 | } |
477 | ||
5bb40c6d AL |
478 | #ifdef CONFIG_X86_32 |
479 | /* The 32-bit entry code needs to find cpu_entry_area. */ | |
480 | DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area); | |
481 | #endif | |
482 | ||
bb568391 AL |
483 | #ifdef CONFIG_X86_64 |
484 | /* | |
485 | * Special IST stacks which the CPU switches to when it calls | |
486 | * an IST-marked descriptor entry. Up to 7 stacks (hardware | |
487 | * limit), all of them are 4K, except the debug stack which | |
488 | * is 8K. | |
489 | */ | |
490 | static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { | |
491 | [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, | |
492 | [DEBUG_STACK - 1] = DEBUG_STKSZ | |
493 | }; | |
45fc8757 | 494 | #endif |
69218e47 | 495 | |
45fc8757 TG |
496 | /* Load the original GDT from the per-cpu structure */ |
497 | void load_direct_gdt(int cpu) | |
498 | { | |
499 | struct desc_ptr gdt_descr; | |
500 | ||
501 | gdt_descr.address = (long)get_cpu_gdt_rw(cpu); | |
502 | gdt_descr.size = GDT_SIZE - 1; | |
503 | load_gdt(&gdt_descr); | |
504 | } | |
505 | EXPORT_SYMBOL_GPL(load_direct_gdt); | |
506 | ||
69218e47 TG |
507 | /* Load a fixmap remapping of the per-cpu GDT */ |
508 | void load_fixmap_gdt(int cpu) | |
509 | { | |
510 | struct desc_ptr gdt_descr; | |
511 | ||
512 | gdt_descr.address = (long)get_cpu_gdt_ro(cpu); | |
513 | gdt_descr.size = GDT_SIZE - 1; | |
514 | load_gdt(&gdt_descr); | |
515 | } | |
45fc8757 | 516 | EXPORT_SYMBOL_GPL(load_fixmap_gdt); |
69218e47 | 517 | |
0f3fa48a IM |
518 | /* |
519 | * Current gdt points %fs at the "master" per-cpu area: after this, | |
520 | * it's on the real one. | |
521 | */ | |
552be871 | 522 | void switch_to_new_gdt(int cpu) |
9d31d35b | 523 | { |
45fc8757 TG |
524 | /* Load the original GDT */ |
525 | load_direct_gdt(cpu); | |
2697fbd5 | 526 | /* Reload the per-cpu base */ |
11e3a840 | 527 | load_percpu_segment(cpu); |
9d31d35b YL |
528 | } |
529 | ||
148f9bb8 | 530 | static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; |
1da177e4 | 531 | |
148f9bb8 | 532 | static void get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
533 | { |
534 | unsigned int *v; | |
ee098e1a | 535 | char *p, *q, *s; |
1da177e4 | 536 | |
3da99c97 | 537 | if (c->extended_cpuid_level < 0x80000004) |
1b05d60d | 538 | return; |
1da177e4 | 539 | |
0f3fa48a | 540 | v = (unsigned int *)c->x86_model_id; |
1da177e4 LT |
541 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); |
542 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
543 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
544 | c->x86_model_id[48] = 0; | |
545 | ||
ee098e1a BP |
546 | /* Trim whitespace */ |
547 | p = q = s = &c->x86_model_id[0]; | |
548 | ||
549 | while (*p == ' ') | |
550 | p++; | |
551 | ||
552 | while (*p) { | |
553 | /* Note the last non-whitespace index */ | |
554 | if (!isspace(*p)) | |
555 | s = q; | |
556 | ||
557 | *q++ = *p++; | |
558 | } | |
559 | ||
560 | *(s + 1) = '\0'; | |
1da177e4 LT |
561 | } |
562 | ||
148f9bb8 | 563 | void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) |
1da177e4 | 564 | { |
9d31d35b | 565 | unsigned int n, dummy, ebx, ecx, edx, l2size; |
1da177e4 | 566 | |
3da99c97 | 567 | n = c->extended_cpuid_level; |
1da177e4 LT |
568 | |
569 | if (n >= 0x80000005) { | |
9d31d35b | 570 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); |
9d31d35b | 571 | c->x86_cache_size = (ecx>>24) + (edx>>24); |
140fc727 YL |
572 | #ifdef CONFIG_X86_64 |
573 | /* On K8 L1 TLB is inclusive, so don't count it */ | |
574 | c->x86_tlbsize = 0; | |
575 | #endif | |
1da177e4 LT |
576 | } |
577 | ||
578 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
579 | return; | |
580 | ||
0a488a53 | 581 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 582 | l2size = ecx >> 16; |
34048c9e | 583 | |
140fc727 YL |
584 | #ifdef CONFIG_X86_64 |
585 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
586 | #else | |
1da177e4 | 587 | /* do processor-specific cache resizing */ |
09dc68d9 JB |
588 | if (this_cpu->legacy_cache_size) |
589 | l2size = this_cpu->legacy_cache_size(c, l2size); | |
1da177e4 LT |
590 | |
591 | /* Allow user to override all this if necessary. */ | |
592 | if (cachesize_override != -1) | |
593 | l2size = cachesize_override; | |
594 | ||
34048c9e | 595 | if (l2size == 0) |
1da177e4 | 596 | return; /* Again, no L2 cache is possible */ |
140fc727 | 597 | #endif |
1da177e4 LT |
598 | |
599 | c->x86_cache_size = l2size; | |
1da177e4 LT |
600 | } |
601 | ||
e0ba94f1 AS |
602 | u16 __read_mostly tlb_lli_4k[NR_INFO]; |
603 | u16 __read_mostly tlb_lli_2m[NR_INFO]; | |
604 | u16 __read_mostly tlb_lli_4m[NR_INFO]; | |
605 | u16 __read_mostly tlb_lld_4k[NR_INFO]; | |
606 | u16 __read_mostly tlb_lld_2m[NR_INFO]; | |
607 | u16 __read_mostly tlb_lld_4m[NR_INFO]; | |
dd360393 | 608 | u16 __read_mostly tlb_lld_1g[NR_INFO]; |
e0ba94f1 | 609 | |
f94fe119 | 610 | static void cpu_detect_tlb(struct cpuinfo_x86 *c) |
e0ba94f1 AS |
611 | { |
612 | if (this_cpu->c_detect_tlb) | |
613 | this_cpu->c_detect_tlb(c); | |
614 | ||
f94fe119 | 615 | pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", |
e0ba94f1 | 616 | tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], |
f94fe119 SH |
617 | tlb_lli_4m[ENTRIES]); |
618 | ||
619 | pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", | |
620 | tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES], | |
621 | tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); | |
e0ba94f1 AS |
622 | } |
623 | ||
bfa4f8ae | 624 | int detect_ht_early(struct cpuinfo_x86 *c) |
1da177e4 | 625 | { |
c8e56d20 | 626 | #ifdef CONFIG_SMP |
0a488a53 | 627 | u32 eax, ebx, ecx, edx; |
1da177e4 | 628 | |
0a488a53 | 629 | if (!cpu_has(c, X86_FEATURE_HT)) |
bfa4f8ae | 630 | return -1; |
1da177e4 | 631 | |
0a488a53 | 632 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
bfa4f8ae | 633 | return -1; |
1da177e4 | 634 | |
1cd78776 | 635 | if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) |
bfa4f8ae | 636 | return -1; |
1da177e4 | 637 | |
0a488a53 | 638 | cpuid(1, &eax, &ebx, &ecx, &edx); |
1da177e4 | 639 | |
9d31d35b | 640 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
bfa4f8ae TG |
641 | if (smp_num_siblings == 1) |
642 | pr_info_once("CPU0: Hyper-Threading is disabled\n"); | |
643 | #endif | |
644 | return 0; | |
645 | } | |
9d31d35b | 646 | |
bfa4f8ae TG |
647 | void detect_ht(struct cpuinfo_x86 *c) |
648 | { | |
649 | #ifdef CONFIG_SMP | |
650 | int index_msb, core_bits; | |
728ac482 | 651 | |
bfa4f8ae | 652 | if (detect_ht_early(c) < 0) |
728ac482 | 653 | return; |
9d31d35b | 654 | |
0f3fa48a IM |
655 | index_msb = get_count_order(smp_num_siblings); |
656 | c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); | |
9d31d35b | 657 | |
0f3fa48a | 658 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; |
9d31d35b | 659 | |
0f3fa48a | 660 | index_msb = get_count_order(smp_num_siblings); |
9d31d35b | 661 | |
0f3fa48a | 662 | core_bits = get_count_order(c->x86_max_cores); |
9d31d35b | 663 | |
0f3fa48a IM |
664 | c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & |
665 | ((1 << core_bits) - 1); | |
9d31d35b | 666 | #endif |
97e4db7c | 667 | } |
1da177e4 | 668 | |
148f9bb8 | 669 | static void get_cpu_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
670 | { |
671 | char *v = c->x86_vendor_id; | |
0f3fa48a | 672 | int i; |
1da177e4 LT |
673 | |
674 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
10a434fc YL |
675 | if (!cpu_devs[i]) |
676 | break; | |
677 | ||
678 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
679 | (cpu_devs[i]->c_ident[1] && | |
680 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
0f3fa48a | 681 | |
10a434fc YL |
682 | this_cpu = cpu_devs[i]; |
683 | c->x86_vendor = this_cpu->c_x86_vendor; | |
684 | return; | |
1da177e4 LT |
685 | } |
686 | } | |
10a434fc | 687 | |
1b74dde7 CY |
688 | pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \ |
689 | "CPU: Your system may be unstable.\n", v); | |
10a434fc | 690 | |
fe38d855 CE |
691 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
692 | this_cpu = &default_cpu; | |
1da177e4 LT |
693 | } |
694 | ||
148f9bb8 | 695 | void cpu_detect(struct cpuinfo_x86 *c) |
1da177e4 | 696 | { |
1da177e4 | 697 | /* Get vendor name */ |
4a148513 HH |
698 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, |
699 | (unsigned int *)&c->x86_vendor_id[0], | |
700 | (unsigned int *)&c->x86_vendor_id[8], | |
701 | (unsigned int *)&c->x86_vendor_id[4]); | |
1da177e4 | 702 | |
1da177e4 | 703 | c->x86 = 4; |
9d31d35b | 704 | /* Intel-defined flags: level 0x00000001 */ |
1da177e4 LT |
705 | if (c->cpuid_level >= 0x00000001) { |
706 | u32 junk, tfms, cap0, misc; | |
0f3fa48a | 707 | |
1da177e4 | 708 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); |
99f925ce BP |
709 | c->x86 = x86_family(tfms); |
710 | c->x86_model = x86_model(tfms); | |
325cbb04 | 711 | c->x86_stepping = x86_stepping(tfms); |
0f3fa48a | 712 | |
d4387bd3 | 713 | if (cap0 & (1<<19)) { |
d4387bd3 | 714 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
9d31d35b | 715 | c->x86_cache_alignment = c->x86_clflush_size; |
d4387bd3 | 716 | } |
1da177e4 | 717 | } |
1da177e4 | 718 | } |
3da99c97 | 719 | |
8bf1ebca AL |
720 | static void apply_forced_caps(struct cpuinfo_x86 *c) |
721 | { | |
722 | int i; | |
723 | ||
8388d287 | 724 | for (i = 0; i < NCAPINTS + NBUGINTS; i++) { |
8bf1ebca AL |
725 | c->x86_capability[i] &= ~cpu_caps_cleared[i]; |
726 | c->x86_capability[i] |= cpu_caps_set[i]; | |
727 | } | |
728 | } | |
729 | ||
85543d76 DW |
730 | static void init_speculation_control(struct cpuinfo_x86 *c) |
731 | { | |
732 | /* | |
733 | * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support, | |
734 | * and they also have a different bit for STIBP support. Also, | |
735 | * a hypervisor might have set the individual AMD bits even on | |
736 | * Intel CPUs, for finer-grained selection of what's available. | |
85543d76 DW |
737 | */ |
738 | if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) { | |
739 | set_cpu_cap(c, X86_FEATURE_IBRS); | |
740 | set_cpu_cap(c, X86_FEATURE_IBPB); | |
8e0836d1 | 741 | set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); |
85543d76 | 742 | } |
b1d1984f | 743 | |
85543d76 DW |
744 | if (cpu_has(c, X86_FEATURE_INTEL_STIBP)) |
745 | set_cpu_cap(c, X86_FEATURE_STIBP); | |
b1d1984f | 746 | |
e8837f0a TL |
747 | if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) || |
748 | cpu_has(c, X86_FEATURE_VIRT_SSBD)) | |
bbc0d1c3 TG |
749 | set_cpu_cap(c, X86_FEATURE_SSBD); |
750 | ||
8e0836d1 | 751 | if (cpu_has(c, X86_FEATURE_AMD_IBRS)) { |
b1d1984f | 752 | set_cpu_cap(c, X86_FEATURE_IBRS); |
8e0836d1 TG |
753 | set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); |
754 | } | |
b1d1984f BP |
755 | |
756 | if (cpu_has(c, X86_FEATURE_AMD_IBPB)) | |
757 | set_cpu_cap(c, X86_FEATURE_IBPB); | |
758 | ||
8e0836d1 | 759 | if (cpu_has(c, X86_FEATURE_AMD_STIBP)) { |
b1d1984f | 760 | set_cpu_cap(c, X86_FEATURE_STIBP); |
8e0836d1 TG |
761 | set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); |
762 | } | |
54b65f8e KRW |
763 | |
764 | if (cpu_has(c, X86_FEATURE_AMD_SSBD)) { | |
765 | set_cpu_cap(c, X86_FEATURE_SSBD); | |
766 | set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); | |
767 | clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD); | |
768 | } | |
85543d76 DW |
769 | } |
770 | ||
091c0268 BP |
771 | static void init_cqm(struct cpuinfo_x86 *c) |
772 | { | |
d63c2a99 FY |
773 | if (!cpu_has(c, X86_FEATURE_CQM_LLC)) { |
774 | c->x86_cache_max_rmid = -1; | |
775 | c->x86_cache_occ_scale = -1; | |
776 | return; | |
777 | } | |
091c0268 | 778 | |
d63c2a99 FY |
779 | /* will be overridden if occupancy monitoring exists */ |
780 | c->x86_cache_max_rmid = cpuid_ebx(0xf); | |
781 | ||
782 | if (cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC) || | |
783 | cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL) || | |
784 | cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)) { | |
785 | u32 eax, ebx, ecx, edx; | |
786 | ||
787 | /* QoS sub-leaf, EAX=0Fh, ECX=1 */ | |
788 | cpuid_count(0xf, 1, &eax, &ebx, &ecx, &edx); | |
789 | ||
790 | c->x86_cache_max_rmid = ecx; | |
791 | c->x86_cache_occ_scale = ebx; | |
091c0268 BP |
792 | } |
793 | } | |
794 | ||
148f9bb8 | 795 | void get_cpu_cap(struct cpuinfo_x86 *c) |
093af8d7 | 796 | { |
39c06df4 | 797 | u32 eax, ebx, ecx, edx; |
093af8d7 | 798 | |
3da99c97 YL |
799 | /* Intel-defined flags: level 0x00000001 */ |
800 | if (c->cpuid_level >= 0x00000001) { | |
39c06df4 | 801 | cpuid(0x00000001, &eax, &ebx, &ecx, &edx); |
0f3fa48a | 802 | |
39c06df4 BP |
803 | c->x86_capability[CPUID_1_ECX] = ecx; |
804 | c->x86_capability[CPUID_1_EDX] = edx; | |
3da99c97 | 805 | } |
093af8d7 | 806 | |
3df8d920 AL |
807 | /* Thermal and Power Management Leaf: level 0x00000006 (eax) */ |
808 | if (c->cpuid_level >= 0x00000006) | |
809 | c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); | |
810 | ||
bdc802dc PA |
811 | /* Additional Intel-defined flags: level 0x00000007 */ |
812 | if (c->cpuid_level >= 0x00000007) { | |
bdc802dc | 813 | cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); |
39c06df4 | 814 | c->x86_capability[CPUID_7_0_EBX] = ebx; |
dfb4a70f | 815 | c->x86_capability[CPUID_7_ECX] = ecx; |
76c4bd53 | 816 | c->x86_capability[CPUID_7_EDX] = edx; |
bdc802dc PA |
817 | } |
818 | ||
6229ad27 FY |
819 | /* Extended state features: level 0x0000000d */ |
820 | if (c->cpuid_level >= 0x0000000d) { | |
6229ad27 FY |
821 | cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); |
822 | ||
39c06df4 | 823 | c->x86_capability[CPUID_D_1_EAX] = eax; |
6229ad27 FY |
824 | } |
825 | ||
3da99c97 | 826 | /* AMD-defined flags: level 0x80000001 */ |
39c06df4 BP |
827 | eax = cpuid_eax(0x80000000); |
828 | c->extended_cpuid_level = eax; | |
829 | ||
830 | if ((eax & 0xffff0000) == 0x80000000) { | |
831 | if (eax >= 0x80000001) { | |
832 | cpuid(0x80000001, &eax, &ebx, &ecx, &edx); | |
0f3fa48a | 833 | |
39c06df4 BP |
834 | c->x86_capability[CPUID_8000_0001_ECX] = ecx; |
835 | c->x86_capability[CPUID_8000_0001_EDX] = edx; | |
093af8d7 | 836 | } |
093af8d7 | 837 | } |
093af8d7 | 838 | |
71faad43 YG |
839 | if (c->extended_cpuid_level >= 0x80000007) { |
840 | cpuid(0x80000007, &eax, &ebx, &ecx, &edx); | |
841 | ||
842 | c->x86_capability[CPUID_8000_0007_EBX] = ebx; | |
843 | c->x86_power = edx; | |
844 | } | |
845 | ||
5122c890 | 846 | if (c->extended_cpuid_level >= 0x80000008) { |
39c06df4 | 847 | cpuid(0x80000008, &eax, &ebx, &ecx, &edx); |
5122c890 YL |
848 | |
849 | c->x86_virt_bits = (eax >> 8) & 0xff; | |
850 | c->x86_phys_bits = eax & 0xff; | |
39c06df4 | 851 | c->x86_capability[CPUID_8000_0008_EBX] = ebx; |
093af8d7 | 852 | } |
13c6c532 JB |
853 | #ifdef CONFIG_X86_32 |
854 | else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) | |
855 | c->x86_phys_bits = 36; | |
5122c890 | 856 | #endif |
e3224234 | 857 | |
2ccd71f1 | 858 | if (c->extended_cpuid_level >= 0x8000000a) |
39c06df4 | 859 | c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); |
093af8d7 | 860 | |
1dedefd1 | 861 | init_scattered_cpuid_features(c); |
85543d76 | 862 | init_speculation_control(c); |
091c0268 | 863 | init_cqm(c); |
60d34501 AL |
864 | |
865 | /* | |
866 | * Clear/Set all flags overridden by options, after probe. | |
867 | * This needs to happen each time we re-probe, which may happen | |
868 | * several times during CPU initialization. | |
869 | */ | |
870 | apply_forced_caps(c); | |
093af8d7 | 871 | } |
1da177e4 | 872 | |
148f9bb8 | 873 | static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) |
aef93c8b YL |
874 | { |
875 | #ifdef CONFIG_X86_32 | |
876 | int i; | |
877 | ||
878 | /* | |
879 | * First of all, decide if this is a 486 or higher | |
880 | * It's a 486 if we can modify the AC flag | |
881 | */ | |
882 | if (flag_is_changeable_p(X86_EFLAGS_AC)) | |
883 | c->x86 = 4; | |
884 | else | |
885 | c->x86 = 3; | |
886 | ||
887 | for (i = 0; i < X86_VENDOR_NUM; i++) | |
888 | if (cpu_devs[i] && cpu_devs[i]->c_identify) { | |
889 | c->x86_vendor_id[0] = 0; | |
890 | cpu_devs[i]->c_identify(c); | |
891 | if (c->x86_vendor_id[0]) { | |
892 | get_cpu_vendor(c); | |
893 | break; | |
894 | } | |
895 | } | |
896 | #endif | |
ec403483 | 897 | c->x86_cache_bits = c->x86_phys_bits; |
aef93c8b YL |
898 | } |
899 | ||
56a0f386 VT |
900 | #define NO_SPECULATION BIT(0) |
901 | #define NO_MELTDOWN BIT(1) | |
902 | #define NO_SSB BIT(2) | |
903 | #define NO_L1TF BIT(3) | |
904 | #define NO_MDS BIT(4) | |
905 | #define MSBDS_ONLY BIT(5) | |
906 | #define NO_SWAPGS BIT(6) | |
907 | #define NO_ITLB_MULTIHIT BIT(7) | |
1553938d TG |
908 | |
909 | #define VULNWL(_vendor, _family, _model, _whitelist) \ | |
910 | { X86_VENDOR_##_vendor, _family, _model, X86_FEATURE_ANY, _whitelist } | |
911 | ||
912 | #define VULNWL_INTEL(model, whitelist) \ | |
913 | VULNWL(INTEL, 6, INTEL_FAM6_##model, whitelist) | |
914 | ||
915 | #define VULNWL_AMD(family, whitelist) \ | |
916 | VULNWL(AMD, family, X86_MODEL_ANY, whitelist) | |
917 | ||
918 | static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { | |
919 | VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION), | |
920 | VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION), | |
921 | VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION), | |
922 | VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION), | |
923 | ||
f619a159 | 924 | /* Intel Family 6 */ |
56a0f386 VT |
925 | VULNWL_INTEL(ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT), |
926 | VULNWL_INTEL(ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT), | |
927 | VULNWL_INTEL(ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), | |
928 | VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT), | |
929 | VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), | |
930 | ||
931 | VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), | |
932 | VULNWL_INTEL(ATOM_SILVERMONT_X, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), | |
933 | VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), | |
934 | VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), | |
935 | VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), | |
936 | VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), | |
1553938d TG |
937 | |
938 | VULNWL_INTEL(CORE_YONAH, NO_SSB), | |
939 | ||
56a0f386 | 940 | VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), |
1553938d | 941 | |
56a0f386 VT |
942 | VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), |
943 | VULNWL_INTEL(ATOM_GOLDMONT_X, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), | |
944 | VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), | |
c4e6262b TG |
945 | |
946 | /* | |
947 | * Technically, swapgs isn't serializing on AMD (despite it previously | |
948 | * being documented as such in the APM). But according to AMD, %gs is | |
949 | * updated non-speculatively, and the issuing of %gs-relative memory | |
950 | * operands will be blocked until the %gs update completes, which is | |
951 | * good enough for our purposes. | |
952 | */ | |
f619a159 AK |
953 | |
954 | /* AMD Family 0xf - 0x12 */ | |
56a0f386 VT |
955 | VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), |
956 | VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), | |
957 | VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), | |
958 | VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), | |
1553938d TG |
959 | |
960 | /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */ | |
56a0f386 | 961 | VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), |
d9b47a41 DW |
962 | {} |
963 | }; | |
964 | ||
1553938d TG |
965 | static bool __init cpu_matches(unsigned long which) |
966 | { | |
967 | const struct x86_cpu_id *m = x86_match_cpu(cpu_vuln_whitelist); | |
c6dc89dd | 968 | |
1553938d TG |
969 | return m && !!(m->driver_data & which); |
970 | } | |
3d98de69 | 971 | |
52bd862a | 972 | u64 x86_read_arch_cap_msr(void) |
d9b47a41 DW |
973 | { |
974 | u64 ia32_cap = 0; | |
975 | ||
52bd862a PG |
976 | if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) |
977 | rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap); | |
978 | ||
979 | return ia32_cap; | |
980 | } | |
981 | ||
982 | static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) | |
983 | { | |
984 | u64 ia32_cap = x86_read_arch_cap_msr(); | |
985 | ||
56a0f386 VT |
986 | /* Set ITLB_MULTIHIT bug if cpu is not in the whitelist and not mitigated */ |
987 | if (!cpu_matches(NO_ITLB_MULTIHIT) && !(ia32_cap & ARCH_CAP_PSCHANGE_MC_NO)) | |
988 | setup_force_cpu_bug(X86_BUG_ITLB_MULTIHIT); | |
989 | ||
1553938d | 990 | if (cpu_matches(NO_SPECULATION)) |
80ceda7b DB |
991 | return; |
992 | ||
993 | setup_force_cpu_bug(X86_BUG_SPECTRE_V1); | |
994 | setup_force_cpu_bug(X86_BUG_SPECTRE_V2); | |
995 | ||
1553938d | 996 | if (!cpu_matches(NO_SSB) && !(ia32_cap & ARCH_CAP_SSB_NO) && |
da06d6d1 | 997 | !cpu_has(c, X86_FEATURE_AMD_SSB_NO)) |
c6dc89dd KRW |
998 | setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS); |
999 | ||
a7051265 SP |
1000 | if (ia32_cap & ARCH_CAP_IBRS_ALL) |
1001 | setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED); | |
1002 | ||
9a805a7f | 1003 | if (!cpu_matches(NO_MDS) && !(ia32_cap & ARCH_CAP_MDS_NO)) { |
f619a159 | 1004 | setup_force_cpu_bug(X86_BUG_MDS); |
9a805a7f TG |
1005 | if (cpu_matches(MSBDS_ONLY)) |
1006 | setup_force_cpu_bug(X86_BUG_MSBDS_ONLY); | |
1007 | } | |
f619a159 | 1008 | |
c4e6262b TG |
1009 | if (!cpu_matches(NO_SWAPGS)) |
1010 | setup_force_cpu_bug(X86_BUG_SWAPGS); | |
1011 | ||
9a575777 PG |
1012 | /* |
1013 | * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when: | |
1014 | * - TSX is supported or | |
1015 | * - TSX_CTRL is present | |
1016 | * | |
1017 | * TSX_CTRL check is needed for cases when TSX could be disabled before | |
1018 | * the kernel boot e.g. kexec. | |
1019 | * TSX_CTRL check alone is not sufficient for cases when the microcode | |
1020 | * update is not present or running as guest that don't get TSX_CTRL. | |
1021 | */ | |
1022 | if (!(ia32_cap & ARCH_CAP_TAA_NO) && | |
1023 | (cpu_has(c, X86_FEATURE_RTM) || | |
1024 | (ia32_cap & ARCH_CAP_TSX_CTRL_MSR))) | |
1025 | setup_force_cpu_bug(X86_BUG_TAA); | |
1026 | ||
1553938d | 1027 | if (cpu_matches(NO_MELTDOWN)) |
69dc7380 | 1028 | return; |
d9b47a41 | 1029 | |
d9b47a41 DW |
1030 | /* Rogue Data Cache Load? No! */ |
1031 | if (ia32_cap & ARCH_CAP_RDCL_NO) | |
69dc7380 | 1032 | return; |
d9b47a41 | 1033 | |
69dc7380 | 1034 | setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN); |
3d98de69 | 1035 | |
1553938d | 1036 | if (cpu_matches(NO_L1TF)) |
3d98de69 AK |
1037 | return; |
1038 | ||
1039 | setup_force_cpu_bug(X86_BUG_L1TF); | |
d9b47a41 DW |
1040 | } |
1041 | ||
34048c9e PC |
1042 | /* |
1043 | * Do minimum CPU detection early. | |
1044 | * Fields really needed: vendor, cpuid_level, family, model, mask, | |
1045 | * cache alignment. | |
1046 | * The others are not touched to avoid unwanted side effects. | |
1047 | * | |
1048 | * WARNING: this function is only called on the BP. Don't add code here | |
1049 | * that is supposed to run on all CPUs. | |
1050 | */ | |
3da99c97 | 1051 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) |
d7cd5611 | 1052 | { |
6627d242 YL |
1053 | #ifdef CONFIG_X86_64 |
1054 | c->x86_clflush_size = 64; | |
13c6c532 JB |
1055 | c->x86_phys_bits = 36; |
1056 | c->x86_virt_bits = 48; | |
6627d242 | 1057 | #else |
d4387bd3 | 1058 | c->x86_clflush_size = 32; |
13c6c532 JB |
1059 | c->x86_phys_bits = 32; |
1060 | c->x86_virt_bits = 32; | |
6627d242 | 1061 | #endif |
0a488a53 | 1062 | c->x86_cache_alignment = c->x86_clflush_size; |
d7cd5611 | 1063 | |
3da99c97 | 1064 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
0a488a53 | 1065 | c->extended_cpuid_level = 0; |
d7cd5611 | 1066 | |
aef93c8b | 1067 | /* cyrix could have cpuid enabled via c_identify()*/ |
05fb3c19 AL |
1068 | if (have_cpuid_p()) { |
1069 | cpu_detect(c); | |
1070 | get_cpu_vendor(c); | |
1071 | get_cpu_cap(c); | |
78d1b296 | 1072 | setup_force_cpu_cap(X86_FEATURE_CPUID); |
d7cd5611 | 1073 | |
05fb3c19 AL |
1074 | if (this_cpu->c_early_init) |
1075 | this_cpu->c_early_init(c); | |
12cf105c | 1076 | |
05fb3c19 AL |
1077 | c->cpu_index = 0; |
1078 | filter_cpuid_features(c, false); | |
093af8d7 | 1079 | |
05fb3c19 AL |
1080 | if (this_cpu->c_bsp_init) |
1081 | this_cpu->c_bsp_init(c); | |
78d1b296 BP |
1082 | } else { |
1083 | identify_cpu_without_cpuid(c); | |
1084 | setup_clear_cpu_cap(X86_FEATURE_CPUID); | |
05fb3c19 | 1085 | } |
c3b83598 BP |
1086 | |
1087 | setup_force_cpu_cap(X86_FEATURE_ALWAYS); | |
72a2bedd | 1088 | |
69dc7380 | 1089 | cpu_set_bug_bits(c); |
9298e868 | 1090 | |
db52ef74 | 1091 | fpu__init_system(c); |
b8b7abae AL |
1092 | |
1093 | #ifdef CONFIG_X86_32 | |
1094 | /* | |
1095 | * Regardless of whether PCID is enumerated, the SDM says | |
1096 | * that it can't be enabled in 32-bit mode. | |
1097 | */ | |
1098 | setup_clear_cpu_cap(X86_FEATURE_PCID); | |
1099 | #endif | |
d7cd5611 RR |
1100 | } |
1101 | ||
9d31d35b YL |
1102 | void __init early_cpu_init(void) |
1103 | { | |
02dde8b4 | 1104 | const struct cpu_dev *const *cdev; |
10a434fc YL |
1105 | int count = 0; |
1106 | ||
ac23f253 | 1107 | #ifdef CONFIG_PROCESSOR_SELECT |
1b74dde7 | 1108 | pr_info("KERNEL supported cpus:\n"); |
31c997ca IM |
1109 | #endif |
1110 | ||
10a434fc | 1111 | for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { |
02dde8b4 | 1112 | const struct cpu_dev *cpudev = *cdev; |
9d31d35b | 1113 | |
10a434fc YL |
1114 | if (count >= X86_VENDOR_NUM) |
1115 | break; | |
1116 | cpu_devs[count] = cpudev; | |
1117 | count++; | |
1118 | ||
ac23f253 | 1119 | #ifdef CONFIG_PROCESSOR_SELECT |
31c997ca IM |
1120 | { |
1121 | unsigned int j; | |
1122 | ||
1123 | for (j = 0; j < 2; j++) { | |
1124 | if (!cpudev->c_ident[j]) | |
1125 | continue; | |
1b74dde7 | 1126 | pr_info(" %s %s\n", cpudev->c_vendor, |
31c997ca IM |
1127 | cpudev->c_ident[j]); |
1128 | } | |
10a434fc | 1129 | } |
0388423d | 1130 | #endif |
10a434fc | 1131 | } |
9d31d35b | 1132 | early_identify_cpu(&boot_cpu_data); |
d7cd5611 | 1133 | } |
093af8d7 | 1134 | |
b6734c35 | 1135 | /* |
366d4a43 BP |
1136 | * The NOPL instruction is supposed to exist on all CPUs of family >= 6; |
1137 | * unfortunately, that's not true in practice because of early VIA | |
1138 | * chips and (more importantly) broken virtualizers that are not easy | |
1139 | * to detect. In the latter case it doesn't even *fail* reliably, so | |
1140 | * probing for it doesn't even work. Disable it completely on 32-bit | |
ba0593bf | 1141 | * unless we can find a reliable way to detect all the broken cases. |
366d4a43 | 1142 | * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). |
b6734c35 | 1143 | */ |
148f9bb8 | 1144 | static void detect_nopl(struct cpuinfo_x86 *c) |
b6734c35 | 1145 | { |
366d4a43 | 1146 | #ifdef CONFIG_X86_32 |
b6734c35 | 1147 | clear_cpu_cap(c, X86_FEATURE_NOPL); |
366d4a43 BP |
1148 | #else |
1149 | set_cpu_cap(c, X86_FEATURE_NOPL); | |
58a5aac5 | 1150 | #endif |
d7cd5611 | 1151 | } |
58a5aac5 | 1152 | |
7a5d6704 AL |
1153 | static void detect_null_seg_behavior(struct cpuinfo_x86 *c) |
1154 | { | |
1155 | #ifdef CONFIG_X86_64 | |
58a5aac5 | 1156 | /* |
7a5d6704 AL |
1157 | * Empirically, writing zero to a segment selector on AMD does |
1158 | * not clear the base, whereas writing zero to a segment | |
1159 | * selector on Intel does clear the base. Intel's behavior | |
1160 | * allows slightly faster context switches in the common case | |
1161 | * where GS is unused by the prev and next threads. | |
58a5aac5 | 1162 | * |
7a5d6704 AL |
1163 | * Since neither vendor documents this anywhere that I can see, |
1164 | * detect it directly instead of hardcoding the choice by | |
1165 | * vendor. | |
1166 | * | |
1167 | * I've designated AMD's behavior as the "bug" because it's | |
1168 | * counterintuitive and less friendly. | |
58a5aac5 | 1169 | */ |
7a5d6704 AL |
1170 | |
1171 | unsigned long old_base, tmp; | |
1172 | rdmsrl(MSR_FS_BASE, old_base); | |
1173 | wrmsrl(MSR_FS_BASE, 1); | |
1174 | loadsegment(fs, 0); | |
1175 | rdmsrl(MSR_FS_BASE, tmp); | |
1176 | if (tmp != 0) | |
1177 | set_cpu_bug(c, X86_BUG_NULL_SEG); | |
1178 | wrmsrl(MSR_FS_BASE, old_base); | |
366d4a43 | 1179 | #endif |
d7cd5611 RR |
1180 | } |
1181 | ||
148f9bb8 | 1182 | static void generic_identify(struct cpuinfo_x86 *c) |
1da177e4 | 1183 | { |
aef93c8b | 1184 | c->extended_cpuid_level = 0; |
1da177e4 | 1185 | |
3da99c97 | 1186 | if (!have_cpuid_p()) |
aef93c8b | 1187 | identify_cpu_without_cpuid(c); |
1d67953f | 1188 | |
aef93c8b | 1189 | /* cyrix could have cpuid enabled via c_identify()*/ |
a9853dd6 | 1190 | if (!have_cpuid_p()) |
aef93c8b | 1191 | return; |
1da177e4 | 1192 | |
3da99c97 | 1193 | cpu_detect(c); |
1da177e4 | 1194 | |
3da99c97 | 1195 | get_cpu_vendor(c); |
1da177e4 | 1196 | |
3da99c97 | 1197 | get_cpu_cap(c); |
1da177e4 | 1198 | |
3da99c97 YL |
1199 | if (c->cpuid_level >= 0x00000001) { |
1200 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; | |
b89d3b3e | 1201 | #ifdef CONFIG_X86_32 |
c8e56d20 | 1202 | # ifdef CONFIG_SMP |
cb8cc442 | 1203 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
b89d3b3e | 1204 | # else |
3da99c97 | 1205 | c->apicid = c->initial_apicid; |
b89d3b3e YL |
1206 | # endif |
1207 | #endif | |
b89d3b3e | 1208 | c->phys_proc_id = c->initial_apicid; |
3da99c97 | 1209 | } |
1da177e4 | 1210 | |
1b05d60d | 1211 | get_model_name(c); /* Default name */ |
1da177e4 | 1212 | |
3da99c97 | 1213 | detect_nopl(c); |
7a5d6704 AL |
1214 | |
1215 | detect_null_seg_behavior(c); | |
0230bb03 AL |
1216 | |
1217 | /* | |
1218 | * ESPFIX is a strange bug. All real CPUs have it. Paravirt | |
1219 | * systems that run Linux at CPL > 0 may or may not have the | |
1220 | * issue, but, even if they have the issue, there's absolutely | |
1221 | * nothing we can do about it because we can't use the real IRET | |
1222 | * instruction. | |
1223 | * | |
1224 | * NB: For the time being, only 32-bit kernels support | |
1225 | * X86_BUG_ESPFIX as such. 64-bit kernels directly choose | |
1226 | * whether to apply espfix using paravirt hooks. If any | |
1227 | * non-paravirt system ever shows up that does *not* have the | |
1228 | * ESPFIX issue, we can change this. | |
1229 | */ | |
1230 | #ifdef CONFIG_X86_32 | |
1231 | # ifdef CONFIG_PARAVIRT | |
1232 | do { | |
1233 | extern void native_iret(void); | |
1234 | if (pv_cpu_ops.iret == native_iret) | |
1235 | set_cpu_bug(c, X86_BUG_ESPFIX); | |
1236 | } while (0); | |
1237 | # else | |
1238 | set_cpu_bug(c, X86_BUG_ESPFIX); | |
1239 | # endif | |
1240 | #endif | |
1da177e4 | 1241 | } |
1da177e4 | 1242 | |
cbc82b17 PWJ |
1243 | static void x86_init_cache_qos(struct cpuinfo_x86 *c) |
1244 | { | |
1245 | /* | |
1246 | * The heavy lifting of max_rmid and cache_occ_scale are handled | |
1247 | * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu | |
1248 | * in case CQM bits really aren't there in this CPU. | |
1249 | */ | |
1250 | if (c != &boot_cpu_data) { | |
1251 | boot_cpu_data.x86_cache_max_rmid = | |
1252 | min(boot_cpu_data.x86_cache_max_rmid, | |
1253 | c->x86_cache_max_rmid); | |
1254 | } | |
1255 | } | |
1256 | ||
d49597fd | 1257 | /* |
9d85eb91 TG |
1258 | * Validate that ACPI/mptables have the same information about the |
1259 | * effective APIC id and update the package map. | |
d49597fd | 1260 | */ |
9d85eb91 | 1261 | static void validate_apic_and_package_id(struct cpuinfo_x86 *c) |
d49597fd TG |
1262 | { |
1263 | #ifdef CONFIG_SMP | |
9d85eb91 | 1264 | unsigned int apicid, cpu = smp_processor_id(); |
d49597fd TG |
1265 | |
1266 | apicid = apic->cpu_present_to_apicid(cpu); | |
d49597fd | 1267 | |
9d85eb91 TG |
1268 | if (apicid != c->apicid) { |
1269 | pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n", | |
d49597fd | 1270 | cpu, apicid, c->initial_apicid); |
d49597fd | 1271 | } |
9d85eb91 | 1272 | BUG_ON(topology_update_package_map(c->phys_proc_id, cpu)); |
d49597fd TG |
1273 | #else |
1274 | c->logical_proc_id = 0; | |
1275 | #endif | |
1276 | } | |
1277 | ||
1da177e4 LT |
1278 | /* |
1279 | * This does the hard work of actually picking apart the CPU stuff... | |
1280 | */ | |
148f9bb8 | 1281 | static void identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
1282 | { |
1283 | int i; | |
1284 | ||
1285 | c->loops_per_jiffy = loops_per_jiffy; | |
231d0c70 | 1286 | c->x86_cache_size = 0; |
1da177e4 | 1287 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
325cbb04 | 1288 | c->x86_model = c->x86_stepping = 0; /* So far unknown... */ |
1da177e4 LT |
1289 | c->x86_vendor_id[0] = '\0'; /* Unset */ |
1290 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 1291 | c->x86_max_cores = 1; |
102bbe3a | 1292 | c->x86_coreid_bits = 0; |
79a8b9aa | 1293 | c->cu_id = 0xff; |
11fdd252 | 1294 | #ifdef CONFIG_X86_64 |
102bbe3a | 1295 | c->x86_clflush_size = 64; |
13c6c532 JB |
1296 | c->x86_phys_bits = 36; |
1297 | c->x86_virt_bits = 48; | |
102bbe3a YL |
1298 | #else |
1299 | c->cpuid_level = -1; /* CPUID not detected */ | |
770d132f | 1300 | c->x86_clflush_size = 32; |
13c6c532 JB |
1301 | c->x86_phys_bits = 32; |
1302 | c->x86_virt_bits = 32; | |
102bbe3a YL |
1303 | #endif |
1304 | c->x86_cache_alignment = c->x86_clflush_size; | |
1da177e4 LT |
1305 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
1306 | ||
1da177e4 LT |
1307 | generic_identify(c); |
1308 | ||
3898534d | 1309 | if (this_cpu->c_identify) |
1da177e4 LT |
1310 | this_cpu->c_identify(c); |
1311 | ||
6a6256f9 | 1312 | /* Clear/Set all flags overridden by options, after probe */ |
8bf1ebca | 1313 | apply_forced_caps(c); |
2759c328 | 1314 | |
102bbe3a | 1315 | #ifdef CONFIG_X86_64 |
cb8cc442 | 1316 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
102bbe3a YL |
1317 | #endif |
1318 | ||
1da177e4 LT |
1319 | /* |
1320 | * Vendor-specific initialization. In this section we | |
1321 | * canonicalize the feature flags, meaning if there are | |
1322 | * features a certain CPU supports which CPUID doesn't | |
1323 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
1324 | * we handle them here. | |
1325 | * | |
1326 | * At the end of this section, c->x86_capability better | |
1327 | * indicate the features this CPU genuinely supports! | |
1328 | */ | |
1329 | if (this_cpu->c_init) | |
1330 | this_cpu->c_init(c); | |
1331 | ||
1332 | /* Disable the PN if appropriate */ | |
1333 | squash_the_stupid_serial_number(c); | |
1334 | ||
b2cc2a07 PA |
1335 | /* Set up SMEP/SMAP */ |
1336 | setup_smep(c); | |
1337 | setup_smap(c); | |
1338 | ||
1da177e4 | 1339 | /* |
0f3fa48a IM |
1340 | * The vendor-specific functions might have changed features. |
1341 | * Now we do "generic changes." | |
1da177e4 LT |
1342 | */ |
1343 | ||
b38b0665 PA |
1344 | /* Filter out anything that depends on CPUID levels we don't have */ |
1345 | filter_cpuid_features(c, true); | |
1346 | ||
1da177e4 | 1347 | /* If the model name is still unset, do table lookup. */ |
34048c9e | 1348 | if (!c->x86_model_id[0]) { |
02dde8b4 | 1349 | const char *p; |
1da177e4 | 1350 | p = table_lookup_model(c); |
34048c9e | 1351 | if (p) |
1da177e4 LT |
1352 | strcpy(c->x86_model_id, p); |
1353 | else | |
1354 | /* Last resort... */ | |
1355 | sprintf(c->x86_model_id, "%02x/%02x", | |
54a20f8c | 1356 | c->x86, c->x86_model); |
1da177e4 LT |
1357 | } |
1358 | ||
102bbe3a YL |
1359 | #ifdef CONFIG_X86_64 |
1360 | detect_ht(c); | |
1361 | #endif | |
1362 | ||
49d859d7 | 1363 | x86_init_rdrand(c); |
cbc82b17 | 1364 | x86_init_cache_qos(c); |
06976945 | 1365 | setup_pku(c); |
3e0c3737 YL |
1366 | |
1367 | /* | |
6a6256f9 | 1368 | * Clear/Set all flags overridden by options, need do it |
3e0c3737 YL |
1369 | * before following smp all cpus cap AND. |
1370 | */ | |
8bf1ebca | 1371 | apply_forced_caps(c); |
3e0c3737 | 1372 | |
1da177e4 LT |
1373 | /* |
1374 | * On SMP, boot_cpu_data holds the common feature set between | |
1375 | * all CPUs; so make sure that we indicate which features are | |
1376 | * common between the CPUs. The first time this routine gets | |
1377 | * executed, c == &boot_cpu_data. | |
1378 | */ | |
34048c9e | 1379 | if (c != &boot_cpu_data) { |
1da177e4 | 1380 | /* AND the already accumulated flags with these */ |
9d31d35b | 1381 | for (i = 0; i < NCAPINTS; i++) |
1da177e4 | 1382 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; |
65fc985b BP |
1383 | |
1384 | /* OR, i.e. replicate the bug flags */ | |
1385 | for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) | |
1386 | c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; | |
1da177e4 LT |
1387 | } |
1388 | ||
1389 | /* Init Machine Check Exception if available. */ | |
5e09954a | 1390 | mcheck_cpu_init(c); |
30d432df AK |
1391 | |
1392 | select_idle_routine(c); | |
102bbe3a | 1393 | |
de2d9445 | 1394 | #ifdef CONFIG_NUMA |
102bbe3a YL |
1395 | numa_add_cpu(smp_processor_id()); |
1396 | #endif | |
a6c4e076 | 1397 | } |
31ab269a | 1398 | |
8b6c0ab1 IM |
1399 | /* |
1400 | * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions | |
1401 | * on 32-bit kernels: | |
1402 | */ | |
cfda7bb9 AL |
1403 | #ifdef CONFIG_X86_32 |
1404 | void enable_sep_cpu(void) | |
1405 | { | |
8b6c0ab1 IM |
1406 | struct tss_struct *tss; |
1407 | int cpu; | |
cfda7bb9 | 1408 | |
b3edfda4 BP |
1409 | if (!boot_cpu_has(X86_FEATURE_SEP)) |
1410 | return; | |
1411 | ||
8b6c0ab1 | 1412 | cpu = get_cpu(); |
25e2999e | 1413 | tss = &per_cpu(cpu_tss_rw, cpu); |
8b6c0ab1 | 1414 | |
8b6c0ab1 | 1415 | /* |
cf9328cc AL |
1416 | * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- |
1417 | * see the big comment in struct x86_hw_tss's definition. | |
8b6c0ab1 | 1418 | */ |
cfda7bb9 AL |
1419 | |
1420 | tss->x86_tss.ss1 = __KERNEL_CS; | |
8b6c0ab1 | 1421 | wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); |
06f9acfe | 1422 | wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0); |
4c8cd0c5 | 1423 | wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); |
8b6c0ab1 | 1424 | |
cfda7bb9 AL |
1425 | put_cpu(); |
1426 | } | |
e04d645f GC |
1427 | #endif |
1428 | ||
a6c4e076 JF |
1429 | void __init identify_boot_cpu(void) |
1430 | { | |
1431 | identify_cpu(&boot_cpu_data); | |
102bbe3a | 1432 | #ifdef CONFIG_X86_32 |
a6c4e076 | 1433 | sysenter_setup(); |
6fe940d6 | 1434 | enable_sep_cpu(); |
102bbe3a | 1435 | #endif |
5b556332 | 1436 | cpu_detect_tlb(&boot_cpu_data); |
4b708ea4 | 1437 | tsx_init(); |
a6c4e076 | 1438 | } |
3b520b23 | 1439 | |
148f9bb8 | 1440 | void identify_secondary_cpu(struct cpuinfo_x86 *c) |
a6c4e076 JF |
1441 | { |
1442 | BUG_ON(c == &boot_cpu_data); | |
1443 | identify_cpu(c); | |
102bbe3a | 1444 | #ifdef CONFIG_X86_32 |
a6c4e076 | 1445 | enable_sep_cpu(); |
102bbe3a | 1446 | #endif |
a6c4e076 | 1447 | mtrr_ap_init(); |
9d85eb91 | 1448 | validate_apic_and_package_id(c); |
128e6990 | 1449 | x86_spec_ctrl_setup_ap(); |
1da177e4 LT |
1450 | } |
1451 | ||
191679fd AK |
1452 | static __init int setup_noclflush(char *arg) |
1453 | { | |
840d2830 | 1454 | setup_clear_cpu_cap(X86_FEATURE_CLFLUSH); |
da4aaa7d | 1455 | setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT); |
191679fd AK |
1456 | return 1; |
1457 | } | |
1458 | __setup("noclflush", setup_noclflush); | |
1459 | ||
148f9bb8 | 1460 | void print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 | 1461 | { |
02dde8b4 | 1462 | const char *vendor = NULL; |
1da177e4 | 1463 | |
0f3fa48a | 1464 | if (c->x86_vendor < X86_VENDOR_NUM) { |
1da177e4 | 1465 | vendor = this_cpu->c_vendor; |
0f3fa48a IM |
1466 | } else { |
1467 | if (c->cpuid_level >= 0) | |
1468 | vendor = c->x86_vendor_id; | |
1469 | } | |
1da177e4 | 1470 | |
bd32a8cf | 1471 | if (vendor && !strstr(c->x86_model_id, vendor)) |
1b74dde7 | 1472 | pr_cont("%s ", vendor); |
1da177e4 | 1473 | |
9d31d35b | 1474 | if (c->x86_model_id[0]) |
1b74dde7 | 1475 | pr_cont("%s", c->x86_model_id); |
1da177e4 | 1476 | else |
1b74dde7 | 1477 | pr_cont("%d86", c->x86); |
1da177e4 | 1478 | |
1b74dde7 | 1479 | pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model); |
924e101a | 1480 | |
325cbb04 JZ |
1481 | if (c->x86_stepping || c->cpuid_level >= 0) |
1482 | pr_cont(", stepping: 0x%x)\n", c->x86_stepping); | |
1da177e4 | 1483 | else |
1b74dde7 | 1484 | pr_cont(")\n"); |
1da177e4 LT |
1485 | } |
1486 | ||
f01d7efa AK |
1487 | /* |
1488 | * clearcpuid= was already parsed in fpu__init_parse_early_param. | |
1489 | * But we need to keep a dummy __setup around otherwise it would | |
1490 | * show up as an environment variable for init. | |
1491 | */ | |
1492 | static __init int setup_clearcpuid(char *arg) | |
ac72e788 | 1493 | { |
ac72e788 AK |
1494 | return 1; |
1495 | } | |
f01d7efa | 1496 | __setup("clearcpuid=", setup_clearcpuid); |
ac72e788 | 1497 | |
d5494d4f | 1498 | #ifdef CONFIG_X86_64 |
947e76cd | 1499 | DEFINE_PER_CPU_FIRST(union irq_stack_union, |
277d5b40 | 1500 | irq_stack_union) __aligned(PAGE_SIZE) __visible; |
0f3fa48a | 1501 | |
bdf977b3 | 1502 | /* |
a7fcf28d AL |
1503 | * The following percpu variables are hot. Align current_task to |
1504 | * cacheline size such that they fall in the same cacheline. | |
bdf977b3 TH |
1505 | */ |
1506 | DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = | |
1507 | &init_task; | |
1508 | EXPORT_PER_CPU_SYMBOL(current_task); | |
d5494d4f | 1509 | |
bdf977b3 | 1510 | DEFINE_PER_CPU(char *, irq_stack_ptr) = |
4950d6d4 | 1511 | init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE; |
bdf977b3 | 1512 | |
277d5b40 | 1513 | DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1; |
d5494d4f | 1514 | |
c2daa3be PZ |
1515 | DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; |
1516 | EXPORT_PER_CPU_SYMBOL(__preempt_count); | |
1517 | ||
d5494d4f YL |
1518 | /* May not be marked __init: used by software suspend */ |
1519 | void syscall_init(void) | |
1da177e4 | 1520 | { |
c631a16e AL |
1521 | extern char _entry_trampoline[]; |
1522 | extern char entry_SYSCALL_64_trampoline[]; | |
1523 | ||
5bb40c6d | 1524 | int cpu = smp_processor_id(); |
c631a16e AL |
1525 | unsigned long SYSCALL64_entry_trampoline = |
1526 | (unsigned long)get_cpu_entry_area(cpu)->entry_trampoline + | |
1527 | (entry_SYSCALL_64_trampoline - _entry_trampoline); | |
5bb40c6d | 1528 | |
31ac34ca | 1529 | wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); |
35531133 TG |
1530 | if (static_cpu_has(X86_FEATURE_PTI)) |
1531 | wrmsrl(MSR_LSTAR, SYSCALL64_entry_trampoline); | |
1532 | else | |
1533 | wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); | |
d56fe4bf IM |
1534 | |
1535 | #ifdef CONFIG_IA32_EMULATION | |
47edb651 | 1536 | wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat); |
a76c7f46 | 1537 | /* |
487d1edb DV |
1538 | * This only works on Intel CPUs. |
1539 | * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. | |
1540 | * This does not cause SYSENTER to jump to the wrong location, because | |
1541 | * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). | |
a76c7f46 DV |
1542 | */ |
1543 | wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); | |
06f9acfe | 1544 | wrmsrl_safe(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1)); |
4c8cd0c5 | 1545 | wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); |
d56fe4bf | 1546 | #else |
47edb651 | 1547 | wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret); |
6b51311c | 1548 | wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); |
d56fe4bf IM |
1549 | wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); |
1550 | wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); | |
d5494d4f | 1551 | #endif |
03ae5768 | 1552 | |
d5494d4f YL |
1553 | /* Flags to clear on syscall */ |
1554 | wrmsrl(MSR_SYSCALL_MASK, | |
63bcff2a | 1555 | X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF| |
8c7aa698 | 1556 | X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT); |
1da177e4 | 1557 | } |
62111195 | 1558 | |
d5494d4f YL |
1559 | /* |
1560 | * Copies of the original ist values from the tss are only accessed during | |
1561 | * debugging, no special alignment required. | |
1562 | */ | |
1563 | DEFINE_PER_CPU(struct orig_ist, orig_ist); | |
1564 | ||
228bdaa9 | 1565 | static DEFINE_PER_CPU(unsigned long, debug_stack_addr); |
42181186 | 1566 | DEFINE_PER_CPU(int, debug_stack_usage); |
228bdaa9 SR |
1567 | |
1568 | int is_debug_stack(unsigned long addr) | |
1569 | { | |
89cbc767 CL |
1570 | return __this_cpu_read(debug_stack_usage) || |
1571 | (addr <= __this_cpu_read(debug_stack_addr) && | |
1572 | addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ)); | |
228bdaa9 | 1573 | } |
0f46efeb | 1574 | NOKPROBE_SYMBOL(is_debug_stack); |
228bdaa9 | 1575 | |
629f4f9d | 1576 | DEFINE_PER_CPU(u32, debug_idt_ctr); |
f8988175 | 1577 | |
228bdaa9 SR |
1578 | void debug_stack_set_zero(void) |
1579 | { | |
629f4f9d SA |
1580 | this_cpu_inc(debug_idt_ctr); |
1581 | load_current_idt(); | |
228bdaa9 | 1582 | } |
0f46efeb | 1583 | NOKPROBE_SYMBOL(debug_stack_set_zero); |
228bdaa9 SR |
1584 | |
1585 | void debug_stack_reset(void) | |
1586 | { | |
629f4f9d | 1587 | if (WARN_ON(!this_cpu_read(debug_idt_ctr))) |
f8988175 | 1588 | return; |
629f4f9d SA |
1589 | if (this_cpu_dec_return(debug_idt_ctr) == 0) |
1590 | load_current_idt(); | |
228bdaa9 | 1591 | } |
0f46efeb | 1592 | NOKPROBE_SYMBOL(debug_stack_reset); |
228bdaa9 | 1593 | |
0f3fa48a | 1594 | #else /* CONFIG_X86_64 */ |
d5494d4f | 1595 | |
bdf977b3 TH |
1596 | DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; |
1597 | EXPORT_PER_CPU_SYMBOL(current_task); | |
c2daa3be PZ |
1598 | DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; |
1599 | EXPORT_PER_CPU_SYMBOL(__preempt_count); | |
bdf977b3 | 1600 | |
a7fcf28d AL |
1601 | /* |
1602 | * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find | |
1603 | * the top of the kernel stack. Use an extra percpu variable to track the | |
1604 | * top of the kernel stack directly. | |
1605 | */ | |
1606 | DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = | |
1607 | (unsigned long)&init_thread_union + THREAD_SIZE; | |
1608 | EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack); | |
1609 | ||
60a5317f | 1610 | #ifdef CONFIG_CC_STACKPROTECTOR |
53f82452 | 1611 | DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); |
60a5317f | 1612 | #endif |
d5494d4f | 1613 | |
0f3fa48a | 1614 | #endif /* CONFIG_X86_64 */ |
c5413fbe | 1615 | |
9766cdbc JSR |
1616 | /* |
1617 | * Clear all 6 debug registers: | |
1618 | */ | |
1619 | static void clear_all_debug_regs(void) | |
1620 | { | |
1621 | int i; | |
1622 | ||
1623 | for (i = 0; i < 8; i++) { | |
1624 | /* Ignore db4, db5 */ | |
1625 | if ((i == 4) || (i == 5)) | |
1626 | continue; | |
1627 | ||
1628 | set_debugreg(0, i); | |
1629 | } | |
1630 | } | |
c5413fbe | 1631 | |
0bb9fef9 JW |
1632 | #ifdef CONFIG_KGDB |
1633 | /* | |
1634 | * Restore debug regs if using kgdbwait and you have a kernel debugger | |
1635 | * connection established. | |
1636 | */ | |
1637 | static void dbg_restore_debug_regs(void) | |
1638 | { | |
1639 | if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) | |
1640 | arch_kgdb_ops.correct_hw_break(); | |
1641 | } | |
1642 | #else /* ! CONFIG_KGDB */ | |
1643 | #define dbg_restore_debug_regs() | |
1644 | #endif /* ! CONFIG_KGDB */ | |
1645 | ||
ce4b1b16 IM |
1646 | static void wait_for_master_cpu(int cpu) |
1647 | { | |
1648 | #ifdef CONFIG_SMP | |
1649 | /* | |
1650 | * wait for ACK from master CPU before continuing | |
1651 | * with AP initialization | |
1652 | */ | |
1653 | WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)); | |
1654 | while (!cpumask_test_cpu(cpu, cpu_callout_mask)) | |
1655 | cpu_relax(); | |
1656 | #endif | |
1657 | } | |
1658 | ||
d2cbcc49 RR |
1659 | /* |
1660 | * cpu_init() initializes state that is per-CPU. Some data is already | |
1661 | * initialized (naturally) in the bootstrap process, such as the GDT | |
1662 | * and IDT. We reload them nevertheless, this function acts as a | |
1663 | * 'CPU state barrier', nothing should get across. | |
1ba76586 | 1664 | * A lot of state is already set up in PDA init for 64 bit |
d2cbcc49 | 1665 | */ |
1ba76586 | 1666 | #ifdef CONFIG_X86_64 |
0f3fa48a | 1667 | |
148f9bb8 | 1668 | void cpu_init(void) |
1ba76586 | 1669 | { |
0fe1e009 | 1670 | struct orig_ist *oist; |
1ba76586 | 1671 | struct task_struct *me; |
0f3fa48a IM |
1672 | struct tss_struct *t; |
1673 | unsigned long v; | |
fb59831b | 1674 | int cpu = raw_smp_processor_id(); |
1ba76586 YL |
1675 | int i; |
1676 | ||
ce4b1b16 IM |
1677 | wait_for_master_cpu(cpu); |
1678 | ||
1e02ce4c AL |
1679 | /* |
1680 | * Initialize the CR4 shadow before doing anything that could | |
1681 | * try to read it. | |
1682 | */ | |
1683 | cr4_init_shadow(); | |
1684 | ||
777284b6 BP |
1685 | if (cpu) |
1686 | load_ucode_ap(); | |
e6ebf5de | 1687 | |
25e2999e | 1688 | t = &per_cpu(cpu_tss_rw, cpu); |
0fe1e009 | 1689 | oist = &per_cpu(orig_ist, cpu); |
0f3fa48a | 1690 | |
e7a22c1e | 1691 | #ifdef CONFIG_NUMA |
27fd185f | 1692 | if (this_cpu_read(numa_node) == 0 && |
e534c7c5 LS |
1693 | early_cpu_to_node(cpu) != NUMA_NO_NODE) |
1694 | set_numa_node(early_cpu_to_node(cpu)); | |
e7a22c1e | 1695 | #endif |
1ba76586 YL |
1696 | |
1697 | me = current; | |
1698 | ||
2eaad1fd | 1699 | pr_debug("Initializing CPU#%d\n", cpu); |
1ba76586 | 1700 | |
375074cc | 1701 | cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); |
1ba76586 YL |
1702 | |
1703 | /* | |
1704 | * Initialize the per-CPU GDT with the boot GDT, | |
1705 | * and set up the GDT descriptor: | |
1706 | */ | |
1707 | ||
552be871 | 1708 | switch_to_new_gdt(cpu); |
2697fbd5 BG |
1709 | loadsegment(fs, 0); |
1710 | ||
cf910e83 | 1711 | load_current_idt(); |
1ba76586 YL |
1712 | |
1713 | memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); | |
1714 | syscall_init(); | |
1715 | ||
1716 | wrmsrl(MSR_FS_BASE, 0); | |
1717 | wrmsrl(MSR_KERNEL_GS_BASE, 0); | |
1718 | barrier(); | |
1719 | ||
4763ed4d | 1720 | x86_configure_nx(); |
659006bf | 1721 | x2apic_setup(); |
1ba76586 YL |
1722 | |
1723 | /* | |
1724 | * set up and load the per-CPU TSS | |
1725 | */ | |
0fe1e009 | 1726 | if (!oist->ist[0]) { |
bb568391 | 1727 | char *estacks = get_cpu_entry_area(cpu)->exception_stacks; |
0f3fa48a | 1728 | |
1ba76586 | 1729 | for (v = 0; v < N_EXCEPTION_STACKS; v++) { |
0f3fa48a | 1730 | estacks += exception_stack_sizes[v]; |
0fe1e009 | 1731 | oist->ist[v] = t->x86_tss.ist[v] = |
1ba76586 | 1732 | (unsigned long)estacks; |
228bdaa9 SR |
1733 | if (v == DEBUG_STACK-1) |
1734 | per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks; | |
1ba76586 YL |
1735 | } |
1736 | } | |
1737 | ||
5be13695 | 1738 | t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET; |
0f3fa48a | 1739 | |
1ba76586 YL |
1740 | /* |
1741 | * <= is required because the CPU will access up to | |
1742 | * 8 bits beyond the end of the IO permission bitmap. | |
1743 | */ | |
1744 | for (i = 0; i <= IO_BITMAP_LONGS; i++) | |
1745 | t->io_bitmap[i] = ~0UL; | |
1746 | ||
f1f10076 | 1747 | mmgrab(&init_mm); |
1ba76586 | 1748 | me->active_mm = &init_mm; |
8c5dfd25 | 1749 | BUG_ON(me->mm); |
72c0098d | 1750 | initialize_tlbstate_and_flush(); |
1ba76586 YL |
1751 | enter_lazy_tlb(&init_mm, me); |
1752 | ||
71d7244e | 1753 | /* |
2bc9fa0b AL |
1754 | * Initialize the TSS. sp0 points to the entry trampoline stack |
1755 | * regardless of what task is running. | |
71d7244e | 1756 | */ |
5bb40c6d | 1757 | set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); |
1ba76586 | 1758 | load_TR_desc(); |
06f9acfe | 1759 | load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1)); |
71d7244e | 1760 | |
37868fe1 | 1761 | load_mm_ldt(&init_mm); |
1ba76586 | 1762 | |
0bb9fef9 JW |
1763 | clear_all_debug_regs(); |
1764 | dbg_restore_debug_regs(); | |
1ba76586 | 1765 | |
21c4cd10 | 1766 | fpu__init_cpu(); |
1ba76586 | 1767 | |
1ba76586 YL |
1768 | if (is_uv_system()) |
1769 | uv_cpu_init(); | |
69218e47 | 1770 | |
69218e47 | 1771 | load_fixmap_gdt(cpu); |
1ba76586 YL |
1772 | } |
1773 | ||
1774 | #else | |
1775 | ||
148f9bb8 | 1776 | void cpu_init(void) |
9ee79a3d | 1777 | { |
d2cbcc49 RR |
1778 | int cpu = smp_processor_id(); |
1779 | struct task_struct *curr = current; | |
25e2999e | 1780 | struct tss_struct *t = &per_cpu(cpu_tss_rw, cpu); |
62111195 | 1781 | |
ce4b1b16 | 1782 | wait_for_master_cpu(cpu); |
e6ebf5de | 1783 | |
5b2bdbc8 SR |
1784 | /* |
1785 | * Initialize the CR4 shadow before doing anything that could | |
1786 | * try to read it. | |
1787 | */ | |
1788 | cr4_init_shadow(); | |
1789 | ||
ce4b1b16 | 1790 | show_ucode_info_early(); |
62111195 | 1791 | |
1b74dde7 | 1792 | pr_info("Initializing CPU#%d\n", cpu); |
62111195 | 1793 | |
362f924b | 1794 | if (cpu_feature_enabled(X86_FEATURE_VME) || |
59e21e3d | 1795 | boot_cpu_has(X86_FEATURE_TSC) || |
362f924b | 1796 | boot_cpu_has(X86_FEATURE_DE)) |
375074cc | 1797 | cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); |
62111195 | 1798 | |
cf910e83 | 1799 | load_current_idt(); |
552be871 | 1800 | switch_to_new_gdt(cpu); |
1da177e4 | 1801 | |
1da177e4 LT |
1802 | /* |
1803 | * Set up and load the per-CPU TSS and LDT | |
1804 | */ | |
f1f10076 | 1805 | mmgrab(&init_mm); |
62111195 | 1806 | curr->active_mm = &init_mm; |
8c5dfd25 | 1807 | BUG_ON(curr->mm); |
72c0098d | 1808 | initialize_tlbstate_and_flush(); |
62111195 | 1809 | enter_lazy_tlb(&init_mm, curr); |
1da177e4 | 1810 | |
71d7244e AL |
1811 | /* |
1812 | * Initialize the TSS. Don't bother initializing sp0, as the initial | |
1813 | * task never enters user mode. | |
1814 | */ | |
5bb40c6d | 1815 | set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); |
1da177e4 | 1816 | load_TR_desc(); |
71d7244e | 1817 | |
37868fe1 | 1818 | load_mm_ldt(&init_mm); |
1da177e4 | 1819 | |
5be13695 | 1820 | t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET; |
f9a196b8 | 1821 | |
22c4e308 | 1822 | #ifdef CONFIG_DOUBLEFAULT |
1da177e4 LT |
1823 | /* Set up doublefault TSS pointer in the GDT */ |
1824 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
22c4e308 | 1825 | #endif |
1da177e4 | 1826 | |
9766cdbc | 1827 | clear_all_debug_regs(); |
0bb9fef9 | 1828 | dbg_restore_debug_regs(); |
1da177e4 | 1829 | |
21c4cd10 | 1830 | fpu__init_cpu(); |
69218e47 | 1831 | |
69218e47 | 1832 | load_fixmap_gdt(cpu); |
1da177e4 | 1833 | } |
1ba76586 | 1834 | #endif |
5700f743 | 1835 | |
b51ef52d LA |
1836 | static void bsp_resume(void) |
1837 | { | |
1838 | if (this_cpu->c_bsp_resume) | |
1839 | this_cpu->c_bsp_resume(&boot_cpu_data); | |
1840 | } | |
1841 | ||
1842 | static struct syscore_ops cpu_syscore_ops = { | |
1843 | .resume = bsp_resume, | |
1844 | }; | |
1845 | ||
1846 | static int __init init_cpu_syscore(void) | |
1847 | { | |
1848 | register_syscore_ops(&cpu_syscore_ops); | |
1849 | return 0; | |
1850 | } | |
1851 | core_initcall(init_cpu_syscore); | |
00ba4bcf BP |
1852 | |
1853 | /* | |
1854 | * The microcode loader calls this upon late microcode load to recheck features, | |
1855 | * only when microcode has been updated. Caller holds microcode_mutex and CPU | |
1856 | * hotplug lock. | |
1857 | */ | |
1858 | void microcode_check(void) | |
1859 | { | |
35da0d50 BP |
1860 | struct cpuinfo_x86 info; |
1861 | ||
00ba4bcf | 1862 | perf_check_microcode(); |
35da0d50 BP |
1863 | |
1864 | /* Reload CPUID max function as it might've changed. */ | |
1865 | info.cpuid_level = cpuid_eax(0); | |
1866 | ||
1867 | /* | |
1868 | * Copy all capability leafs to pick up the synthetic ones so that | |
1869 | * memcmp() below doesn't fail on that. The ones coming from CPUID will | |
1870 | * get overwritten in get_cpu_cap(). | |
1871 | */ | |
1872 | memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability)); | |
1873 | ||
1874 | get_cpu_cap(&info); | |
1875 | ||
1876 | if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability))) | |
1877 | return; | |
1878 | ||
1879 | pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n"); | |
1880 | pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n"); | |
00ba4bcf | 1881 | } |