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Commit | Line | Data |
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457c8996 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
2458e53f KS |
2 | /* cpu_feature_enabled() cannot be used this early */ |
3 | #define USE_EARLY_PGTABLE_L5 | |
4 | ||
57c8a661 | 5 | #include <linux/memblock.h> |
9766cdbc | 6 | #include <linux/linkage.h> |
f0fc4aff | 7 | #include <linux/bitops.h> |
9766cdbc | 8 | #include <linux/kernel.h> |
186f4360 | 9 | #include <linux/export.h> |
9766cdbc JSR |
10 | #include <linux/percpu.h> |
11 | #include <linux/string.h> | |
ee098e1a | 12 | #include <linux/ctype.h> |
1da177e4 | 13 | #include <linux/delay.h> |
68e21be2 | 14 | #include <linux/sched/mm.h> |
e6017571 | 15 | #include <linux/sched/clock.h> |
9164bb4a | 16 | #include <linux/sched/task.h> |
b47a3698 | 17 | #include <linux/sched/smt.h> |
9766cdbc | 18 | #include <linux/init.h> |
0f46efeb | 19 | #include <linux/kprobes.h> |
9766cdbc | 20 | #include <linux/kgdb.h> |
1da177e4 | 21 | #include <linux/smp.h> |
9766cdbc | 22 | #include <linux/io.h> |
b51ef52d | 23 | #include <linux/syscore_ops.h> |
65fddcfc | 24 | #include <linux/pgtable.h> |
9766cdbc | 25 | |
1ef5423a | 26 | #include <asm/cmdline.h> |
9766cdbc | 27 | #include <asm/stackprotector.h> |
cdd6c482 | 28 | #include <asm/perf_event.h> |
1da177e4 | 29 | #include <asm/mmu_context.h> |
dc4e0021 | 30 | #include <asm/doublefault.h> |
49d859d7 | 31 | #include <asm/archrandom.h> |
9766cdbc JSR |
32 | #include <asm/hypervisor.h> |
33 | #include <asm/processor.h> | |
1e02ce4c | 34 | #include <asm/tlbflush.h> |
f649e938 | 35 | #include <asm/debugreg.h> |
9766cdbc | 36 | #include <asm/sections.h> |
f40c3300 | 37 | #include <asm/vsyscall.h> |
8bdbd962 AC |
38 | #include <linux/topology.h> |
39 | #include <linux/cpumask.h> | |
60063497 | 40 | #include <linux/atomic.h> |
9766cdbc JSR |
41 | #include <asm/proto.h> |
42 | #include <asm/setup.h> | |
43 | #include <asm/apic.h> | |
44 | #include <asm/desc.h> | |
b56d2795 | 45 | #include <asm/fpu/api.h> |
27b07da7 | 46 | #include <asm/mtrr.h> |
0274f955 | 47 | #include <asm/hwcap2.h> |
8bdbd962 | 48 | #include <linux/numa.h> |
0cd39f46 | 49 | #include <asm/numa.h> |
9766cdbc | 50 | #include <asm/asm.h> |
0f6ff2bc | 51 | #include <asm/bugs.h> |
9766cdbc | 52 | #include <asm/cpu.h> |
a03a3e28 | 53 | #include <asm/mce.h> |
9766cdbc | 54 | #include <asm/msr.h> |
eb243d1d | 55 | #include <asm/memtype.h> |
d288e1cf FY |
56 | #include <asm/microcode.h> |
57 | #include <asm/microcode_intel.h> | |
fec9434a DW |
58 | #include <asm/intel-family.h> |
59 | #include <asm/cpu_device_id.h> | |
bdbcdd48 | 60 | #include <asm/uv/uv.h> |
939ef713 | 61 | #include <asm/sigframe.h> |
1da177e4 LT |
62 | |
63 | #include "cpu.h" | |
64 | ||
0274f955 GA |
65 | u32 elf_hwcap2 __read_mostly; |
66 | ||
c2d1cec1 | 67 | /* all of these masks are initialized in setup_cpu_local_masks() */ |
c2d1cec1 | 68 | cpumask_var_t cpu_initialized_mask; |
9766cdbc JSR |
69 | cpumask_var_t cpu_callout_mask; |
70 | cpumask_var_t cpu_callin_mask; | |
c2d1cec1 MT |
71 | |
72 | /* representing cpus for which sibling maps can be computed */ | |
73 | cpumask_var_t cpu_sibling_setup_mask; | |
74 | ||
f8b64d08 BP |
75 | /* Number of siblings per CPU package */ |
76 | int smp_num_siblings = 1; | |
77 | EXPORT_SYMBOL(smp_num_siblings); | |
78 | ||
79 | /* Last level cache ID of each logical CPU */ | |
80 | DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; | |
81 | ||
9164d949 KP |
82 | u16 get_llc_id(unsigned int cpu) |
83 | { | |
84 | return per_cpu(cpu_llc_id, cpu); | |
85 | } | |
86 | EXPORT_SYMBOL_GPL(get_llc_id); | |
87 | ||
66558b73 TC |
88 | /* L2 cache ID of each logical CPU */ |
89 | DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_l2c_id) = BAD_APICID; | |
90 | ||
0dcab41d TL |
91 | static struct ppin_info { |
92 | int feature; | |
93 | int msr_ppin_ctl; | |
94 | } ppin_info[] = { | |
95 | [X86_VENDOR_INTEL] = { | |
96 | .feature = X86_FEATURE_INTEL_PPIN, | |
97 | .msr_ppin_ctl = MSR_PPIN_CTL, | |
98 | }, | |
99 | [X86_VENDOR_AMD] = { | |
100 | .feature = X86_FEATURE_AMD_PPIN, | |
101 | .msr_ppin_ctl = MSR_AMD_PPIN_CTL, | |
102 | }, | |
103 | }; | |
104 | ||
105 | static const struct x86_cpu_id ppin_cpuids[] = { | |
106 | X86_MATCH_FEATURE(X86_FEATURE_AMD_PPIN, &ppin_info[X86_VENDOR_AMD]), | |
107 | ||
108 | /* Legacy models without CPUID enumeration */ | |
109 | X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE_X, &ppin_info[X86_VENDOR_INTEL]), | |
110 | X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, &ppin_info[X86_VENDOR_INTEL]), | |
111 | X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_D, &ppin_info[X86_VENDOR_INTEL]), | |
112 | X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, &ppin_info[X86_VENDOR_INTEL]), | |
113 | X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, &ppin_info[X86_VENDOR_INTEL]), | |
114 | X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, &ppin_info[X86_VENDOR_INTEL]), | |
115 | X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, &ppin_info[X86_VENDOR_INTEL]), | |
116 | X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, &ppin_info[X86_VENDOR_INTEL]), | |
117 | X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL, &ppin_info[X86_VENDOR_INTEL]), | |
118 | X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM, &ppin_info[X86_VENDOR_INTEL]), | |
119 | ||
120 | {} | |
121 | }; | |
122 | ||
123 | static void ppin_init(struct cpuinfo_x86 *c) | |
124 | { | |
125 | const struct x86_cpu_id *id; | |
126 | unsigned long long val; | |
127 | struct ppin_info *info; | |
128 | ||
129 | id = x86_match_cpu(ppin_cpuids); | |
130 | if (!id) | |
131 | return; | |
132 | ||
133 | /* | |
134 | * Testing the presence of the MSR is not enough. Need to check | |
135 | * that the PPIN_CTL allows reading of the PPIN. | |
136 | */ | |
137 | info = (struct ppin_info *)id->driver_data; | |
138 | ||
139 | if (rdmsrl_safe(info->msr_ppin_ctl, &val)) | |
140 | goto clear_ppin; | |
141 | ||
142 | if ((val & 3UL) == 1UL) { | |
143 | /* PPIN locked in disabled mode */ | |
144 | goto clear_ppin; | |
145 | } | |
146 | ||
147 | /* If PPIN is disabled, try to enable */ | |
148 | if (!(val & 2UL)) { | |
149 | wrmsrl_safe(info->msr_ppin_ctl, val | 2UL); | |
150 | rdmsrl_safe(info->msr_ppin_ctl, &val); | |
151 | } | |
152 | ||
153 | /* Is the enable bit set? */ | |
154 | if (val & 2UL) { | |
155 | set_cpu_cap(c, info->feature); | |
156 | return; | |
157 | } | |
158 | ||
159 | clear_ppin: | |
160 | clear_cpu_cap(c, info->feature); | |
161 | } | |
162 | ||
2f2f52ba | 163 | /* correctly size the local cpu masks */ |
4369f1fb | 164 | void __init setup_cpu_local_masks(void) |
2f2f52ba BG |
165 | { |
166 | alloc_bootmem_cpumask_var(&cpu_initialized_mask); | |
167 | alloc_bootmem_cpumask_var(&cpu_callin_mask); | |
168 | alloc_bootmem_cpumask_var(&cpu_callout_mask); | |
169 | alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); | |
170 | } | |
171 | ||
148f9bb8 | 172 | static void default_init(struct cpuinfo_x86 *c) |
e8055139 OZ |
173 | { |
174 | #ifdef CONFIG_X86_64 | |
27c13ece | 175 | cpu_detect_cache_sizes(c); |
e8055139 OZ |
176 | #else |
177 | /* Not much we can do here... */ | |
178 | /* Check if at least it has cpuid */ | |
179 | if (c->cpuid_level == -1) { | |
180 | /* No cpuid. It must be an ancient CPU */ | |
181 | if (c->x86 == 4) | |
182 | strcpy(c->x86_model_id, "486"); | |
183 | else if (c->x86 == 3) | |
184 | strcpy(c->x86_model_id, "386"); | |
185 | } | |
186 | #endif | |
187 | } | |
188 | ||
148f9bb8 | 189 | static const struct cpu_dev default_cpu = { |
e8055139 OZ |
190 | .c_init = default_init, |
191 | .c_vendor = "Unknown", | |
192 | .c_x86_vendor = X86_VENDOR_UNKNOWN, | |
193 | }; | |
194 | ||
148f9bb8 | 195 | static const struct cpu_dev *this_cpu = &default_cpu; |
0a488a53 | 196 | |
06deef89 | 197 | DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { |
950ad7ff | 198 | #ifdef CONFIG_X86_64 |
06deef89 BG |
199 | /* |
200 | * We need valid kernel segments for data and code in long mode too | |
201 | * IRET will check the segment types kkeil 2000/10/28 | |
202 | * Also sysret mandates a special GDT layout | |
203 | * | |
9766cdbc | 204 | * TLS descriptors are currently at a different place compared to i386. |
06deef89 BG |
205 | * Hopefully nobody expects them at a fixed place (Wine?) |
206 | */ | |
1e5de182 AM |
207 | [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), |
208 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), | |
209 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), | |
210 | [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), | |
211 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), | |
212 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), | |
950ad7ff | 213 | #else |
1e5de182 AM |
214 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), |
215 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
216 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), | |
217 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), | |
bf504672 RR |
218 | /* |
219 | * Segments used for calling PnP BIOS have byte granularity. | |
220 | * They code segments and data segments have fixed 64k limits, | |
221 | * the transfer segment sizes are set at run time. | |
222 | */ | |
6842ef0e | 223 | /* 32-bit code */ |
1e5de182 | 224 | [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), |
6842ef0e | 225 | /* 16-bit code */ |
1e5de182 | 226 | [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), |
6842ef0e | 227 | /* 16-bit data */ |
1e5de182 | 228 | [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), |
6842ef0e | 229 | /* 16-bit data */ |
1e5de182 | 230 | [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), |
6842ef0e | 231 | /* 16-bit data */ |
1e5de182 | 232 | [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), |
bf504672 RR |
233 | /* |
234 | * The APM segments have byte granularity and their bases | |
235 | * are set at run time. All have 64k limits. | |
236 | */ | |
6842ef0e | 237 | /* 32-bit code */ |
1e5de182 | 238 | [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), |
bf504672 | 239 | /* 16-bit code */ |
1e5de182 | 240 | [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), |
6842ef0e | 241 | /* data */ |
72c4d853 | 242 | [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), |
bf504672 | 243 | |
1e5de182 AM |
244 | [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), |
245 | [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
950ad7ff | 246 | #endif |
06deef89 | 247 | } }; |
7a61d35d | 248 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); |
ae1ee11b | 249 | |
0790c9aa | 250 | #ifdef CONFIG_X86_64 |
c7ad5ad2 | 251 | static int __init x86_nopcid_setup(char *s) |
0790c9aa | 252 | { |
c7ad5ad2 AL |
253 | /* nopcid doesn't accept parameters */ |
254 | if (s) | |
255 | return -EINVAL; | |
0790c9aa AL |
256 | |
257 | /* do not emit a message if the feature is not present */ | |
258 | if (!boot_cpu_has(X86_FEATURE_PCID)) | |
c7ad5ad2 | 259 | return 0; |
0790c9aa AL |
260 | |
261 | setup_clear_cpu_cap(X86_FEATURE_PCID); | |
262 | pr_info("nopcid: PCID feature disabled\n"); | |
c7ad5ad2 | 263 | return 0; |
0790c9aa | 264 | } |
c7ad5ad2 | 265 | early_param("nopcid", x86_nopcid_setup); |
0790c9aa AL |
266 | #endif |
267 | ||
d12a72b8 AL |
268 | static int __init x86_noinvpcid_setup(char *s) |
269 | { | |
270 | /* noinvpcid doesn't accept parameters */ | |
271 | if (s) | |
272 | return -EINVAL; | |
273 | ||
274 | /* do not emit a message if the feature is not present */ | |
275 | if (!boot_cpu_has(X86_FEATURE_INVPCID)) | |
276 | return 0; | |
277 | ||
278 | setup_clear_cpu_cap(X86_FEATURE_INVPCID); | |
279 | pr_info("noinvpcid: INVPCID feature disabled\n"); | |
280 | return 0; | |
281 | } | |
282 | early_param("noinvpcid", x86_noinvpcid_setup); | |
283 | ||
ba51dced | 284 | #ifdef CONFIG_X86_32 |
148f9bb8 PG |
285 | static int cachesize_override = -1; |
286 | static int disable_x86_serial_nr = 1; | |
1da177e4 | 287 | |
0a488a53 YL |
288 | static int __init cachesize_setup(char *str) |
289 | { | |
290 | get_option(&str, &cachesize_override); | |
291 | return 1; | |
292 | } | |
293 | __setup("cachesize=", cachesize_setup); | |
294 | ||
0a488a53 YL |
295 | static int __init x86_sep_setup(char *s) |
296 | { | |
297 | setup_clear_cpu_cap(X86_FEATURE_SEP); | |
298 | return 1; | |
299 | } | |
300 | __setup("nosep", x86_sep_setup); | |
301 | ||
302 | /* Standard macro to see if a specific flag is changeable */ | |
303 | static inline int flag_is_changeable_p(u32 flag) | |
304 | { | |
305 | u32 f1, f2; | |
306 | ||
94f6bac1 KH |
307 | /* |
308 | * Cyrix and IDT cpus allow disabling of CPUID | |
309 | * so the code below may return different results | |
310 | * when it is executed before and after enabling | |
311 | * the CPUID. Add "volatile" to not allow gcc to | |
312 | * optimize the subsequent calls to this function. | |
313 | */ | |
0f3fa48a IM |
314 | asm volatile ("pushfl \n\t" |
315 | "pushfl \n\t" | |
316 | "popl %0 \n\t" | |
317 | "movl %0, %1 \n\t" | |
318 | "xorl %2, %0 \n\t" | |
319 | "pushl %0 \n\t" | |
320 | "popfl \n\t" | |
321 | "pushfl \n\t" | |
322 | "popl %0 \n\t" | |
323 | "popfl \n\t" | |
324 | ||
94f6bac1 KH |
325 | : "=&r" (f1), "=&r" (f2) |
326 | : "ir" (flag)); | |
0a488a53 YL |
327 | |
328 | return ((f1^f2) & flag) != 0; | |
329 | } | |
330 | ||
331 | /* Probe for the CPUID instruction */ | |
148f9bb8 | 332 | int have_cpuid_p(void) |
0a488a53 YL |
333 | { |
334 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
335 | } | |
336 | ||
148f9bb8 | 337 | static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
0a488a53 | 338 | { |
0f3fa48a IM |
339 | unsigned long lo, hi; |
340 | ||
341 | if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) | |
342 | return; | |
343 | ||
344 | /* Disable processor serial number: */ | |
345 | ||
346 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
347 | lo |= 0x200000; | |
348 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
349 | ||
1b74dde7 | 350 | pr_notice("CPU serial number disabled.\n"); |
0f3fa48a IM |
351 | clear_cpu_cap(c, X86_FEATURE_PN); |
352 | ||
353 | /* Disabling the serial number may affect the cpuid level */ | |
354 | c->cpuid_level = cpuid_eax(0); | |
0a488a53 YL |
355 | } |
356 | ||
357 | static int __init x86_serial_nr_setup(char *s) | |
358 | { | |
359 | disable_x86_serial_nr = 0; | |
360 | return 1; | |
361 | } | |
362 | __setup("serialnumber", x86_serial_nr_setup); | |
ba51dced | 363 | #else |
102bbe3a YL |
364 | static inline int flag_is_changeable_p(u32 flag) |
365 | { | |
366 | return 1; | |
367 | } | |
102bbe3a YL |
368 | static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
369 | { | |
370 | } | |
ba51dced | 371 | #endif |
0a488a53 | 372 | |
de5397ad FY |
373 | static __init int setup_disable_smep(char *arg) |
374 | { | |
b2cc2a07 | 375 | setup_clear_cpu_cap(X86_FEATURE_SMEP); |
de5397ad FY |
376 | return 1; |
377 | } | |
378 | __setup("nosmep", setup_disable_smep); | |
379 | ||
b2cc2a07 | 380 | static __always_inline void setup_smep(struct cpuinfo_x86 *c) |
de5397ad | 381 | { |
b2cc2a07 | 382 | if (cpu_has(c, X86_FEATURE_SMEP)) |
375074cc | 383 | cr4_set_bits(X86_CR4_SMEP); |
de5397ad FY |
384 | } |
385 | ||
52b6179a PA |
386 | static __init int setup_disable_smap(char *arg) |
387 | { | |
b2cc2a07 | 388 | setup_clear_cpu_cap(X86_FEATURE_SMAP); |
52b6179a PA |
389 | return 1; |
390 | } | |
391 | __setup("nosmap", setup_disable_smap); | |
392 | ||
b2cc2a07 PA |
393 | static __always_inline void setup_smap(struct cpuinfo_x86 *c) |
394 | { | |
581b7f15 | 395 | unsigned long eflags = native_save_fl(); |
b2cc2a07 PA |
396 | |
397 | /* This should have been cleared long ago */ | |
b2cc2a07 PA |
398 | BUG_ON(eflags & X86_EFLAGS_AC); |
399 | ||
03bbd596 PA |
400 | if (cpu_has(c, X86_FEATURE_SMAP)) { |
401 | #ifdef CONFIG_X86_SMAP | |
375074cc | 402 | cr4_set_bits(X86_CR4_SMAP); |
03bbd596 | 403 | #else |
3958b9c3 | 404 | clear_cpu_cap(c, X86_FEATURE_SMAP); |
375074cc | 405 | cr4_clear_bits(X86_CR4_SMAP); |
03bbd596 PA |
406 | #endif |
407 | } | |
de5397ad FY |
408 | } |
409 | ||
aa35f896 RN |
410 | static __always_inline void setup_umip(struct cpuinfo_x86 *c) |
411 | { | |
412 | /* Check the boot processor, plus build option for UMIP. */ | |
413 | if (!cpu_feature_enabled(X86_FEATURE_UMIP)) | |
414 | goto out; | |
415 | ||
416 | /* Check the current processor's cpuid bits. */ | |
417 | if (!cpu_has(c, X86_FEATURE_UMIP)) | |
418 | goto out; | |
419 | ||
420 | cr4_set_bits(X86_CR4_UMIP); | |
421 | ||
438cbf88 | 422 | pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n"); |
770c7755 | 423 | |
aa35f896 RN |
424 | return; |
425 | ||
426 | out: | |
427 | /* | |
428 | * Make sure UMIP is disabled in case it was enabled in a | |
429 | * previous boot (e.g., via kexec). | |
430 | */ | |
431 | cr4_clear_bits(X86_CR4_UMIP); | |
432 | } | |
433 | ||
a13b9d0b KC |
434 | /* These bits should not change their value after CPU init is finished. */ |
435 | static const unsigned long cr4_pinned_mask = | |
436 | X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP | X86_CR4_FSGSBASE; | |
7652ac92 TG |
437 | static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning); |
438 | static unsigned long cr4_pinned_bits __ro_after_init; | |
439 | ||
440 | void native_write_cr0(unsigned long val) | |
441 | { | |
442 | unsigned long bits_missing = 0; | |
443 | ||
444 | set_register: | |
aa5cacdc | 445 | asm volatile("mov %0,%%cr0": "+r" (val) : : "memory"); |
7652ac92 TG |
446 | |
447 | if (static_branch_likely(&cr_pinning)) { | |
448 | if (unlikely((val & X86_CR0_WP) != X86_CR0_WP)) { | |
449 | bits_missing = X86_CR0_WP; | |
450 | val |= bits_missing; | |
451 | goto set_register; | |
452 | } | |
453 | /* Warn after we've set the missing bits. */ | |
454 | WARN_ONCE(bits_missing, "CR0 WP bit went missing!?\n"); | |
455 | } | |
456 | } | |
457 | EXPORT_SYMBOL(native_write_cr0); | |
458 | ||
b64dfcde | 459 | void __no_profile native_write_cr4(unsigned long val) |
7652ac92 | 460 | { |
a13b9d0b | 461 | unsigned long bits_changed = 0; |
7652ac92 TG |
462 | |
463 | set_register: | |
aa5cacdc | 464 | asm volatile("mov %0,%%cr4": "+r" (val) : : "memory"); |
7652ac92 TG |
465 | |
466 | if (static_branch_likely(&cr_pinning)) { | |
a13b9d0b KC |
467 | if (unlikely((val & cr4_pinned_mask) != cr4_pinned_bits)) { |
468 | bits_changed = (val & cr4_pinned_mask) ^ cr4_pinned_bits; | |
469 | val = (val & ~cr4_pinned_mask) | cr4_pinned_bits; | |
7652ac92 TG |
470 | goto set_register; |
471 | } | |
a13b9d0b KC |
472 | /* Warn after we've corrected the changed bits. */ |
473 | WARN_ONCE(bits_changed, "pinned CR4 bits changed: 0x%lx!?\n", | |
474 | bits_changed); | |
7652ac92 TG |
475 | } |
476 | } | |
21953ee5 | 477 | #if IS_MODULE(CONFIG_LKDTM) |
d8f0b353 | 478 | EXPORT_SYMBOL_GPL(native_write_cr4); |
21953ee5 | 479 | #endif |
d8f0b353 TG |
480 | |
481 | void cr4_update_irqsoff(unsigned long set, unsigned long clear) | |
482 | { | |
483 | unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4); | |
484 | ||
485 | lockdep_assert_irqs_disabled(); | |
486 | ||
487 | newval = (cr4 & ~clear) | set; | |
488 | if (newval != cr4) { | |
489 | this_cpu_write(cpu_tlbstate.cr4, newval); | |
490 | __write_cr4(newval); | |
491 | } | |
492 | } | |
493 | EXPORT_SYMBOL(cr4_update_irqsoff); | |
494 | ||
495 | /* Read the CR4 shadow. */ | |
496 | unsigned long cr4_read_shadow(void) | |
497 | { | |
498 | return this_cpu_read(cpu_tlbstate.cr4); | |
499 | } | |
500 | EXPORT_SYMBOL_GPL(cr4_read_shadow); | |
7652ac92 TG |
501 | |
502 | void cr4_init(void) | |
503 | { | |
504 | unsigned long cr4 = __read_cr4(); | |
505 | ||
506 | if (boot_cpu_has(X86_FEATURE_PCID)) | |
507 | cr4 |= X86_CR4_PCIDE; | |
508 | if (static_branch_likely(&cr_pinning)) | |
a13b9d0b | 509 | cr4 = (cr4 & ~cr4_pinned_mask) | cr4_pinned_bits; |
7652ac92 TG |
510 | |
511 | __write_cr4(cr4); | |
512 | ||
513 | /* Initialize cr4 shadow for this CPU. */ | |
514 | this_cpu_write(cpu_tlbstate.cr4, cr4); | |
515 | } | |
873d50d5 KC |
516 | |
517 | /* | |
518 | * Once CPU feature detection is finished (and boot params have been | |
519 | * parsed), record any of the sensitive CR bits that are set, and | |
520 | * enable CR pinning. | |
521 | */ | |
522 | static void __init setup_cr_pinning(void) | |
523 | { | |
a13b9d0b | 524 | cr4_pinned_bits = this_cpu_read(cpu_tlbstate.cr4) & cr4_pinned_mask; |
873d50d5 KC |
525 | static_key_enable(&cr_pinning.key); |
526 | } | |
527 | ||
b745cfba | 528 | static __init int x86_nofsgsbase_setup(char *arg) |
dd649bd0 | 529 | { |
b745cfba AL |
530 | /* Require an exact match without trailing characters. */ |
531 | if (strlen(arg)) | |
532 | return 0; | |
533 | ||
534 | /* Do not emit a message if the feature is not present. */ | |
535 | if (!boot_cpu_has(X86_FEATURE_FSGSBASE)) | |
536 | return 1; | |
537 | ||
538 | setup_clear_cpu_cap(X86_FEATURE_FSGSBASE); | |
539 | pr_info("FSGSBASE disabled via kernel command line\n"); | |
dd649bd0 AL |
540 | return 1; |
541 | } | |
b745cfba | 542 | __setup("nofsgsbase", x86_nofsgsbase_setup); |
dd649bd0 | 543 | |
06976945 DH |
544 | /* |
545 | * Protection Keys are not available in 32-bit mode. | |
546 | */ | |
547 | static bool pku_disabled; | |
548 | ||
549 | static __always_inline void setup_pku(struct cpuinfo_x86 *c) | |
550 | { | |
8a1dc55a TG |
551 | if (c == &boot_cpu_data) { |
552 | if (pku_disabled || !cpu_feature_enabled(X86_FEATURE_PKU)) | |
553 | return; | |
554 | /* | |
555 | * Setting CR4.PKE will cause the X86_FEATURE_OSPKE cpuid | |
556 | * bit to be set. Enforce it. | |
557 | */ | |
558 | setup_force_cpu_cap(X86_FEATURE_OSPKE); | |
a5eff725 | 559 | |
8a1dc55a | 560 | } else if (!cpu_feature_enabled(X86_FEATURE_OSPKE)) { |
06976945 | 561 | return; |
8a1dc55a | 562 | } |
06976945 DH |
563 | |
564 | cr4_set_bits(X86_CR4_PKE); | |
fa8c84b7 TG |
565 | /* Load the default PKRU value */ |
566 | pkru_write_default(); | |
06976945 DH |
567 | } |
568 | ||
569 | #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS | |
570 | static __init int setup_disable_pku(char *arg) | |
571 | { | |
572 | /* | |
573 | * Do not clear the X86_FEATURE_PKU bit. All of the | |
574 | * runtime checks are against OSPKE so clearing the | |
575 | * bit does nothing. | |
576 | * | |
577 | * This way, we will see "pku" in cpuinfo, but not | |
578 | * "ospke", which is exactly what we want. It shows | |
579 | * that the CPU has PKU, but the OS has not enabled it. | |
580 | * This happens to be exactly how a system would look | |
581 | * if we disabled the config option. | |
582 | */ | |
583 | pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n"); | |
584 | pku_disabled = true; | |
585 | return 1; | |
586 | } | |
587 | __setup("nopku", setup_disable_pku); | |
588 | #endif /* CONFIG_X86_64 */ | |
589 | ||
b38b0665 PA |
590 | /* |
591 | * Some CPU features depend on higher CPUID levels, which may not always | |
592 | * be available due to CPUID level capping or broken virtualization | |
593 | * software. Add those features to this table to auto-disable them. | |
594 | */ | |
595 | struct cpuid_dependent_feature { | |
596 | u32 feature; | |
597 | u32 level; | |
598 | }; | |
0f3fa48a | 599 | |
148f9bb8 | 600 | static const struct cpuid_dependent_feature |
b38b0665 PA |
601 | cpuid_dependent_features[] = { |
602 | { X86_FEATURE_MWAIT, 0x00000005 }, | |
603 | { X86_FEATURE_DCA, 0x00000009 }, | |
604 | { X86_FEATURE_XSAVE, 0x0000000d }, | |
605 | { 0, 0 } | |
606 | }; | |
607 | ||
148f9bb8 | 608 | static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) |
b38b0665 PA |
609 | { |
610 | const struct cpuid_dependent_feature *df; | |
9766cdbc | 611 | |
b38b0665 | 612 | for (df = cpuid_dependent_features; df->feature; df++) { |
0f3fa48a IM |
613 | |
614 | if (!cpu_has(c, df->feature)) | |
615 | continue; | |
b38b0665 PA |
616 | /* |
617 | * Note: cpuid_level is set to -1 if unavailable, but | |
618 | * extended_extended_level is set to 0 if unavailable | |
619 | * and the legitimate extended levels are all negative | |
620 | * when signed; hence the weird messing around with | |
621 | * signs here... | |
622 | */ | |
0f3fa48a | 623 | if (!((s32)df->level < 0 ? |
f6db44df | 624 | (u32)df->level > (u32)c->extended_cpuid_level : |
0f3fa48a IM |
625 | (s32)df->level > (s32)c->cpuid_level)) |
626 | continue; | |
627 | ||
628 | clear_cpu_cap(c, df->feature); | |
629 | if (!warn) | |
630 | continue; | |
631 | ||
1b74dde7 CY |
632 | pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", |
633 | x86_cap_flag(df->feature), df->level); | |
b38b0665 | 634 | } |
f6db44df | 635 | } |
b38b0665 | 636 | |
102bbe3a YL |
637 | /* |
638 | * Naming convention should be: <Name> [(<Codename>)] | |
639 | * This table only is used unless init_<vendor>() below doesn't set it; | |
0f3fa48a IM |
640 | * in particular, if CPUID levels 0x80000002..4 are supported, this |
641 | * isn't used | |
102bbe3a YL |
642 | */ |
643 | ||
644 | /* Look up CPU names by table lookup. */ | |
148f9bb8 | 645 | static const char *table_lookup_model(struct cpuinfo_x86 *c) |
102bbe3a | 646 | { |
09dc68d9 JB |
647 | #ifdef CONFIG_X86_32 |
648 | const struct legacy_cpu_model_info *info; | |
102bbe3a YL |
649 | |
650 | if (c->x86_model >= 16) | |
651 | return NULL; /* Range check */ | |
652 | ||
653 | if (!this_cpu) | |
654 | return NULL; | |
655 | ||
09dc68d9 | 656 | info = this_cpu->legacy_models; |
102bbe3a | 657 | |
09dc68d9 | 658 | while (info->family) { |
102bbe3a YL |
659 | if (info->family == c->x86) |
660 | return info->model_names[c->x86_model]; | |
661 | info++; | |
662 | } | |
09dc68d9 | 663 | #endif |
102bbe3a YL |
664 | return NULL; /* Not found */ |
665 | } | |
666 | ||
f6a892dd FY |
667 | /* Aligned to unsigned long to avoid split lock in atomic bitmap ops */ |
668 | __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); | |
669 | __u32 cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long)); | |
7d851c8d | 670 | |
11e3a840 JF |
671 | void load_percpu_segment(int cpu) |
672 | { | |
673 | #ifdef CONFIG_X86_32 | |
674 | loadsegment(fs, __KERNEL_PERCPU); | |
675 | #else | |
45e876f7 | 676 | __loadsegment_simple(gs, 0); |
35060ed6 | 677 | wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu)); |
11e3a840 JF |
678 | #endif |
679 | } | |
680 | ||
72f5e08d AL |
681 | #ifdef CONFIG_X86_32 |
682 | /* The 32-bit entry code needs to find cpu_entry_area. */ | |
683 | DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area); | |
684 | #endif | |
685 | ||
45fc8757 TG |
686 | /* Load the original GDT from the per-cpu structure */ |
687 | void load_direct_gdt(int cpu) | |
688 | { | |
689 | struct desc_ptr gdt_descr; | |
690 | ||
691 | gdt_descr.address = (long)get_cpu_gdt_rw(cpu); | |
692 | gdt_descr.size = GDT_SIZE - 1; | |
693 | load_gdt(&gdt_descr); | |
694 | } | |
695 | EXPORT_SYMBOL_GPL(load_direct_gdt); | |
696 | ||
69218e47 TG |
697 | /* Load a fixmap remapping of the per-cpu GDT */ |
698 | void load_fixmap_gdt(int cpu) | |
699 | { | |
700 | struct desc_ptr gdt_descr; | |
701 | ||
702 | gdt_descr.address = (long)get_cpu_gdt_ro(cpu); | |
703 | gdt_descr.size = GDT_SIZE - 1; | |
704 | load_gdt(&gdt_descr); | |
705 | } | |
45fc8757 | 706 | EXPORT_SYMBOL_GPL(load_fixmap_gdt); |
69218e47 | 707 | |
0f3fa48a IM |
708 | /* |
709 | * Current gdt points %fs at the "master" per-cpu area: after this, | |
710 | * it's on the real one. | |
711 | */ | |
552be871 | 712 | void switch_to_new_gdt(int cpu) |
9d31d35b | 713 | { |
45fc8757 TG |
714 | /* Load the original GDT */ |
715 | load_direct_gdt(cpu); | |
2697fbd5 | 716 | /* Reload the per-cpu base */ |
11e3a840 | 717 | load_percpu_segment(cpu); |
9d31d35b YL |
718 | } |
719 | ||
148f9bb8 | 720 | static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; |
1da177e4 | 721 | |
148f9bb8 | 722 | static void get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
723 | { |
724 | unsigned int *v; | |
ee098e1a | 725 | char *p, *q, *s; |
1da177e4 | 726 | |
3da99c97 | 727 | if (c->extended_cpuid_level < 0x80000004) |
1b05d60d | 728 | return; |
1da177e4 | 729 | |
0f3fa48a | 730 | v = (unsigned int *)c->x86_model_id; |
1da177e4 LT |
731 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); |
732 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
733 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
734 | c->x86_model_id[48] = 0; | |
735 | ||
ee098e1a BP |
736 | /* Trim whitespace */ |
737 | p = q = s = &c->x86_model_id[0]; | |
738 | ||
739 | while (*p == ' ') | |
740 | p++; | |
741 | ||
742 | while (*p) { | |
743 | /* Note the last non-whitespace index */ | |
744 | if (!isspace(*p)) | |
745 | s = q; | |
746 | ||
747 | *q++ = *p++; | |
748 | } | |
749 | ||
750 | *(s + 1) = '\0'; | |
1da177e4 LT |
751 | } |
752 | ||
9305bd6c | 753 | void detect_num_cpu_cores(struct cpuinfo_x86 *c) |
2cc61be6 DW |
754 | { |
755 | unsigned int eax, ebx, ecx, edx; | |
756 | ||
9305bd6c | 757 | c->x86_max_cores = 1; |
2cc61be6 | 758 | if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4) |
9305bd6c | 759 | return; |
2cc61be6 DW |
760 | |
761 | cpuid_count(4, 0, &eax, &ebx, &ecx, &edx); | |
762 | if (eax & 0x1f) | |
9305bd6c | 763 | c->x86_max_cores = (eax >> 26) + 1; |
2cc61be6 DW |
764 | } |
765 | ||
148f9bb8 | 766 | void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) |
1da177e4 | 767 | { |
9d31d35b | 768 | unsigned int n, dummy, ebx, ecx, edx, l2size; |
1da177e4 | 769 | |
3da99c97 | 770 | n = c->extended_cpuid_level; |
1da177e4 LT |
771 | |
772 | if (n >= 0x80000005) { | |
9d31d35b | 773 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); |
9d31d35b | 774 | c->x86_cache_size = (ecx>>24) + (edx>>24); |
140fc727 YL |
775 | #ifdef CONFIG_X86_64 |
776 | /* On K8 L1 TLB is inclusive, so don't count it */ | |
777 | c->x86_tlbsize = 0; | |
778 | #endif | |
1da177e4 LT |
779 | } |
780 | ||
781 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
782 | return; | |
783 | ||
0a488a53 | 784 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 785 | l2size = ecx >> 16; |
34048c9e | 786 | |
140fc727 YL |
787 | #ifdef CONFIG_X86_64 |
788 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
789 | #else | |
1da177e4 | 790 | /* do processor-specific cache resizing */ |
09dc68d9 JB |
791 | if (this_cpu->legacy_cache_size) |
792 | l2size = this_cpu->legacy_cache_size(c, l2size); | |
1da177e4 LT |
793 | |
794 | /* Allow user to override all this if necessary. */ | |
795 | if (cachesize_override != -1) | |
796 | l2size = cachesize_override; | |
797 | ||
34048c9e | 798 | if (l2size == 0) |
1da177e4 | 799 | return; /* Again, no L2 cache is possible */ |
140fc727 | 800 | #endif |
1da177e4 LT |
801 | |
802 | c->x86_cache_size = l2size; | |
1da177e4 LT |
803 | } |
804 | ||
e0ba94f1 AS |
805 | u16 __read_mostly tlb_lli_4k[NR_INFO]; |
806 | u16 __read_mostly tlb_lli_2m[NR_INFO]; | |
807 | u16 __read_mostly tlb_lli_4m[NR_INFO]; | |
808 | u16 __read_mostly tlb_lld_4k[NR_INFO]; | |
809 | u16 __read_mostly tlb_lld_2m[NR_INFO]; | |
810 | u16 __read_mostly tlb_lld_4m[NR_INFO]; | |
dd360393 | 811 | u16 __read_mostly tlb_lld_1g[NR_INFO]; |
e0ba94f1 | 812 | |
f94fe119 | 813 | static void cpu_detect_tlb(struct cpuinfo_x86 *c) |
e0ba94f1 AS |
814 | { |
815 | if (this_cpu->c_detect_tlb) | |
816 | this_cpu->c_detect_tlb(c); | |
817 | ||
f94fe119 | 818 | pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", |
e0ba94f1 | 819 | tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], |
f94fe119 SH |
820 | tlb_lli_4m[ENTRIES]); |
821 | ||
822 | pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", | |
823 | tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES], | |
824 | tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); | |
e0ba94f1 AS |
825 | } |
826 | ||
545401f4 | 827 | int detect_ht_early(struct cpuinfo_x86 *c) |
1da177e4 | 828 | { |
c8e56d20 | 829 | #ifdef CONFIG_SMP |
0a488a53 | 830 | u32 eax, ebx, ecx, edx; |
1da177e4 | 831 | |
0a488a53 | 832 | if (!cpu_has(c, X86_FEATURE_HT)) |
545401f4 | 833 | return -1; |
1da177e4 | 834 | |
0a488a53 | 835 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
545401f4 | 836 | return -1; |
1da177e4 | 837 | |
1cd78776 | 838 | if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) |
545401f4 | 839 | return -1; |
1da177e4 | 840 | |
0a488a53 | 841 | cpuid(1, &eax, &ebx, &ecx, &edx); |
1da177e4 | 842 | |
9d31d35b | 843 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
545401f4 | 844 | if (smp_num_siblings == 1) |
1b74dde7 | 845 | pr_info_once("CPU0: Hyper-Threading is disabled\n"); |
545401f4 TG |
846 | #endif |
847 | return 0; | |
848 | } | |
9d31d35b | 849 | |
545401f4 TG |
850 | void detect_ht(struct cpuinfo_x86 *c) |
851 | { | |
852 | #ifdef CONFIG_SMP | |
853 | int index_msb, core_bits; | |
55e6d279 | 854 | |
545401f4 | 855 | if (detect_ht_early(c) < 0) |
55e6d279 | 856 | return; |
9d31d35b | 857 | |
0f3fa48a IM |
858 | index_msb = get_count_order(smp_num_siblings); |
859 | c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); | |
9d31d35b | 860 | |
0f3fa48a | 861 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; |
9d31d35b | 862 | |
0f3fa48a | 863 | index_msb = get_count_order(smp_num_siblings); |
9d31d35b | 864 | |
0f3fa48a | 865 | core_bits = get_count_order(c->x86_max_cores); |
9d31d35b | 866 | |
0f3fa48a IM |
867 | c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & |
868 | ((1 << core_bits) - 1); | |
9d31d35b | 869 | #endif |
97e4db7c | 870 | } |
1da177e4 | 871 | |
148f9bb8 | 872 | static void get_cpu_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
873 | { |
874 | char *v = c->x86_vendor_id; | |
0f3fa48a | 875 | int i; |
1da177e4 LT |
876 | |
877 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
10a434fc YL |
878 | if (!cpu_devs[i]) |
879 | break; | |
880 | ||
881 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
882 | (cpu_devs[i]->c_ident[1] && | |
883 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
0f3fa48a | 884 | |
10a434fc YL |
885 | this_cpu = cpu_devs[i]; |
886 | c->x86_vendor = this_cpu->c_x86_vendor; | |
887 | return; | |
1da177e4 LT |
888 | } |
889 | } | |
10a434fc | 890 | |
1b74dde7 CY |
891 | pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \ |
892 | "CPU: Your system may be unstable.\n", v); | |
10a434fc | 893 | |
fe38d855 CE |
894 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
895 | this_cpu = &default_cpu; | |
1da177e4 LT |
896 | } |
897 | ||
148f9bb8 | 898 | void cpu_detect(struct cpuinfo_x86 *c) |
1da177e4 | 899 | { |
1da177e4 | 900 | /* Get vendor name */ |
4a148513 HH |
901 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, |
902 | (unsigned int *)&c->x86_vendor_id[0], | |
903 | (unsigned int *)&c->x86_vendor_id[8], | |
904 | (unsigned int *)&c->x86_vendor_id[4]); | |
1da177e4 | 905 | |
1da177e4 | 906 | c->x86 = 4; |
9d31d35b | 907 | /* Intel-defined flags: level 0x00000001 */ |
1da177e4 LT |
908 | if (c->cpuid_level >= 0x00000001) { |
909 | u32 junk, tfms, cap0, misc; | |
0f3fa48a | 910 | |
1da177e4 | 911 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); |
99f925ce BP |
912 | c->x86 = x86_family(tfms); |
913 | c->x86_model = x86_model(tfms); | |
b399151c | 914 | c->x86_stepping = x86_stepping(tfms); |
0f3fa48a | 915 | |
d4387bd3 | 916 | if (cap0 & (1<<19)) { |
d4387bd3 | 917 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
9d31d35b | 918 | c->x86_cache_alignment = c->x86_clflush_size; |
d4387bd3 | 919 | } |
1da177e4 | 920 | } |
1da177e4 | 921 | } |
3da99c97 | 922 | |
8bf1ebca AL |
923 | static void apply_forced_caps(struct cpuinfo_x86 *c) |
924 | { | |
925 | int i; | |
926 | ||
6cbd2171 | 927 | for (i = 0; i < NCAPINTS + NBUGINTS; i++) { |
8bf1ebca AL |
928 | c->x86_capability[i] &= ~cpu_caps_cleared[i]; |
929 | c->x86_capability[i] |= cpu_caps_set[i]; | |
930 | } | |
931 | } | |
932 | ||
7fcae111 DW |
933 | static void init_speculation_control(struct cpuinfo_x86 *c) |
934 | { | |
935 | /* | |
936 | * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support, | |
937 | * and they also have a different bit for STIBP support. Also, | |
938 | * a hypervisor might have set the individual AMD bits even on | |
939 | * Intel CPUs, for finer-grained selection of what's available. | |
7fcae111 DW |
940 | */ |
941 | if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) { | |
942 | set_cpu_cap(c, X86_FEATURE_IBRS); | |
943 | set_cpu_cap(c, X86_FEATURE_IBPB); | |
7eb8956a | 944 | set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); |
7fcae111 | 945 | } |
e7c587da | 946 | |
7fcae111 DW |
947 | if (cpu_has(c, X86_FEATURE_INTEL_STIBP)) |
948 | set_cpu_cap(c, X86_FEATURE_STIBP); | |
e7c587da | 949 | |
bc226f07 TL |
950 | if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) || |
951 | cpu_has(c, X86_FEATURE_VIRT_SSBD)) | |
52817587 TG |
952 | set_cpu_cap(c, X86_FEATURE_SSBD); |
953 | ||
7eb8956a | 954 | if (cpu_has(c, X86_FEATURE_AMD_IBRS)) { |
e7c587da | 955 | set_cpu_cap(c, X86_FEATURE_IBRS); |
7eb8956a TG |
956 | set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); |
957 | } | |
e7c587da BP |
958 | |
959 | if (cpu_has(c, X86_FEATURE_AMD_IBPB)) | |
960 | set_cpu_cap(c, X86_FEATURE_IBPB); | |
961 | ||
7eb8956a | 962 | if (cpu_has(c, X86_FEATURE_AMD_STIBP)) { |
e7c587da | 963 | set_cpu_cap(c, X86_FEATURE_STIBP); |
7eb8956a TG |
964 | set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); |
965 | } | |
6ac2f49e KRW |
966 | |
967 | if (cpu_has(c, X86_FEATURE_AMD_SSBD)) { | |
968 | set_cpu_cap(c, X86_FEATURE_SSBD); | |
969 | set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL); | |
970 | clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD); | |
971 | } | |
7fcae111 DW |
972 | } |
973 | ||
148f9bb8 | 974 | void get_cpu_cap(struct cpuinfo_x86 *c) |
093af8d7 | 975 | { |
39c06df4 | 976 | u32 eax, ebx, ecx, edx; |
093af8d7 | 977 | |
3da99c97 YL |
978 | /* Intel-defined flags: level 0x00000001 */ |
979 | if (c->cpuid_level >= 0x00000001) { | |
39c06df4 | 980 | cpuid(0x00000001, &eax, &ebx, &ecx, &edx); |
0f3fa48a | 981 | |
39c06df4 BP |
982 | c->x86_capability[CPUID_1_ECX] = ecx; |
983 | c->x86_capability[CPUID_1_EDX] = edx; | |
3da99c97 | 984 | } |
093af8d7 | 985 | |
3df8d920 AL |
986 | /* Thermal and Power Management Leaf: level 0x00000006 (eax) */ |
987 | if (c->cpuid_level >= 0x00000006) | |
988 | c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); | |
989 | ||
bdc802dc PA |
990 | /* Additional Intel-defined flags: level 0x00000007 */ |
991 | if (c->cpuid_level >= 0x00000007) { | |
bdc802dc | 992 | cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); |
39c06df4 | 993 | c->x86_capability[CPUID_7_0_EBX] = ebx; |
dfb4a70f | 994 | c->x86_capability[CPUID_7_ECX] = ecx; |
95ca0ee8 | 995 | c->x86_capability[CPUID_7_EDX] = edx; |
b302e4b1 FY |
996 | |
997 | /* Check valid sub-leaf index before accessing it */ | |
998 | if (eax >= 1) { | |
999 | cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx); | |
1000 | c->x86_capability[CPUID_7_1_EAX] = eax; | |
1001 | } | |
bdc802dc PA |
1002 | } |
1003 | ||
6229ad27 FY |
1004 | /* Extended state features: level 0x0000000d */ |
1005 | if (c->cpuid_level >= 0x0000000d) { | |
6229ad27 FY |
1006 | cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); |
1007 | ||
39c06df4 | 1008 | c->x86_capability[CPUID_D_1_EAX] = eax; |
6229ad27 FY |
1009 | } |
1010 | ||
3da99c97 | 1011 | /* AMD-defined flags: level 0x80000001 */ |
39c06df4 BP |
1012 | eax = cpuid_eax(0x80000000); |
1013 | c->extended_cpuid_level = eax; | |
1014 | ||
1015 | if ((eax & 0xffff0000) == 0x80000000) { | |
1016 | if (eax >= 0x80000001) { | |
1017 | cpuid(0x80000001, &eax, &ebx, &ecx, &edx); | |
0f3fa48a | 1018 | |
39c06df4 BP |
1019 | c->x86_capability[CPUID_8000_0001_ECX] = ecx; |
1020 | c->x86_capability[CPUID_8000_0001_EDX] = edx; | |
093af8d7 | 1021 | } |
093af8d7 | 1022 | } |
093af8d7 | 1023 | |
71faad43 YG |
1024 | if (c->extended_cpuid_level >= 0x80000007) { |
1025 | cpuid(0x80000007, &eax, &ebx, &ecx, &edx); | |
1026 | ||
1027 | c->x86_capability[CPUID_8000_0007_EBX] = ebx; | |
1028 | c->x86_power = edx; | |
1029 | } | |
1030 | ||
c65732e4 TG |
1031 | if (c->extended_cpuid_level >= 0x80000008) { |
1032 | cpuid(0x80000008, &eax, &ebx, &ecx, &edx); | |
1033 | c->x86_capability[CPUID_8000_0008_EBX] = ebx; | |
1034 | } | |
1035 | ||
2ccd71f1 | 1036 | if (c->extended_cpuid_level >= 0x8000000a) |
39c06df4 | 1037 | c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); |
093af8d7 | 1038 | |
fb35d30f SC |
1039 | if (c->extended_cpuid_level >= 0x8000001f) |
1040 | c->x86_capability[CPUID_8000_001F_EAX] = cpuid_eax(0x8000001f); | |
1041 | ||
1dedefd1 | 1042 | init_scattered_cpuid_features(c); |
7fcae111 | 1043 | init_speculation_control(c); |
60d34501 AL |
1044 | |
1045 | /* | |
1046 | * Clear/Set all flags overridden by options, after probe. | |
1047 | * This needs to happen each time we re-probe, which may happen | |
1048 | * several times during CPU initialization. | |
1049 | */ | |
1050 | apply_forced_caps(c); | |
093af8d7 | 1051 | } |
1da177e4 | 1052 | |
405c018a | 1053 | void get_cpu_address_sizes(struct cpuinfo_x86 *c) |
d94a155c KS |
1054 | { |
1055 | u32 eax, ebx, ecx, edx; | |
1056 | ||
1057 | if (c->extended_cpuid_level >= 0x80000008) { | |
1058 | cpuid(0x80000008, &eax, &ebx, &ecx, &edx); | |
1059 | ||
1060 | c->x86_virt_bits = (eax >> 8) & 0xff; | |
1061 | c->x86_phys_bits = eax & 0xff; | |
d94a155c KS |
1062 | } |
1063 | #ifdef CONFIG_X86_32 | |
1064 | else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) | |
1065 | c->x86_phys_bits = 36; | |
1066 | #endif | |
cc51e542 | 1067 | c->x86_cache_bits = c->x86_phys_bits; |
d94a155c KS |
1068 | } |
1069 | ||
148f9bb8 | 1070 | static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) |
aef93c8b YL |
1071 | { |
1072 | #ifdef CONFIG_X86_32 | |
1073 | int i; | |
1074 | ||
1075 | /* | |
1076 | * First of all, decide if this is a 486 or higher | |
1077 | * It's a 486 if we can modify the AC flag | |
1078 | */ | |
1079 | if (flag_is_changeable_p(X86_EFLAGS_AC)) | |
1080 | c->x86 = 4; | |
1081 | else | |
1082 | c->x86 = 3; | |
1083 | ||
1084 | for (i = 0; i < X86_VENDOR_NUM; i++) | |
1085 | if (cpu_devs[i] && cpu_devs[i]->c_identify) { | |
1086 | c->x86_vendor_id[0] = 0; | |
1087 | cpu_devs[i]->c_identify(c); | |
1088 | if (c->x86_vendor_id[0]) { | |
1089 | get_cpu_vendor(c); | |
1090 | break; | |
1091 | } | |
1092 | } | |
1093 | #endif | |
1094 | } | |
1095 | ||
db4d30fb VT |
1096 | #define NO_SPECULATION BIT(0) |
1097 | #define NO_MELTDOWN BIT(1) | |
1098 | #define NO_SSB BIT(2) | |
1099 | #define NO_L1TF BIT(3) | |
1100 | #define NO_MDS BIT(4) | |
1101 | #define MSBDS_ONLY BIT(5) | |
1102 | #define NO_SWAPGS BIT(6) | |
1103 | #define NO_ITLB_MULTIHIT BIT(7) | |
1e41a766 | 1104 | #define NO_SPECTRE_V2 BIT(8) |
36ad3513 | 1105 | |
f6d502fc TG |
1106 | #define VULNWL(vendor, family, model, whitelist) \ |
1107 | X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, whitelist) | |
36ad3513 TG |
1108 | |
1109 | #define VULNWL_INTEL(model, whitelist) \ | |
1110 | VULNWL(INTEL, 6, INTEL_FAM6_##model, whitelist) | |
1111 | ||
1112 | #define VULNWL_AMD(family, whitelist) \ | |
1113 | VULNWL(AMD, family, X86_MODEL_ANY, whitelist) | |
1114 | ||
1115 | #define VULNWL_HYGON(family, whitelist) \ | |
1116 | VULNWL(HYGON, family, X86_MODEL_ANY, whitelist) | |
1117 | ||
1118 | static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { | |
1119 | VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION), | |
1120 | VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION), | |
1121 | VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION), | |
1122 | VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION), | |
639475d4 MDSV |
1123 | VULNWL(VORTEX, 5, X86_MODEL_ANY, NO_SPECULATION), |
1124 | VULNWL(VORTEX, 6, X86_MODEL_ANY, NO_SPECULATION), | |
36ad3513 | 1125 | |
ed5194c2 | 1126 | /* Intel Family 6 */ |
db4d30fb VT |
1127 | VULNWL_INTEL(ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT), |
1128 | VULNWL_INTEL(ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT), | |
1129 | VULNWL_INTEL(ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), | |
1130 | VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT), | |
1131 | VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), | |
1132 | ||
1133 | VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), | |
1134 | VULNWL_INTEL(ATOM_SILVERMONT_D, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), | |
1135 | VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), | |
1136 | VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), | |
1137 | VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), | |
1138 | VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), | |
36ad3513 TG |
1139 | |
1140 | VULNWL_INTEL(CORE_YONAH, NO_SSB), | |
1141 | ||
db4d30fb VT |
1142 | VULNWL_INTEL(ATOM_AIRMONT_MID, NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT), |
1143 | VULNWL_INTEL(ATOM_AIRMONT_NP, NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), | |
36ad3513 | 1144 | |
db4d30fb VT |
1145 | VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), |
1146 | VULNWL_INTEL(ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), | |
1147 | VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT), | |
f36cf386 TG |
1148 | |
1149 | /* | |
1150 | * Technically, swapgs isn't serializing on AMD (despite it previously | |
1151 | * being documented as such in the APM). But according to AMD, %gs is | |
1152 | * updated non-speculatively, and the issuing of %gs-relative memory | |
1153 | * operands will be blocked until the %gs update completes, which is | |
1154 | * good enough for our purposes. | |
1155 | */ | |
ed5194c2 | 1156 | |
cad14885 PG |
1157 | VULNWL_INTEL(ATOM_TREMONT_D, NO_ITLB_MULTIHIT), |
1158 | ||
ed5194c2 | 1159 | /* AMD Family 0xf - 0x12 */ |
db4d30fb VT |
1160 | VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), |
1161 | VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), | |
1162 | VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), | |
1163 | VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), | |
36ad3513 TG |
1164 | |
1165 | /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */ | |
db4d30fb VT |
1166 | VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), |
1167 | VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT), | |
1e41a766 TW |
1168 | |
1169 | /* Zhaoxin Family 7 */ | |
a84de2fa TW |
1170 | VULNWL(CENTAUR, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS), |
1171 | VULNWL(ZHAOXIN, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS), | |
fec9434a DW |
1172 | {} |
1173 | }; | |
1174 | ||
7e5b3c26 MG |
1175 | #define VULNBL_INTEL_STEPPINGS(model, steppings, issues) \ |
1176 | X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE(INTEL, 6, \ | |
1177 | INTEL_FAM6_##model, steppings, \ | |
1178 | X86_FEATURE_ANY, issues) | |
1179 | ||
1180 | #define SRBDS BIT(0) | |
1181 | ||
1182 | static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = { | |
1183 | VULNBL_INTEL_STEPPINGS(IVYBRIDGE, X86_STEPPING_ANY, SRBDS), | |
1184 | VULNBL_INTEL_STEPPINGS(HASWELL, X86_STEPPING_ANY, SRBDS), | |
1185 | VULNBL_INTEL_STEPPINGS(HASWELL_L, X86_STEPPING_ANY, SRBDS), | |
1186 | VULNBL_INTEL_STEPPINGS(HASWELL_G, X86_STEPPING_ANY, SRBDS), | |
1187 | VULNBL_INTEL_STEPPINGS(BROADWELL_G, X86_STEPPING_ANY, SRBDS), | |
1188 | VULNBL_INTEL_STEPPINGS(BROADWELL, X86_STEPPING_ANY, SRBDS), | |
1189 | VULNBL_INTEL_STEPPINGS(SKYLAKE_L, X86_STEPPING_ANY, SRBDS), | |
1190 | VULNBL_INTEL_STEPPINGS(SKYLAKE, X86_STEPPING_ANY, SRBDS), | |
1191 | VULNBL_INTEL_STEPPINGS(KABYLAKE_L, X86_STEPPINGS(0x0, 0xC), SRBDS), | |
1192 | VULNBL_INTEL_STEPPINGS(KABYLAKE, X86_STEPPINGS(0x0, 0xD), SRBDS), | |
1193 | {} | |
1194 | }; | |
1195 | ||
93920f61 | 1196 | static bool __init cpu_matches(const struct x86_cpu_id *table, unsigned long which) |
36ad3513 | 1197 | { |
93920f61 | 1198 | const struct x86_cpu_id *m = x86_match_cpu(table); |
c456442c | 1199 | |
36ad3513 TG |
1200 | return m && !!(m->driver_data & which); |
1201 | } | |
17dbca11 | 1202 | |
286836a7 | 1203 | u64 x86_read_arch_cap_msr(void) |
fec9434a DW |
1204 | { |
1205 | u64 ia32_cap = 0; | |
1206 | ||
286836a7 PG |
1207 | if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) |
1208 | rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap); | |
1209 | ||
1210 | return ia32_cap; | |
1211 | } | |
1212 | ||
1213 | static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) | |
1214 | { | |
1215 | u64 ia32_cap = x86_read_arch_cap_msr(); | |
1216 | ||
db4d30fb | 1217 | /* Set ITLB_MULTIHIT bug if cpu is not in the whitelist and not mitigated */ |
93920f61 MG |
1218 | if (!cpu_matches(cpu_vuln_whitelist, NO_ITLB_MULTIHIT) && |
1219 | !(ia32_cap & ARCH_CAP_PSCHANGE_MC_NO)) | |
db4d30fb VT |
1220 | setup_force_cpu_bug(X86_BUG_ITLB_MULTIHIT); |
1221 | ||
93920f61 | 1222 | if (cpu_matches(cpu_vuln_whitelist, NO_SPECULATION)) |
8ecc4979 DB |
1223 | return; |
1224 | ||
1225 | setup_force_cpu_bug(X86_BUG_SPECTRE_V1); | |
1e41a766 | 1226 | |
93920f61 | 1227 | if (!cpu_matches(cpu_vuln_whitelist, NO_SPECTRE_V2)) |
1e41a766 | 1228 | setup_force_cpu_bug(X86_BUG_SPECTRE_V2); |
8ecc4979 | 1229 | |
93920f61 MG |
1230 | if (!cpu_matches(cpu_vuln_whitelist, NO_SSB) && |
1231 | !(ia32_cap & ARCH_CAP_SSB_NO) && | |
24809860 | 1232 | !cpu_has(c, X86_FEATURE_AMD_SSB_NO)) |
c456442c KRW |
1233 | setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS); |
1234 | ||
706d5168 SP |
1235 | if (ia32_cap & ARCH_CAP_IBRS_ALL) |
1236 | setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED); | |
1237 | ||
93920f61 MG |
1238 | if (!cpu_matches(cpu_vuln_whitelist, NO_MDS) && |
1239 | !(ia32_cap & ARCH_CAP_MDS_NO)) { | |
ed5194c2 | 1240 | setup_force_cpu_bug(X86_BUG_MDS); |
93920f61 | 1241 | if (cpu_matches(cpu_vuln_whitelist, MSBDS_ONLY)) |
e261f209 TG |
1242 | setup_force_cpu_bug(X86_BUG_MSBDS_ONLY); |
1243 | } | |
ed5194c2 | 1244 | |
93920f61 | 1245 | if (!cpu_matches(cpu_vuln_whitelist, NO_SWAPGS)) |
f36cf386 TG |
1246 | setup_force_cpu_bug(X86_BUG_SWAPGS); |
1247 | ||
1b42f017 PG |
1248 | /* |
1249 | * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when: | |
1250 | * - TSX is supported or | |
1251 | * - TSX_CTRL is present | |
1252 | * | |
1253 | * TSX_CTRL check is needed for cases when TSX could be disabled before | |
1254 | * the kernel boot e.g. kexec. | |
1255 | * TSX_CTRL check alone is not sufficient for cases when the microcode | |
1256 | * update is not present or running as guest that don't get TSX_CTRL. | |
1257 | */ | |
1258 | if (!(ia32_cap & ARCH_CAP_TAA_NO) && | |
1259 | (cpu_has(c, X86_FEATURE_RTM) || | |
1260 | (ia32_cap & ARCH_CAP_TSX_CTRL_MSR))) | |
1261 | setup_force_cpu_bug(X86_BUG_TAA); | |
1262 | ||
7e5b3c26 MG |
1263 | /* |
1264 | * SRBDS affects CPUs which support RDRAND or RDSEED and are listed | |
1265 | * in the vulnerability blacklist. | |
1266 | */ | |
1267 | if ((cpu_has(c, X86_FEATURE_RDRAND) || | |
1268 | cpu_has(c, X86_FEATURE_RDSEED)) && | |
1269 | cpu_matches(cpu_vuln_blacklist, SRBDS)) | |
1270 | setup_force_cpu_bug(X86_BUG_SRBDS); | |
1271 | ||
93920f61 | 1272 | if (cpu_matches(cpu_vuln_whitelist, NO_MELTDOWN)) |
4a28bfe3 | 1273 | return; |
fec9434a | 1274 | |
fec9434a DW |
1275 | /* Rogue Data Cache Load? No! */ |
1276 | if (ia32_cap & ARCH_CAP_RDCL_NO) | |
4a28bfe3 | 1277 | return; |
fec9434a | 1278 | |
4a28bfe3 | 1279 | setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN); |
17dbca11 | 1280 | |
93920f61 | 1281 | if (cpu_matches(cpu_vuln_whitelist, NO_L1TF)) |
17dbca11 AK |
1282 | return; |
1283 | ||
1284 | setup_force_cpu_bug(X86_BUG_L1TF); | |
fec9434a DW |
1285 | } |
1286 | ||
8990cac6 PT |
1287 | /* |
1288 | * The NOPL instruction is supposed to exist on all CPUs of family >= 6; | |
1289 | * unfortunately, that's not true in practice because of early VIA | |
1290 | * chips and (more importantly) broken virtualizers that are not easy | |
1291 | * to detect. In the latter case it doesn't even *fail* reliably, so | |
1292 | * probing for it doesn't even work. Disable it completely on 32-bit | |
1293 | * unless we can find a reliable way to detect all the broken cases. | |
1294 | * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). | |
1295 | */ | |
9b3661cd | 1296 | static void detect_nopl(void) |
8990cac6 PT |
1297 | { |
1298 | #ifdef CONFIG_X86_32 | |
9b3661cd | 1299 | setup_clear_cpu_cap(X86_FEATURE_NOPL); |
8990cac6 | 1300 | #else |
9b3661cd | 1301 | setup_force_cpu_cap(X86_FEATURE_NOPL); |
8990cac6 PT |
1302 | #endif |
1303 | } | |
1304 | ||
1ef5423a MH |
1305 | /* |
1306 | * We parse cpu parameters early because fpu__init_system() is executed | |
1307 | * before parse_early_param(). | |
1308 | */ | |
1309 | static void __init cpu_parse_early_param(void) | |
1310 | { | |
1311 | char arg[128]; | |
1312 | char *argptr = arg; | |
1313 | int arglen, res, bit; | |
1314 | ||
1315 | #ifdef CONFIG_X86_32 | |
1316 | if (cmdline_find_option_bool(boot_command_line, "no387")) | |
1317 | #ifdef CONFIG_MATH_EMULATION | |
1318 | setup_clear_cpu_cap(X86_FEATURE_FPU); | |
1319 | #else | |
1320 | pr_err("Option 'no387' required CONFIG_MATH_EMULATION enabled.\n"); | |
1321 | #endif | |
1322 | ||
1323 | if (cmdline_find_option_bool(boot_command_line, "nofxsr")) | |
1324 | setup_clear_cpu_cap(X86_FEATURE_FXSR); | |
1325 | #endif | |
1326 | ||
1327 | if (cmdline_find_option_bool(boot_command_line, "noxsave")) | |
1328 | setup_clear_cpu_cap(X86_FEATURE_XSAVE); | |
1329 | ||
1330 | if (cmdline_find_option_bool(boot_command_line, "noxsaveopt")) | |
1331 | setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); | |
1332 | ||
1333 | if (cmdline_find_option_bool(boot_command_line, "noxsaves")) | |
1334 | setup_clear_cpu_cap(X86_FEATURE_XSAVES); | |
1335 | ||
1336 | arglen = cmdline_find_option(boot_command_line, "clearcpuid", arg, sizeof(arg)); | |
1337 | if (arglen <= 0) | |
1338 | return; | |
1339 | ||
1340 | pr_info("Clearing CPUID bits:"); | |
1341 | do { | |
1342 | res = get_option(&argptr, &bit); | |
1343 | if (res == 0 || res == 3) | |
1344 | break; | |
1345 | ||
1346 | /* If the argument was too long, the last bit may be cut off */ | |
1347 | if (res == 1 && arglen >= sizeof(arg)) | |
1348 | break; | |
1349 | ||
1350 | if (bit >= 0 && bit < NCAPINTS * 32) { | |
1351 | pr_cont(" " X86_CAP_FMT, x86_cap_flag(bit)); | |
1352 | setup_clear_cpu_cap(bit); | |
1353 | } | |
1354 | } while (res == 2); | |
1355 | pr_cont("\n"); | |
1356 | } | |
1357 | ||
34048c9e PC |
1358 | /* |
1359 | * Do minimum CPU detection early. | |
1360 | * Fields really needed: vendor, cpuid_level, family, model, mask, | |
1361 | * cache alignment. | |
1362 | * The others are not touched to avoid unwanted side effects. | |
1363 | * | |
a1652bb8 JD |
1364 | * WARNING: this function is only called on the boot CPU. Don't add code |
1365 | * here that is supposed to run on all CPUs. | |
34048c9e | 1366 | */ |
3da99c97 | 1367 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) |
d7cd5611 | 1368 | { |
6627d242 YL |
1369 | #ifdef CONFIG_X86_64 |
1370 | c->x86_clflush_size = 64; | |
13c6c532 JB |
1371 | c->x86_phys_bits = 36; |
1372 | c->x86_virt_bits = 48; | |
6627d242 | 1373 | #else |
d4387bd3 | 1374 | c->x86_clflush_size = 32; |
13c6c532 JB |
1375 | c->x86_phys_bits = 32; |
1376 | c->x86_virt_bits = 32; | |
6627d242 | 1377 | #endif |
0a488a53 | 1378 | c->x86_cache_alignment = c->x86_clflush_size; |
d7cd5611 | 1379 | |
0e96f31e | 1380 | memset(&c->x86_capability, 0, sizeof(c->x86_capability)); |
0a488a53 | 1381 | c->extended_cpuid_level = 0; |
d7cd5611 | 1382 | |
2893cc8f MW |
1383 | if (!have_cpuid_p()) |
1384 | identify_cpu_without_cpuid(c); | |
1385 | ||
aef93c8b | 1386 | /* cyrix could have cpuid enabled via c_identify()*/ |
05fb3c19 AL |
1387 | if (have_cpuid_p()) { |
1388 | cpu_detect(c); | |
1389 | get_cpu_vendor(c); | |
1390 | get_cpu_cap(c); | |
d94a155c | 1391 | get_cpu_address_sizes(c); |
78d1b296 | 1392 | setup_force_cpu_cap(X86_FEATURE_CPUID); |
1ef5423a | 1393 | cpu_parse_early_param(); |
d7cd5611 | 1394 | |
05fb3c19 AL |
1395 | if (this_cpu->c_early_init) |
1396 | this_cpu->c_early_init(c); | |
12cf105c | 1397 | |
05fb3c19 AL |
1398 | c->cpu_index = 0; |
1399 | filter_cpuid_features(c, false); | |
093af8d7 | 1400 | |
05fb3c19 AL |
1401 | if (this_cpu->c_bsp_init) |
1402 | this_cpu->c_bsp_init(c); | |
78d1b296 | 1403 | } else { |
78d1b296 | 1404 | setup_clear_cpu_cap(X86_FEATURE_CPUID); |
05fb3c19 | 1405 | } |
c3b83598 BP |
1406 | |
1407 | setup_force_cpu_cap(X86_FEATURE_ALWAYS); | |
a89f040f | 1408 | |
4a28bfe3 | 1409 | cpu_set_bug_bits(c); |
99c6fa25 | 1410 | |
ebb1064e | 1411 | sld_setup(c); |
6650cdd9 | 1412 | |
db52ef74 | 1413 | fpu__init_system(c); |
b8b7abae | 1414 | |
939ef713 CB |
1415 | init_sigframe_size(); |
1416 | ||
b8b7abae AL |
1417 | #ifdef CONFIG_X86_32 |
1418 | /* | |
1419 | * Regardless of whether PCID is enumerated, the SDM says | |
1420 | * that it can't be enabled in 32-bit mode. | |
1421 | */ | |
1422 | setup_clear_cpu_cap(X86_FEATURE_PCID); | |
1423 | #endif | |
372fddf7 KS |
1424 | |
1425 | /* | |
1426 | * Later in the boot process pgtable_l5_enabled() relies on | |
1427 | * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not | |
1428 | * enabled by this point we need to clear the feature bit to avoid | |
1429 | * false-positives at the later stage. | |
1430 | * | |
1431 | * pgtable_l5_enabled() can be false here for several reasons: | |
1432 | * - 5-level paging is disabled compile-time; | |
1433 | * - it's 32-bit kernel; | |
1434 | * - machine doesn't support 5-level paging; | |
1435 | * - user specified 'no5lvl' in kernel command line. | |
1436 | */ | |
1437 | if (!pgtable_l5_enabled()) | |
1438 | setup_clear_cpu_cap(X86_FEATURE_LA57); | |
8990cac6 | 1439 | |
9b3661cd | 1440 | detect_nopl(); |
d7cd5611 RR |
1441 | } |
1442 | ||
9d31d35b YL |
1443 | void __init early_cpu_init(void) |
1444 | { | |
02dde8b4 | 1445 | const struct cpu_dev *const *cdev; |
10a434fc YL |
1446 | int count = 0; |
1447 | ||
ac23f253 | 1448 | #ifdef CONFIG_PROCESSOR_SELECT |
1b74dde7 | 1449 | pr_info("KERNEL supported cpus:\n"); |
31c997ca IM |
1450 | #endif |
1451 | ||
10a434fc | 1452 | for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { |
02dde8b4 | 1453 | const struct cpu_dev *cpudev = *cdev; |
9d31d35b | 1454 | |
10a434fc YL |
1455 | if (count >= X86_VENDOR_NUM) |
1456 | break; | |
1457 | cpu_devs[count] = cpudev; | |
1458 | count++; | |
1459 | ||
ac23f253 | 1460 | #ifdef CONFIG_PROCESSOR_SELECT |
31c997ca IM |
1461 | { |
1462 | unsigned int j; | |
1463 | ||
1464 | for (j = 0; j < 2; j++) { | |
1465 | if (!cpudev->c_ident[j]) | |
1466 | continue; | |
1b74dde7 | 1467 | pr_info(" %s %s\n", cpudev->c_vendor, |
31c997ca IM |
1468 | cpudev->c_ident[j]); |
1469 | } | |
10a434fc | 1470 | } |
0388423d | 1471 | #endif |
10a434fc | 1472 | } |
9d31d35b | 1473 | early_identify_cpu(&boot_cpu_data); |
d7cd5611 | 1474 | } |
093af8d7 | 1475 | |
415de440 | 1476 | static bool detect_null_seg_behavior(void) |
7a5d6704 | 1477 | { |
58a5aac5 | 1478 | /* |
7a5d6704 AL |
1479 | * Empirically, writing zero to a segment selector on AMD does |
1480 | * not clear the base, whereas writing zero to a segment | |
1481 | * selector on Intel does clear the base. Intel's behavior | |
1482 | * allows slightly faster context switches in the common case | |
1483 | * where GS is unused by the prev and next threads. | |
58a5aac5 | 1484 | * |
7a5d6704 | 1485 | * Since neither vendor documents this anywhere that I can see, |
d9f6e12f | 1486 | * detect it directly instead of hard-coding the choice by |
7a5d6704 AL |
1487 | * vendor. |
1488 | * | |
1489 | * I've designated AMD's behavior as the "bug" because it's | |
1490 | * counterintuitive and less friendly. | |
58a5aac5 | 1491 | */ |
7a5d6704 AL |
1492 | |
1493 | unsigned long old_base, tmp; | |
1494 | rdmsrl(MSR_FS_BASE, old_base); | |
1495 | wrmsrl(MSR_FS_BASE, 1); | |
1496 | loadsegment(fs, 0); | |
1497 | rdmsrl(MSR_FS_BASE, tmp); | |
7a5d6704 | 1498 | wrmsrl(MSR_FS_BASE, old_base); |
415de440 JM |
1499 | return tmp == 0; |
1500 | } | |
1501 | ||
1502 | void check_null_seg_clears_base(struct cpuinfo_x86 *c) | |
1503 | { | |
1504 | /* BUG_NULL_SEG is only relevant with 64bit userspace */ | |
1505 | if (!IS_ENABLED(CONFIG_X86_64)) | |
1506 | return; | |
1507 | ||
1508 | /* Zen3 CPUs advertise Null Selector Clears Base in CPUID. */ | |
1509 | if (c->extended_cpuid_level >= 0x80000021 && | |
1510 | cpuid_eax(0x80000021) & BIT(6)) | |
1511 | return; | |
1512 | ||
1513 | /* | |
1514 | * CPUID bit above wasn't set. If this kernel is still running | |
1515 | * as a HV guest, then the HV has decided not to advertize | |
1516 | * that CPUID bit for whatever reason. For example, one | |
1517 | * member of the migration pool might be vulnerable. Which | |
1518 | * means, the bug is present: set the BUG flag and return. | |
1519 | */ | |
1520 | if (cpu_has(c, X86_FEATURE_HYPERVISOR)) { | |
1521 | set_cpu_bug(c, X86_BUG_NULL_SEG); | |
1522 | return; | |
1523 | } | |
1524 | ||
1525 | /* | |
1526 | * Zen2 CPUs also have this behaviour, but no CPUID bit. | |
1527 | * 0x18 is the respective family for Hygon. | |
1528 | */ | |
1529 | if ((c->x86 == 0x17 || c->x86 == 0x18) && | |
1530 | detect_null_seg_behavior()) | |
1531 | return; | |
1532 | ||
1533 | /* All the remaining ones are affected */ | |
1534 | set_cpu_bug(c, X86_BUG_NULL_SEG); | |
d7cd5611 RR |
1535 | } |
1536 | ||
148f9bb8 | 1537 | static void generic_identify(struct cpuinfo_x86 *c) |
1da177e4 | 1538 | { |
aef93c8b | 1539 | c->extended_cpuid_level = 0; |
1da177e4 | 1540 | |
3da99c97 | 1541 | if (!have_cpuid_p()) |
aef93c8b | 1542 | identify_cpu_without_cpuid(c); |
1d67953f | 1543 | |
aef93c8b | 1544 | /* cyrix could have cpuid enabled via c_identify()*/ |
a9853dd6 | 1545 | if (!have_cpuid_p()) |
aef93c8b | 1546 | return; |
1da177e4 | 1547 | |
3da99c97 | 1548 | cpu_detect(c); |
1da177e4 | 1549 | |
3da99c97 | 1550 | get_cpu_vendor(c); |
1da177e4 | 1551 | |
3da99c97 | 1552 | get_cpu_cap(c); |
1da177e4 | 1553 | |
d94a155c KS |
1554 | get_cpu_address_sizes(c); |
1555 | ||
3da99c97 YL |
1556 | if (c->cpuid_level >= 0x00000001) { |
1557 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; | |
b89d3b3e | 1558 | #ifdef CONFIG_X86_32 |
c8e56d20 | 1559 | # ifdef CONFIG_SMP |
cb8cc442 | 1560 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
b89d3b3e | 1561 | # else |
3da99c97 | 1562 | c->apicid = c->initial_apicid; |
b89d3b3e YL |
1563 | # endif |
1564 | #endif | |
b89d3b3e | 1565 | c->phys_proc_id = c->initial_apicid; |
3da99c97 | 1566 | } |
1da177e4 | 1567 | |
1b05d60d | 1568 | get_model_name(c); /* Default name */ |
1da177e4 | 1569 | |
0230bb03 AL |
1570 | /* |
1571 | * ESPFIX is a strange bug. All real CPUs have it. Paravirt | |
1572 | * systems that run Linux at CPL > 0 may or may not have the | |
1573 | * issue, but, even if they have the issue, there's absolutely | |
1574 | * nothing we can do about it because we can't use the real IRET | |
1575 | * instruction. | |
1576 | * | |
1577 | * NB: For the time being, only 32-bit kernels support | |
1578 | * X86_BUG_ESPFIX as such. 64-bit kernels directly choose | |
1579 | * whether to apply espfix using paravirt hooks. If any | |
1580 | * non-paravirt system ever shows up that does *not* have the | |
1581 | * ESPFIX issue, we can change this. | |
1582 | */ | |
1583 | #ifdef CONFIG_X86_32 | |
0230bb03 | 1584 | set_cpu_bug(c, X86_BUG_ESPFIX); |
0230bb03 | 1585 | #endif |
1da177e4 | 1586 | } |
1da177e4 | 1587 | |
d49597fd | 1588 | /* |
9d85eb91 TG |
1589 | * Validate that ACPI/mptables have the same information about the |
1590 | * effective APIC id and update the package map. | |
d49597fd | 1591 | */ |
9d85eb91 | 1592 | static void validate_apic_and_package_id(struct cpuinfo_x86 *c) |
d49597fd TG |
1593 | { |
1594 | #ifdef CONFIG_SMP | |
9d85eb91 | 1595 | unsigned int apicid, cpu = smp_processor_id(); |
d49597fd TG |
1596 | |
1597 | apicid = apic->cpu_present_to_apicid(cpu); | |
d49597fd | 1598 | |
9d85eb91 TG |
1599 | if (apicid != c->apicid) { |
1600 | pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n", | |
d49597fd | 1601 | cpu, apicid, c->initial_apicid); |
d49597fd | 1602 | } |
9d85eb91 | 1603 | BUG_ON(topology_update_package_map(c->phys_proc_id, cpu)); |
212bf4fd | 1604 | BUG_ON(topology_update_die_map(c->cpu_die_id, cpu)); |
d49597fd TG |
1605 | #else |
1606 | c->logical_proc_id = 0; | |
1607 | #endif | |
1608 | } | |
1609 | ||
1da177e4 LT |
1610 | /* |
1611 | * This does the hard work of actually picking apart the CPU stuff... | |
1612 | */ | |
148f9bb8 | 1613 | static void identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
1614 | { |
1615 | int i; | |
1616 | ||
1617 | c->loops_per_jiffy = loops_per_jiffy; | |
24dbc600 | 1618 | c->x86_cache_size = 0; |
1da177e4 | 1619 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
b399151c | 1620 | c->x86_model = c->x86_stepping = 0; /* So far unknown... */ |
1da177e4 LT |
1621 | c->x86_vendor_id[0] = '\0'; /* Unset */ |
1622 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 1623 | c->x86_max_cores = 1; |
102bbe3a | 1624 | c->x86_coreid_bits = 0; |
79a8b9aa | 1625 | c->cu_id = 0xff; |
11fdd252 | 1626 | #ifdef CONFIG_X86_64 |
102bbe3a | 1627 | c->x86_clflush_size = 64; |
13c6c532 JB |
1628 | c->x86_phys_bits = 36; |
1629 | c->x86_virt_bits = 48; | |
102bbe3a YL |
1630 | #else |
1631 | c->cpuid_level = -1; /* CPUID not detected */ | |
770d132f | 1632 | c->x86_clflush_size = 32; |
13c6c532 JB |
1633 | c->x86_phys_bits = 32; |
1634 | c->x86_virt_bits = 32; | |
102bbe3a YL |
1635 | #endif |
1636 | c->x86_cache_alignment = c->x86_clflush_size; | |
0e96f31e | 1637 | memset(&c->x86_capability, 0, sizeof(c->x86_capability)); |
b47ce1fe SC |
1638 | #ifdef CONFIG_X86_VMX_FEATURE_NAMES |
1639 | memset(&c->vmx_capability, 0, sizeof(c->vmx_capability)); | |
1640 | #endif | |
1da177e4 | 1641 | |
1da177e4 LT |
1642 | generic_identify(c); |
1643 | ||
3898534d | 1644 | if (this_cpu->c_identify) |
1da177e4 LT |
1645 | this_cpu->c_identify(c); |
1646 | ||
6a6256f9 | 1647 | /* Clear/Set all flags overridden by options, after probe */ |
8bf1ebca | 1648 | apply_forced_caps(c); |
2759c328 | 1649 | |
102bbe3a | 1650 | #ifdef CONFIG_X86_64 |
cb8cc442 | 1651 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
102bbe3a YL |
1652 | #endif |
1653 | ||
1da177e4 LT |
1654 | /* |
1655 | * Vendor-specific initialization. In this section we | |
1656 | * canonicalize the feature flags, meaning if there are | |
1657 | * features a certain CPU supports which CPUID doesn't | |
1658 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
1659 | * we handle them here. | |
1660 | * | |
1661 | * At the end of this section, c->x86_capability better | |
1662 | * indicate the features this CPU genuinely supports! | |
1663 | */ | |
1664 | if (this_cpu->c_init) | |
1665 | this_cpu->c_init(c); | |
1666 | ||
1667 | /* Disable the PN if appropriate */ | |
1668 | squash_the_stupid_serial_number(c); | |
1669 | ||
aa35f896 | 1670 | /* Set up SMEP/SMAP/UMIP */ |
b2cc2a07 PA |
1671 | setup_smep(c); |
1672 | setup_smap(c); | |
aa35f896 | 1673 | setup_umip(c); |
b2cc2a07 | 1674 | |
dd649bd0 | 1675 | /* Enable FSGSBASE instructions if available. */ |
742c45c3 | 1676 | if (cpu_has(c, X86_FEATURE_FSGSBASE)) { |
b745cfba | 1677 | cr4_set_bits(X86_CR4_FSGSBASE); |
742c45c3 AK |
1678 | elf_hwcap2 |= HWCAP2_FSGSBASE; |
1679 | } | |
dd649bd0 | 1680 | |
1da177e4 | 1681 | /* |
0f3fa48a IM |
1682 | * The vendor-specific functions might have changed features. |
1683 | * Now we do "generic changes." | |
1da177e4 LT |
1684 | */ |
1685 | ||
b38b0665 PA |
1686 | /* Filter out anything that depends on CPUID levels we don't have */ |
1687 | filter_cpuid_features(c, true); | |
1688 | ||
1da177e4 | 1689 | /* If the model name is still unset, do table lookup. */ |
34048c9e | 1690 | if (!c->x86_model_id[0]) { |
02dde8b4 | 1691 | const char *p; |
1da177e4 | 1692 | p = table_lookup_model(c); |
34048c9e | 1693 | if (p) |
1da177e4 LT |
1694 | strcpy(c->x86_model_id, p); |
1695 | else | |
1696 | /* Last resort... */ | |
1697 | sprintf(c->x86_model_id, "%02x/%02x", | |
54a20f8c | 1698 | c->x86, c->x86_model); |
1da177e4 LT |
1699 | } |
1700 | ||
102bbe3a YL |
1701 | #ifdef CONFIG_X86_64 |
1702 | detect_ht(c); | |
1703 | #endif | |
1704 | ||
49d859d7 | 1705 | x86_init_rdrand(c); |
06976945 | 1706 | setup_pku(c); |
3e0c3737 YL |
1707 | |
1708 | /* | |
6a6256f9 | 1709 | * Clear/Set all flags overridden by options, need do it |
3e0c3737 YL |
1710 | * before following smp all cpus cap AND. |
1711 | */ | |
8bf1ebca | 1712 | apply_forced_caps(c); |
3e0c3737 | 1713 | |
1da177e4 LT |
1714 | /* |
1715 | * On SMP, boot_cpu_data holds the common feature set between | |
1716 | * all CPUs; so make sure that we indicate which features are | |
1717 | * common between the CPUs. The first time this routine gets | |
1718 | * executed, c == &boot_cpu_data. | |
1719 | */ | |
34048c9e | 1720 | if (c != &boot_cpu_data) { |
1da177e4 | 1721 | /* AND the already accumulated flags with these */ |
9d31d35b | 1722 | for (i = 0; i < NCAPINTS; i++) |
1da177e4 | 1723 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; |
65fc985b BP |
1724 | |
1725 | /* OR, i.e. replicate the bug flags */ | |
1726 | for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) | |
1727 | c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; | |
1da177e4 LT |
1728 | } |
1729 | ||
0dcab41d TL |
1730 | ppin_init(c); |
1731 | ||
1da177e4 | 1732 | /* Init Machine Check Exception if available. */ |
5e09954a | 1733 | mcheck_cpu_init(c); |
30d432df AK |
1734 | |
1735 | select_idle_routine(c); | |
102bbe3a | 1736 | |
de2d9445 | 1737 | #ifdef CONFIG_NUMA |
102bbe3a YL |
1738 | numa_add_cpu(smp_processor_id()); |
1739 | #endif | |
a6c4e076 | 1740 | } |
31ab269a | 1741 | |
8b6c0ab1 IM |
1742 | /* |
1743 | * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions | |
1744 | * on 32-bit kernels: | |
1745 | */ | |
cfda7bb9 AL |
1746 | #ifdef CONFIG_X86_32 |
1747 | void enable_sep_cpu(void) | |
1748 | { | |
8b6c0ab1 IM |
1749 | struct tss_struct *tss; |
1750 | int cpu; | |
cfda7bb9 | 1751 | |
b3edfda4 BP |
1752 | if (!boot_cpu_has(X86_FEATURE_SEP)) |
1753 | return; | |
1754 | ||
8b6c0ab1 | 1755 | cpu = get_cpu(); |
c482feef | 1756 | tss = &per_cpu(cpu_tss_rw, cpu); |
8b6c0ab1 | 1757 | |
8b6c0ab1 | 1758 | /* |
cf9328cc AL |
1759 | * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- |
1760 | * see the big comment in struct x86_hw_tss's definition. | |
8b6c0ab1 | 1761 | */ |
cfda7bb9 AL |
1762 | |
1763 | tss->x86_tss.ss1 = __KERNEL_CS; | |
8b6c0ab1 | 1764 | wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); |
4fe2d8b1 | 1765 | wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0); |
4c8cd0c5 | 1766 | wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); |
8b6c0ab1 | 1767 | |
cfda7bb9 AL |
1768 | put_cpu(); |
1769 | } | |
e04d645f GC |
1770 | #endif |
1771 | ||
a6c4e076 JF |
1772 | void __init identify_boot_cpu(void) |
1773 | { | |
1774 | identify_cpu(&boot_cpu_data); | |
102bbe3a | 1775 | #ifdef CONFIG_X86_32 |
a6c4e076 | 1776 | sysenter_setup(); |
6fe940d6 | 1777 | enable_sep_cpu(); |
102bbe3a | 1778 | #endif |
5b556332 | 1779 | cpu_detect_tlb(&boot_cpu_data); |
873d50d5 | 1780 | setup_cr_pinning(); |
95c5824f PG |
1781 | |
1782 | tsx_init(); | |
a6c4e076 | 1783 | } |
3b520b23 | 1784 | |
148f9bb8 | 1785 | void identify_secondary_cpu(struct cpuinfo_x86 *c) |
a6c4e076 JF |
1786 | { |
1787 | BUG_ON(c == &boot_cpu_data); | |
1788 | identify_cpu(c); | |
102bbe3a | 1789 | #ifdef CONFIG_X86_32 |
a6c4e076 | 1790 | enable_sep_cpu(); |
102bbe3a | 1791 | #endif |
a6c4e076 | 1792 | mtrr_ap_init(); |
9d85eb91 | 1793 | validate_apic_and_package_id(c); |
77243971 | 1794 | x86_spec_ctrl_setup_ap(); |
7e5b3c26 | 1795 | update_srbds_msr(); |
1da177e4 LT |
1796 | } |
1797 | ||
191679fd AK |
1798 | static __init int setup_noclflush(char *arg) |
1799 | { | |
840d2830 | 1800 | setup_clear_cpu_cap(X86_FEATURE_CLFLUSH); |
da4aaa7d | 1801 | setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT); |
191679fd AK |
1802 | return 1; |
1803 | } | |
1804 | __setup("noclflush", setup_noclflush); | |
1805 | ||
148f9bb8 | 1806 | void print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 | 1807 | { |
02dde8b4 | 1808 | const char *vendor = NULL; |
1da177e4 | 1809 | |
0f3fa48a | 1810 | if (c->x86_vendor < X86_VENDOR_NUM) { |
1da177e4 | 1811 | vendor = this_cpu->c_vendor; |
0f3fa48a IM |
1812 | } else { |
1813 | if (c->cpuid_level >= 0) | |
1814 | vendor = c->x86_vendor_id; | |
1815 | } | |
1da177e4 | 1816 | |
bd32a8cf | 1817 | if (vendor && !strstr(c->x86_model_id, vendor)) |
1b74dde7 | 1818 | pr_cont("%s ", vendor); |
1da177e4 | 1819 | |
9d31d35b | 1820 | if (c->x86_model_id[0]) |
1b74dde7 | 1821 | pr_cont("%s", c->x86_model_id); |
1da177e4 | 1822 | else |
1b74dde7 | 1823 | pr_cont("%d86", c->x86); |
1da177e4 | 1824 | |
1b74dde7 | 1825 | pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model); |
924e101a | 1826 | |
b399151c JZ |
1827 | if (c->x86_stepping || c->cpuid_level >= 0) |
1828 | pr_cont(", stepping: 0x%x)\n", c->x86_stepping); | |
1da177e4 | 1829 | else |
1b74dde7 | 1830 | pr_cont(")\n"); |
1da177e4 LT |
1831 | } |
1832 | ||
0c2a3913 | 1833 | /* |
ce38f038 TG |
1834 | * clearcpuid= was already parsed in cpu_parse_early_param(). This dummy |
1835 | * function prevents it from becoming an environment variable for init. | |
0c2a3913 AK |
1836 | */ |
1837 | static __init int setup_clearcpuid(char *arg) | |
ac72e788 | 1838 | { |
ac72e788 AK |
1839 | return 1; |
1840 | } | |
0c2a3913 | 1841 | __setup("clearcpuid=", setup_clearcpuid); |
ac72e788 | 1842 | |
d5494d4f | 1843 | #ifdef CONFIG_X86_64 |
e6401c13 AL |
1844 | DEFINE_PER_CPU_FIRST(struct fixed_percpu_data, |
1845 | fixed_percpu_data) __aligned(PAGE_SIZE) __visible; | |
1846 | EXPORT_PER_CPU_SYMBOL_GPL(fixed_percpu_data); | |
0f3fa48a | 1847 | |
bdf977b3 | 1848 | /* |
a7fcf28d AL |
1849 | * The following percpu variables are hot. Align current_task to |
1850 | * cacheline size such that they fall in the same cacheline. | |
bdf977b3 TH |
1851 | */ |
1852 | DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = | |
1853 | &init_task; | |
1854 | EXPORT_PER_CPU_SYMBOL(current_task); | |
d5494d4f | 1855 | |
951c2a51 | 1856 | DEFINE_PER_CPU(void *, hardirq_stack_ptr); |
e7f89001 | 1857 | DEFINE_PER_CPU(bool, hardirq_stack_inuse); |
d5494d4f | 1858 | |
c2daa3be PZ |
1859 | DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; |
1860 | EXPORT_PER_CPU_SYMBOL(__preempt_count); | |
1861 | ||
1591584e LJ |
1862 | DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = TOP_OF_INIT_STACK; |
1863 | ||
9c7e2634 AK |
1864 | static void wrmsrl_cstar(unsigned long val) |
1865 | { | |
1866 | /* | |
1867 | * Intel CPUs do not support 32-bit SYSCALL. Writing to MSR_CSTAR | |
1868 | * is so far ignored by the CPU, but raises a #VE trap in a TDX | |
1869 | * guest. Avoid the pointless write on all Intel CPUs. | |
1870 | */ | |
1871 | if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) | |
1872 | wrmsrl(MSR_CSTAR, val); | |
1873 | } | |
1874 | ||
d5494d4f YL |
1875 | /* May not be marked __init: used by software suspend */ |
1876 | void syscall_init(void) | |
1da177e4 | 1877 | { |
31ac34ca | 1878 | wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); |
bf904d27 | 1879 | wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64); |
d56fe4bf IM |
1880 | |
1881 | #ifdef CONFIG_IA32_EMULATION | |
9c7e2634 | 1882 | wrmsrl_cstar((unsigned long)entry_SYSCALL_compat); |
a76c7f46 | 1883 | /* |
487d1edb DV |
1884 | * This only works on Intel CPUs. |
1885 | * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. | |
1886 | * This does not cause SYSENTER to jump to the wrong location, because | |
1887 | * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). | |
a76c7f46 DV |
1888 | */ |
1889 | wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); | |
8e6b65a1 | 1890 | wrmsrl_safe(MSR_IA32_SYSENTER_ESP, |
1891 | (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1)); | |
4c8cd0c5 | 1892 | wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); |
d56fe4bf | 1893 | #else |
9c7e2634 | 1894 | wrmsrl_cstar((unsigned long)ignore_sysret); |
6b51311c | 1895 | wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); |
d56fe4bf IM |
1896 | wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); |
1897 | wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); | |
d5494d4f | 1898 | #endif |
03ae5768 | 1899 | |
6de4ac1d PAI |
1900 | /* |
1901 | * Flags to clear on syscall; clear as much as possible | |
1902 | * to minimize user space-kernel interference. | |
1903 | */ | |
d5494d4f | 1904 | wrmsrl(MSR_SYSCALL_MASK, |
6de4ac1d PAI |
1905 | X86_EFLAGS_CF|X86_EFLAGS_PF|X86_EFLAGS_AF| |
1906 | X86_EFLAGS_ZF|X86_EFLAGS_SF|X86_EFLAGS_TF| | |
1907 | X86_EFLAGS_IF|X86_EFLAGS_DF|X86_EFLAGS_OF| | |
1908 | X86_EFLAGS_IOPL|X86_EFLAGS_NT|X86_EFLAGS_RF| | |
1909 | X86_EFLAGS_AC|X86_EFLAGS_ID); | |
1da177e4 | 1910 | } |
62111195 | 1911 | |
0f3fa48a | 1912 | #else /* CONFIG_X86_64 */ |
d5494d4f | 1913 | |
bdf977b3 TH |
1914 | DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; |
1915 | EXPORT_PER_CPU_SYMBOL(current_task); | |
c2daa3be PZ |
1916 | DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; |
1917 | EXPORT_PER_CPU_SYMBOL(__preempt_count); | |
bdf977b3 | 1918 | |
a7fcf28d AL |
1919 | /* |
1920 | * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find | |
1921 | * the top of the kernel stack. Use an extra percpu variable to track the | |
1922 | * top of the kernel stack directly. | |
1923 | */ | |
1924 | DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = | |
1925 | (unsigned long)&init_thread_union + THREAD_SIZE; | |
1926 | EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack); | |
1927 | ||
050e9baa | 1928 | #ifdef CONFIG_STACKPROTECTOR |
3fb0fdb3 AL |
1929 | DEFINE_PER_CPU(unsigned long, __stack_chk_guard); |
1930 | EXPORT_PER_CPU_SYMBOL(__stack_chk_guard); | |
60a5317f | 1931 | #endif |
d5494d4f | 1932 | |
0f3fa48a | 1933 | #endif /* CONFIG_X86_64 */ |
c5413fbe | 1934 | |
9766cdbc JSR |
1935 | /* |
1936 | * Clear all 6 debug registers: | |
1937 | */ | |
1938 | static void clear_all_debug_regs(void) | |
1939 | { | |
1940 | int i; | |
1941 | ||
1942 | for (i = 0; i < 8; i++) { | |
1943 | /* Ignore db4, db5 */ | |
1944 | if ((i == 4) || (i == 5)) | |
1945 | continue; | |
1946 | ||
1947 | set_debugreg(0, i); | |
1948 | } | |
1949 | } | |
c5413fbe | 1950 | |
0bb9fef9 JW |
1951 | #ifdef CONFIG_KGDB |
1952 | /* | |
1953 | * Restore debug regs if using kgdbwait and you have a kernel debugger | |
1954 | * connection established. | |
1955 | */ | |
1956 | static void dbg_restore_debug_regs(void) | |
1957 | { | |
1958 | if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) | |
1959 | arch_kgdb_ops.correct_hw_break(); | |
1960 | } | |
1961 | #else /* ! CONFIG_KGDB */ | |
1962 | #define dbg_restore_debug_regs() | |
1963 | #endif /* ! CONFIG_KGDB */ | |
1964 | ||
ce4b1b16 IM |
1965 | static void wait_for_master_cpu(int cpu) |
1966 | { | |
1967 | #ifdef CONFIG_SMP | |
1968 | /* | |
1969 | * wait for ACK from master CPU before continuing | |
1970 | * with AP initialization | |
1971 | */ | |
1972 | WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)); | |
1973 | while (!cpumask_test_cpu(cpu, cpu_callout_mask)) | |
1974 | cpu_relax(); | |
1975 | #endif | |
1976 | } | |
1977 | ||
b2e2ba57 | 1978 | #ifdef CONFIG_X86_64 |
505b7899 | 1979 | static inline void setup_getcpu(int cpu) |
b2e2ba57 | 1980 | { |
22245bdf | 1981 | unsigned long cpudata = vdso_encode_cpunode(cpu, early_cpu_to_node(cpu)); |
b2e2ba57 CB |
1982 | struct desc_struct d = { }; |
1983 | ||
b6b4fbd9 | 1984 | if (boot_cpu_has(X86_FEATURE_RDTSCP) || boot_cpu_has(X86_FEATURE_RDPID)) |
fc48a6d1 | 1985 | wrmsr(MSR_TSC_AUX, cpudata, 0); |
b2e2ba57 CB |
1986 | |
1987 | /* Store CPU and node number in limit. */ | |
1988 | d.limit0 = cpudata; | |
1989 | d.limit1 = cpudata >> 16; | |
1990 | ||
1991 | d.type = 5; /* RO data, expand down, accessed */ | |
1992 | d.dpl = 3; /* Visible to user code */ | |
1993 | d.s = 1; /* Not a system segment */ | |
1994 | d.p = 1; /* Present */ | |
1995 | d.d = 1; /* 32-bit */ | |
1996 | ||
22245bdf | 1997 | write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_CPUNODE, &d, DESCTYPE_S); |
b2e2ba57 | 1998 | } |
505b7899 TG |
1999 | |
2000 | static inline void ucode_cpu_init(int cpu) | |
2001 | { | |
2002 | if (cpu) | |
2003 | load_ucode_ap(); | |
2004 | } | |
2005 | ||
2006 | static inline void tss_setup_ist(struct tss_struct *tss) | |
2007 | { | |
2008 | /* Set up the per-CPU TSS IST stacks */ | |
2009 | tss->x86_tss.ist[IST_INDEX_DF] = __this_cpu_ist_top_va(DF); | |
2010 | tss->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI); | |
2011 | tss->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB); | |
2012 | tss->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE); | |
02772fb9 JR |
2013 | /* Only mapped when SEV-ES is active */ |
2014 | tss->x86_tss.ist[IST_INDEX_VC] = __this_cpu_ist_top_va(VC); | |
505b7899 TG |
2015 | } |
2016 | ||
505b7899 TG |
2017 | #else /* CONFIG_X86_64 */ |
2018 | ||
2019 | static inline void setup_getcpu(int cpu) { } | |
2020 | ||
2021 | static inline void ucode_cpu_init(int cpu) | |
2022 | { | |
2023 | show_ucode_info_early(); | |
2024 | } | |
2025 | ||
2026 | static inline void tss_setup_ist(struct tss_struct *tss) { } | |
2027 | ||
505b7899 | 2028 | #endif /* !CONFIG_X86_64 */ |
b2e2ba57 | 2029 | |
111e7b15 TG |
2030 | static inline void tss_setup_io_bitmap(struct tss_struct *tss) |
2031 | { | |
2032 | tss->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET_INVALID; | |
2033 | ||
2034 | #ifdef CONFIG_X86_IOPL_IOPERM | |
2035 | tss->io_bitmap.prev_max = 0; | |
2036 | tss->io_bitmap.prev_sequence = 0; | |
2037 | memset(tss->io_bitmap.bitmap, 0xff, sizeof(tss->io_bitmap.bitmap)); | |
2038 | /* | |
2039 | * Invalidate the extra array entry past the end of the all | |
2040 | * permission bitmap as required by the hardware. | |
2041 | */ | |
2042 | tss->io_bitmap.mapall[IO_BITMAP_LONGS] = ~0UL; | |
b2e2ba57 | 2043 | #endif |
111e7b15 | 2044 | } |
b2e2ba57 | 2045 | |
520d0308 JR |
2046 | /* |
2047 | * Setup everything needed to handle exceptions from the IDT, including the IST | |
2048 | * exceptions which use paranoid_entry(). | |
2049 | */ | |
2050 | void cpu_init_exception_handling(void) | |
2051 | { | |
2052 | struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw); | |
2053 | int cpu = raw_smp_processor_id(); | |
2054 | ||
2055 | /* paranoid_entry() gets the CPU number from the GDT */ | |
2056 | setup_getcpu(cpu); | |
2057 | ||
2058 | /* IST vectors need TSS to be set up. */ | |
2059 | tss_setup_ist(tss); | |
2060 | tss_setup_io_bitmap(tss); | |
2061 | set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); | |
2062 | ||
2063 | load_TR_desc(); | |
2064 | ||
2065 | /* Finally load the IDT */ | |
2066 | load_current_idt(); | |
2067 | } | |
2068 | ||
d2cbcc49 RR |
2069 | /* |
2070 | * cpu_init() initializes state that is per-CPU. Some data is already | |
b1efd0ff BP |
2071 | * initialized (naturally) in the bootstrap process, such as the GDT. We |
2072 | * reload it nevertheless, this function acts as a 'CPU state barrier', | |
2073 | * nothing should get across. | |
d2cbcc49 | 2074 | */ |
148f9bb8 | 2075 | void cpu_init(void) |
1ba76586 | 2076 | { |
505b7899 | 2077 | struct task_struct *cur = current; |
f6ef7322 | 2078 | int cpu = raw_smp_processor_id(); |
1ba76586 | 2079 | |
ce4b1b16 IM |
2080 | wait_for_master_cpu(cpu); |
2081 | ||
505b7899 | 2082 | ucode_cpu_init(cpu); |
0f3fa48a | 2083 | |
e7a22c1e | 2084 | #ifdef CONFIG_NUMA |
27fd185f | 2085 | if (this_cpu_read(numa_node) == 0 && |
e534c7c5 LS |
2086 | early_cpu_to_node(cpu) != NUMA_NO_NODE) |
2087 | set_numa_node(early_cpu_to_node(cpu)); | |
e7a22c1e | 2088 | #endif |
2eaad1fd | 2089 | pr_debug("Initializing CPU#%d\n", cpu); |
1ba76586 | 2090 | |
505b7899 TG |
2091 | if (IS_ENABLED(CONFIG_X86_64) || cpu_feature_enabled(X86_FEATURE_VME) || |
2092 | boot_cpu_has(X86_FEATURE_TSC) || boot_cpu_has(X86_FEATURE_DE)) | |
2093 | cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); | |
1ba76586 YL |
2094 | |
2095 | /* | |
2096 | * Initialize the per-CPU GDT with the boot GDT, | |
2097 | * and set up the GDT descriptor: | |
2098 | */ | |
552be871 | 2099 | switch_to_new_gdt(cpu); |
1ba76586 | 2100 | |
505b7899 TG |
2101 | if (IS_ENABLED(CONFIG_X86_64)) { |
2102 | loadsegment(fs, 0); | |
2103 | memset(cur->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); | |
2104 | syscall_init(); | |
1ba76586 | 2105 | |
505b7899 TG |
2106 | wrmsrl(MSR_FS_BASE, 0); |
2107 | wrmsrl(MSR_KERNEL_GS_BASE, 0); | |
2108 | barrier(); | |
1ba76586 | 2109 | |
505b7899 | 2110 | x2apic_setup(); |
1ba76586 YL |
2111 | } |
2112 | ||
f1f10076 | 2113 | mmgrab(&init_mm); |
505b7899 TG |
2114 | cur->active_mm = &init_mm; |
2115 | BUG_ON(cur->mm); | |
72c0098d | 2116 | initialize_tlbstate_and_flush(); |
505b7899 | 2117 | enter_lazy_tlb(&init_mm, cur); |
1ba76586 | 2118 | |
505b7899 TG |
2119 | /* |
2120 | * sp0 points to the entry trampoline stack regardless of what task | |
2121 | * is running. | |
2122 | */ | |
4fe2d8b1 | 2123 | load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1)); |
20bb8344 | 2124 | |
37868fe1 | 2125 | load_mm_ldt(&init_mm); |
1ba76586 | 2126 | |
0bb9fef9 JW |
2127 | clear_all_debug_regs(); |
2128 | dbg_restore_debug_regs(); | |
1ba76586 | 2129 | |
dc4e0021 | 2130 | doublefault_init_cpu_tss(); |
505b7899 | 2131 | |
21c4cd10 | 2132 | fpu__init_cpu(); |
1ba76586 | 2133 | |
1ba76586 YL |
2134 | if (is_uv_system()) |
2135 | uv_cpu_init(); | |
69218e47 | 2136 | |
69218e47 | 2137 | load_fixmap_gdt(cpu); |
1ba76586 YL |
2138 | } |
2139 | ||
b1efd0ff BP |
2140 | #ifdef CONFIG_SMP |
2141 | void cpu_init_secondary(void) | |
2142 | { | |
2143 | /* | |
2144 | * Relies on the BP having set-up the IDT tables, which are loaded | |
2145 | * on this CPU in cpu_init_exception_handling(). | |
2146 | */ | |
2147 | cpu_init_exception_handling(); | |
2148 | cpu_init(); | |
2149 | } | |
2150 | #endif | |
2151 | ||
1008c52c BP |
2152 | /* |
2153 | * The microcode loader calls this upon late microcode load to recheck features, | |
2154 | * only when microcode has been updated. Caller holds microcode_mutex and CPU | |
2155 | * hotplug lock. | |
2156 | */ | |
2157 | void microcode_check(void) | |
2158 | { | |
42ca8082 BP |
2159 | struct cpuinfo_x86 info; |
2160 | ||
1008c52c | 2161 | perf_check_microcode(); |
42ca8082 BP |
2162 | |
2163 | /* Reload CPUID max function as it might've changed. */ | |
2164 | info.cpuid_level = cpuid_eax(0); | |
2165 | ||
2166 | /* | |
2167 | * Copy all capability leafs to pick up the synthetic ones so that | |
2168 | * memcmp() below doesn't fail on that. The ones coming from CPUID will | |
2169 | * get overwritten in get_cpu_cap(). | |
2170 | */ | |
2171 | memcpy(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability)); | |
2172 | ||
2173 | get_cpu_cap(&info); | |
2174 | ||
2175 | if (!memcmp(&info.x86_capability, &boot_cpu_data.x86_capability, sizeof(info.x86_capability))) | |
2176 | return; | |
2177 | ||
2178 | pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n"); | |
2179 | pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n"); | |
1008c52c | 2180 | } |
9c92374b TG |
2181 | |
2182 | /* | |
2183 | * Invoked from core CPU hotplug code after hotplug operations | |
2184 | */ | |
2185 | void arch_smt_update(void) | |
2186 | { | |
2187 | /* Handle the speculative execution misfeatures */ | |
2188 | cpu_bugs_smt_update(); | |
6a1cb5f5 TG |
2189 | /* Check whether IPI broadcasting can be enabled */ |
2190 | apic_smt_update(); | |
9c92374b | 2191 | } |