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Commit | Line | Data |
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f0fc4aff | 1 | #include <linux/bootmem.h> |
9766cdbc | 2 | #include <linux/linkage.h> |
f0fc4aff | 3 | #include <linux/bitops.h> |
9766cdbc | 4 | #include <linux/kernel.h> |
186f4360 | 5 | #include <linux/export.h> |
9766cdbc JSR |
6 | #include <linux/percpu.h> |
7 | #include <linux/string.h> | |
ee098e1a | 8 | #include <linux/ctype.h> |
1da177e4 | 9 | #include <linux/delay.h> |
68e21be2 | 10 | #include <linux/sched/mm.h> |
e6017571 | 11 | #include <linux/sched/clock.h> |
9164bb4a | 12 | #include <linux/sched/task.h> |
9766cdbc | 13 | #include <linux/init.h> |
0f46efeb | 14 | #include <linux/kprobes.h> |
9766cdbc | 15 | #include <linux/kgdb.h> |
1da177e4 | 16 | #include <linux/smp.h> |
9766cdbc | 17 | #include <linux/io.h> |
b51ef52d | 18 | #include <linux/syscore_ops.h> |
9766cdbc JSR |
19 | |
20 | #include <asm/stackprotector.h> | |
cdd6c482 | 21 | #include <asm/perf_event.h> |
1da177e4 | 22 | #include <asm/mmu_context.h> |
49d859d7 | 23 | #include <asm/archrandom.h> |
9766cdbc JSR |
24 | #include <asm/hypervisor.h> |
25 | #include <asm/processor.h> | |
1e02ce4c | 26 | #include <asm/tlbflush.h> |
f649e938 | 27 | #include <asm/debugreg.h> |
9766cdbc | 28 | #include <asm/sections.h> |
f40c3300 | 29 | #include <asm/vsyscall.h> |
8bdbd962 AC |
30 | #include <linux/topology.h> |
31 | #include <linux/cpumask.h> | |
9766cdbc | 32 | #include <asm/pgtable.h> |
60063497 | 33 | #include <linux/atomic.h> |
9766cdbc JSR |
34 | #include <asm/proto.h> |
35 | #include <asm/setup.h> | |
36 | #include <asm/apic.h> | |
37 | #include <asm/desc.h> | |
78f7f1e5 | 38 | #include <asm/fpu/internal.h> |
27b07da7 | 39 | #include <asm/mtrr.h> |
0274f955 | 40 | #include <asm/hwcap2.h> |
8bdbd962 | 41 | #include <linux/numa.h> |
9766cdbc | 42 | #include <asm/asm.h> |
0f6ff2bc | 43 | #include <asm/bugs.h> |
9766cdbc | 44 | #include <asm/cpu.h> |
a03a3e28 | 45 | #include <asm/mce.h> |
9766cdbc | 46 | #include <asm/msr.h> |
8d4a4300 | 47 | #include <asm/pat.h> |
d288e1cf FY |
48 | #include <asm/microcode.h> |
49 | #include <asm/microcode_intel.h> | |
e641f5f5 IM |
50 | |
51 | #ifdef CONFIG_X86_LOCAL_APIC | |
bdbcdd48 | 52 | #include <asm/uv/uv.h> |
1da177e4 LT |
53 | #endif |
54 | ||
55 | #include "cpu.h" | |
56 | ||
0274f955 GA |
57 | u32 elf_hwcap2 __read_mostly; |
58 | ||
c2d1cec1 | 59 | /* all of these masks are initialized in setup_cpu_local_masks() */ |
c2d1cec1 | 60 | cpumask_var_t cpu_initialized_mask; |
9766cdbc JSR |
61 | cpumask_var_t cpu_callout_mask; |
62 | cpumask_var_t cpu_callin_mask; | |
c2d1cec1 MT |
63 | |
64 | /* representing cpus for which sibling maps can be computed */ | |
65 | cpumask_var_t cpu_sibling_setup_mask; | |
66 | ||
2f2f52ba | 67 | /* correctly size the local cpu masks */ |
4369f1fb | 68 | void __init setup_cpu_local_masks(void) |
2f2f52ba BG |
69 | { |
70 | alloc_bootmem_cpumask_var(&cpu_initialized_mask); | |
71 | alloc_bootmem_cpumask_var(&cpu_callin_mask); | |
72 | alloc_bootmem_cpumask_var(&cpu_callout_mask); | |
73 | alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); | |
74 | } | |
75 | ||
148f9bb8 | 76 | static void default_init(struct cpuinfo_x86 *c) |
e8055139 OZ |
77 | { |
78 | #ifdef CONFIG_X86_64 | |
27c13ece | 79 | cpu_detect_cache_sizes(c); |
e8055139 OZ |
80 | #else |
81 | /* Not much we can do here... */ | |
82 | /* Check if at least it has cpuid */ | |
83 | if (c->cpuid_level == -1) { | |
84 | /* No cpuid. It must be an ancient CPU */ | |
85 | if (c->x86 == 4) | |
86 | strcpy(c->x86_model_id, "486"); | |
87 | else if (c->x86 == 3) | |
88 | strcpy(c->x86_model_id, "386"); | |
89 | } | |
90 | #endif | |
91 | } | |
92 | ||
148f9bb8 | 93 | static const struct cpu_dev default_cpu = { |
e8055139 OZ |
94 | .c_init = default_init, |
95 | .c_vendor = "Unknown", | |
96 | .c_x86_vendor = X86_VENDOR_UNKNOWN, | |
97 | }; | |
98 | ||
148f9bb8 | 99 | static const struct cpu_dev *this_cpu = &default_cpu; |
0a488a53 | 100 | |
06deef89 | 101 | DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = { |
950ad7ff | 102 | #ifdef CONFIG_X86_64 |
06deef89 BG |
103 | /* |
104 | * We need valid kernel segments for data and code in long mode too | |
105 | * IRET will check the segment types kkeil 2000/10/28 | |
106 | * Also sysret mandates a special GDT layout | |
107 | * | |
9766cdbc | 108 | * TLS descriptors are currently at a different place compared to i386. |
06deef89 BG |
109 | * Hopefully nobody expects them at a fixed place (Wine?) |
110 | */ | |
1e5de182 AM |
111 | [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff), |
112 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff), | |
113 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc093, 0, 0xfffff), | |
114 | [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff), | |
115 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff), | |
116 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff), | |
950ad7ff | 117 | #else |
1e5de182 AM |
118 | [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff), |
119 | [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
120 | [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff), | |
121 | [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff), | |
bf504672 RR |
122 | /* |
123 | * Segments used for calling PnP BIOS have byte granularity. | |
124 | * They code segments and data segments have fixed 64k limits, | |
125 | * the transfer segment sizes are set at run time. | |
126 | */ | |
6842ef0e | 127 | /* 32-bit code */ |
1e5de182 | 128 | [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), |
6842ef0e | 129 | /* 16-bit code */ |
1e5de182 | 130 | [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), |
6842ef0e | 131 | /* 16-bit data */ |
1e5de182 | 132 | [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(0x0092, 0, 0xffff), |
6842ef0e | 133 | /* 16-bit data */ |
1e5de182 | 134 | [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(0x0092, 0, 0), |
6842ef0e | 135 | /* 16-bit data */ |
1e5de182 | 136 | [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(0x0092, 0, 0), |
bf504672 RR |
137 | /* |
138 | * The APM segments have byte granularity and their bases | |
139 | * are set at run time. All have 64k limits. | |
140 | */ | |
6842ef0e | 141 | /* 32-bit code */ |
1e5de182 | 142 | [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(0x409a, 0, 0xffff), |
bf504672 | 143 | /* 16-bit code */ |
1e5de182 | 144 | [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(0x009a, 0, 0xffff), |
6842ef0e | 145 | /* data */ |
72c4d853 | 146 | [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(0x4092, 0, 0xffff), |
bf504672 | 147 | |
1e5de182 AM |
148 | [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), |
149 | [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(0xc092, 0, 0xfffff), | |
60a5317f | 150 | GDT_STACK_CANARY_INIT |
950ad7ff | 151 | #endif |
06deef89 | 152 | } }; |
7a61d35d | 153 | EXPORT_PER_CPU_SYMBOL_GPL(gdt_page); |
ae1ee11b | 154 | |
8c3641e9 | 155 | static int __init x86_mpx_setup(char *s) |
0c752a93 | 156 | { |
8c3641e9 | 157 | /* require an exact match without trailing characters */ |
2cd3949f DH |
158 | if (strlen(s)) |
159 | return 0; | |
0c752a93 | 160 | |
8c3641e9 DH |
161 | /* do not emit a message if the feature is not present */ |
162 | if (!boot_cpu_has(X86_FEATURE_MPX)) | |
163 | return 1; | |
6bad06b7 | 164 | |
8c3641e9 DH |
165 | setup_clear_cpu_cap(X86_FEATURE_MPX); |
166 | pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n"); | |
b6f42a4a FY |
167 | return 1; |
168 | } | |
8c3641e9 | 169 | __setup("nompx", x86_mpx_setup); |
b6f42a4a | 170 | |
0790c9aa | 171 | #ifdef CONFIG_X86_64 |
c7ad5ad2 | 172 | static int __init x86_nopcid_setup(char *s) |
0790c9aa | 173 | { |
c7ad5ad2 AL |
174 | /* nopcid doesn't accept parameters */ |
175 | if (s) | |
176 | return -EINVAL; | |
0790c9aa AL |
177 | |
178 | /* do not emit a message if the feature is not present */ | |
179 | if (!boot_cpu_has(X86_FEATURE_PCID)) | |
c7ad5ad2 | 180 | return 0; |
0790c9aa AL |
181 | |
182 | setup_clear_cpu_cap(X86_FEATURE_PCID); | |
183 | pr_info("nopcid: PCID feature disabled\n"); | |
c7ad5ad2 | 184 | return 0; |
0790c9aa | 185 | } |
c7ad5ad2 | 186 | early_param("nopcid", x86_nopcid_setup); |
0790c9aa AL |
187 | #endif |
188 | ||
d12a72b8 AL |
189 | static int __init x86_noinvpcid_setup(char *s) |
190 | { | |
191 | /* noinvpcid doesn't accept parameters */ | |
192 | if (s) | |
193 | return -EINVAL; | |
194 | ||
195 | /* do not emit a message if the feature is not present */ | |
196 | if (!boot_cpu_has(X86_FEATURE_INVPCID)) | |
197 | return 0; | |
198 | ||
199 | setup_clear_cpu_cap(X86_FEATURE_INVPCID); | |
200 | pr_info("noinvpcid: INVPCID feature disabled\n"); | |
201 | return 0; | |
202 | } | |
203 | early_param("noinvpcid", x86_noinvpcid_setup); | |
204 | ||
ba51dced | 205 | #ifdef CONFIG_X86_32 |
148f9bb8 PG |
206 | static int cachesize_override = -1; |
207 | static int disable_x86_serial_nr = 1; | |
1da177e4 | 208 | |
0a488a53 YL |
209 | static int __init cachesize_setup(char *str) |
210 | { | |
211 | get_option(&str, &cachesize_override); | |
212 | return 1; | |
213 | } | |
214 | __setup("cachesize=", cachesize_setup); | |
215 | ||
0a488a53 YL |
216 | static int __init x86_sep_setup(char *s) |
217 | { | |
218 | setup_clear_cpu_cap(X86_FEATURE_SEP); | |
219 | return 1; | |
220 | } | |
221 | __setup("nosep", x86_sep_setup); | |
222 | ||
223 | /* Standard macro to see if a specific flag is changeable */ | |
224 | static inline int flag_is_changeable_p(u32 flag) | |
225 | { | |
226 | u32 f1, f2; | |
227 | ||
94f6bac1 KH |
228 | /* |
229 | * Cyrix and IDT cpus allow disabling of CPUID | |
230 | * so the code below may return different results | |
231 | * when it is executed before and after enabling | |
232 | * the CPUID. Add "volatile" to not allow gcc to | |
233 | * optimize the subsequent calls to this function. | |
234 | */ | |
0f3fa48a IM |
235 | asm volatile ("pushfl \n\t" |
236 | "pushfl \n\t" | |
237 | "popl %0 \n\t" | |
238 | "movl %0, %1 \n\t" | |
239 | "xorl %2, %0 \n\t" | |
240 | "pushl %0 \n\t" | |
241 | "popfl \n\t" | |
242 | "pushfl \n\t" | |
243 | "popl %0 \n\t" | |
244 | "popfl \n\t" | |
245 | ||
94f6bac1 KH |
246 | : "=&r" (f1), "=&r" (f2) |
247 | : "ir" (flag)); | |
0a488a53 YL |
248 | |
249 | return ((f1^f2) & flag) != 0; | |
250 | } | |
251 | ||
252 | /* Probe for the CPUID instruction */ | |
148f9bb8 | 253 | int have_cpuid_p(void) |
0a488a53 YL |
254 | { |
255 | return flag_is_changeable_p(X86_EFLAGS_ID); | |
256 | } | |
257 | ||
148f9bb8 | 258 | static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
0a488a53 | 259 | { |
0f3fa48a IM |
260 | unsigned long lo, hi; |
261 | ||
262 | if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) | |
263 | return; | |
264 | ||
265 | /* Disable processor serial number: */ | |
266 | ||
267 | rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
268 | lo |= 0x200000; | |
269 | wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); | |
270 | ||
1b74dde7 | 271 | pr_notice("CPU serial number disabled.\n"); |
0f3fa48a IM |
272 | clear_cpu_cap(c, X86_FEATURE_PN); |
273 | ||
274 | /* Disabling the serial number may affect the cpuid level */ | |
275 | c->cpuid_level = cpuid_eax(0); | |
0a488a53 YL |
276 | } |
277 | ||
278 | static int __init x86_serial_nr_setup(char *s) | |
279 | { | |
280 | disable_x86_serial_nr = 0; | |
281 | return 1; | |
282 | } | |
283 | __setup("serialnumber", x86_serial_nr_setup); | |
ba51dced | 284 | #else |
102bbe3a YL |
285 | static inline int flag_is_changeable_p(u32 flag) |
286 | { | |
287 | return 1; | |
288 | } | |
102bbe3a YL |
289 | static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) |
290 | { | |
291 | } | |
ba51dced | 292 | #endif |
0a488a53 | 293 | |
de5397ad FY |
294 | static __init int setup_disable_smep(char *arg) |
295 | { | |
b2cc2a07 | 296 | setup_clear_cpu_cap(X86_FEATURE_SMEP); |
0f6ff2bc DH |
297 | /* Check for things that depend on SMEP being enabled: */ |
298 | check_mpx_erratum(&boot_cpu_data); | |
de5397ad FY |
299 | return 1; |
300 | } | |
301 | __setup("nosmep", setup_disable_smep); | |
302 | ||
b2cc2a07 | 303 | static __always_inline void setup_smep(struct cpuinfo_x86 *c) |
de5397ad | 304 | { |
b2cc2a07 | 305 | if (cpu_has(c, X86_FEATURE_SMEP)) |
375074cc | 306 | cr4_set_bits(X86_CR4_SMEP); |
de5397ad FY |
307 | } |
308 | ||
52b6179a PA |
309 | static __init int setup_disable_smap(char *arg) |
310 | { | |
b2cc2a07 | 311 | setup_clear_cpu_cap(X86_FEATURE_SMAP); |
52b6179a PA |
312 | return 1; |
313 | } | |
314 | __setup("nosmap", setup_disable_smap); | |
315 | ||
b2cc2a07 PA |
316 | static __always_inline void setup_smap(struct cpuinfo_x86 *c) |
317 | { | |
581b7f15 | 318 | unsigned long eflags = native_save_fl(); |
b2cc2a07 PA |
319 | |
320 | /* This should have been cleared long ago */ | |
b2cc2a07 PA |
321 | BUG_ON(eflags & X86_EFLAGS_AC); |
322 | ||
03bbd596 PA |
323 | if (cpu_has(c, X86_FEATURE_SMAP)) { |
324 | #ifdef CONFIG_X86_SMAP | |
375074cc | 325 | cr4_set_bits(X86_CR4_SMAP); |
03bbd596 | 326 | #else |
375074cc | 327 | cr4_clear_bits(X86_CR4_SMAP); |
03bbd596 PA |
328 | #endif |
329 | } | |
de5397ad FY |
330 | } |
331 | ||
06976945 DH |
332 | /* |
333 | * Protection Keys are not available in 32-bit mode. | |
334 | */ | |
335 | static bool pku_disabled; | |
336 | ||
337 | static __always_inline void setup_pku(struct cpuinfo_x86 *c) | |
338 | { | |
e8df1a95 DH |
339 | /* check the boot processor, plus compile options for PKU: */ |
340 | if (!cpu_feature_enabled(X86_FEATURE_PKU)) | |
341 | return; | |
342 | /* checks the actual processor's cpuid bits: */ | |
06976945 DH |
343 | if (!cpu_has(c, X86_FEATURE_PKU)) |
344 | return; | |
345 | if (pku_disabled) | |
346 | return; | |
347 | ||
348 | cr4_set_bits(X86_CR4_PKE); | |
349 | /* | |
350 | * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE | |
351 | * cpuid bit to be set. We need to ensure that we | |
352 | * update that bit in this CPU's "cpu_info". | |
353 | */ | |
354 | get_cpu_cap(c); | |
355 | } | |
356 | ||
357 | #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS | |
358 | static __init int setup_disable_pku(char *arg) | |
359 | { | |
360 | /* | |
361 | * Do not clear the X86_FEATURE_PKU bit. All of the | |
362 | * runtime checks are against OSPKE so clearing the | |
363 | * bit does nothing. | |
364 | * | |
365 | * This way, we will see "pku" in cpuinfo, but not | |
366 | * "ospke", which is exactly what we want. It shows | |
367 | * that the CPU has PKU, but the OS has not enabled it. | |
368 | * This happens to be exactly how a system would look | |
369 | * if we disabled the config option. | |
370 | */ | |
371 | pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n"); | |
372 | pku_disabled = true; | |
373 | return 1; | |
374 | } | |
375 | __setup("nopku", setup_disable_pku); | |
376 | #endif /* CONFIG_X86_64 */ | |
377 | ||
b38b0665 PA |
378 | /* |
379 | * Some CPU features depend on higher CPUID levels, which may not always | |
380 | * be available due to CPUID level capping or broken virtualization | |
381 | * software. Add those features to this table to auto-disable them. | |
382 | */ | |
383 | struct cpuid_dependent_feature { | |
384 | u32 feature; | |
385 | u32 level; | |
386 | }; | |
0f3fa48a | 387 | |
148f9bb8 | 388 | static const struct cpuid_dependent_feature |
b38b0665 PA |
389 | cpuid_dependent_features[] = { |
390 | { X86_FEATURE_MWAIT, 0x00000005 }, | |
391 | { X86_FEATURE_DCA, 0x00000009 }, | |
392 | { X86_FEATURE_XSAVE, 0x0000000d }, | |
393 | { 0, 0 } | |
394 | }; | |
395 | ||
148f9bb8 | 396 | static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn) |
b38b0665 PA |
397 | { |
398 | const struct cpuid_dependent_feature *df; | |
9766cdbc | 399 | |
b38b0665 | 400 | for (df = cpuid_dependent_features; df->feature; df++) { |
0f3fa48a IM |
401 | |
402 | if (!cpu_has(c, df->feature)) | |
403 | continue; | |
b38b0665 PA |
404 | /* |
405 | * Note: cpuid_level is set to -1 if unavailable, but | |
406 | * extended_extended_level is set to 0 if unavailable | |
407 | * and the legitimate extended levels are all negative | |
408 | * when signed; hence the weird messing around with | |
409 | * signs here... | |
410 | */ | |
0f3fa48a | 411 | if (!((s32)df->level < 0 ? |
f6db44df | 412 | (u32)df->level > (u32)c->extended_cpuid_level : |
0f3fa48a IM |
413 | (s32)df->level > (s32)c->cpuid_level)) |
414 | continue; | |
415 | ||
416 | clear_cpu_cap(c, df->feature); | |
417 | if (!warn) | |
418 | continue; | |
419 | ||
1b74dde7 CY |
420 | pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n", |
421 | x86_cap_flag(df->feature), df->level); | |
b38b0665 | 422 | } |
f6db44df | 423 | } |
b38b0665 | 424 | |
102bbe3a YL |
425 | /* |
426 | * Naming convention should be: <Name> [(<Codename>)] | |
427 | * This table only is used unless init_<vendor>() below doesn't set it; | |
0f3fa48a IM |
428 | * in particular, if CPUID levels 0x80000002..4 are supported, this |
429 | * isn't used | |
102bbe3a YL |
430 | */ |
431 | ||
432 | /* Look up CPU names by table lookup. */ | |
148f9bb8 | 433 | static const char *table_lookup_model(struct cpuinfo_x86 *c) |
102bbe3a | 434 | { |
09dc68d9 JB |
435 | #ifdef CONFIG_X86_32 |
436 | const struct legacy_cpu_model_info *info; | |
102bbe3a YL |
437 | |
438 | if (c->x86_model >= 16) | |
439 | return NULL; /* Range check */ | |
440 | ||
441 | if (!this_cpu) | |
442 | return NULL; | |
443 | ||
09dc68d9 | 444 | info = this_cpu->legacy_models; |
102bbe3a | 445 | |
09dc68d9 | 446 | while (info->family) { |
102bbe3a YL |
447 | if (info->family == c->x86) |
448 | return info->model_names[c->x86_model]; | |
449 | info++; | |
450 | } | |
09dc68d9 | 451 | #endif |
102bbe3a YL |
452 | return NULL; /* Not found */ |
453 | } | |
454 | ||
148f9bb8 PG |
455 | __u32 cpu_caps_cleared[NCAPINTS]; |
456 | __u32 cpu_caps_set[NCAPINTS]; | |
7d851c8d | 457 | |
11e3a840 JF |
458 | void load_percpu_segment(int cpu) |
459 | { | |
460 | #ifdef CONFIG_X86_32 | |
461 | loadsegment(fs, __KERNEL_PERCPU); | |
462 | #else | |
45e876f7 | 463 | __loadsegment_simple(gs, 0); |
11e3a840 JF |
464 | wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu)); |
465 | #endif | |
60a5317f | 466 | load_stack_canary_segment(); |
11e3a840 JF |
467 | } |
468 | ||
72f5e08d AL |
469 | #ifdef CONFIG_X86_32 |
470 | /* The 32-bit entry code needs to find cpu_entry_area. */ | |
471 | DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area); | |
472 | #endif | |
473 | ||
40e7f949 AL |
474 | #ifdef CONFIG_X86_64 |
475 | /* | |
476 | * Special IST stacks which the CPU switches to when it calls | |
477 | * an IST-marked descriptor entry. Up to 7 stacks (hardware | |
478 | * limit), all of them are 4K, except the debug stack which | |
479 | * is 8K. | |
480 | */ | |
481 | static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = { | |
482 | [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STKSZ, | |
483 | [DEBUG_STACK - 1] = DEBUG_STKSZ | |
484 | }; | |
485 | ||
486 | static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks | |
487 | [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]); | |
488 | #endif | |
489 | ||
490 | static void __init | |
491 | set_percpu_fixmap_pages(int idx, void *ptr, int pages, pgprot_t prot) | |
492 | { | |
493 | for ( ; pages; pages--, idx--, ptr += PAGE_SIZE) | |
494 | __set_fixmap(idx, per_cpu_ptr_to_phys(ptr), prot); | |
495 | } | |
496 | ||
ef8813ab | 497 | /* Setup the fixmap mappings only once per-processor */ |
40e7f949 | 498 | static void __init setup_cpu_entry_area(int cpu) |
b23adb7d | 499 | { |
45fc8757 | 500 | #ifdef CONFIG_X86_64 |
3386bc8a AL |
501 | extern char _entry_trampoline[]; |
502 | ||
b23adb7d | 503 | /* On 64-bit systems, we use a read-only fixmap GDT. */ |
ef8813ab | 504 | pgprot_t gdt_prot = PAGE_KERNEL_RO; |
45fc8757 | 505 | #else |
b23adb7d AL |
506 | /* |
507 | * On native 32-bit systems, the GDT cannot be read-only because | |
508 | * our double fault handler uses a task gate, and entering through | |
509 | * a task gate needs to change an available TSS to busy. If the GDT | |
510 | * is read-only, that will triple fault. | |
511 | * | |
512 | * On Xen PV, the GDT must be read-only because the hypervisor requires | |
513 | * it. | |
514 | */ | |
ef8813ab | 515 | pgprot_t gdt_prot = boot_cpu_has(X86_FEATURE_XENPV) ? |
b23adb7d | 516 | PAGE_KERNEL_RO : PAGE_KERNEL; |
45fc8757 | 517 | #endif |
69218e47 | 518 | |
ef8813ab | 519 | __set_fixmap(get_cpu_entry_area_index(cpu, gdt), get_cpu_gdt_paddr(cpu), gdt_prot); |
1a935bc3 AL |
520 | |
521 | /* | |
522 | * The Intel SDM says (Volume 3, 7.2.1): | |
523 | * | |
524 | * Avoid placing a page boundary in the part of the TSS that the | |
525 | * processor reads during a task switch (the first 104 bytes). The | |
526 | * processor may not correctly perform address translations if a | |
527 | * boundary occurs in this area. During a task switch, the processor | |
528 | * reads and writes into the first 104 bytes of each TSS (using | |
529 | * contiguous physical addresses beginning with the physical address | |
530 | * of the first byte of the TSS). So, after TSS access begins, if | |
531 | * part of the 104 bytes is not physically contiguous, the processor | |
532 | * will access incorrect information without generating a page-fault | |
533 | * exception. | |
534 | * | |
535 | * There are also a lot of errata involving the TSS spanning a page | |
536 | * boundary. Assert that we're not doing that. | |
537 | */ | |
538 | BUILD_BUG_ON((offsetof(struct tss_struct, x86_tss) ^ | |
539 | offsetofend(struct tss_struct, x86_tss)) & PAGE_MASK); | |
72f5e08d AL |
540 | BUILD_BUG_ON(sizeof(struct tss_struct) % PAGE_SIZE != 0); |
541 | set_percpu_fixmap_pages(get_cpu_entry_area_index(cpu, tss), | |
542 | &per_cpu(cpu_tss, cpu), | |
543 | sizeof(struct tss_struct) / PAGE_SIZE, | |
544 | PAGE_KERNEL); | |
1a935bc3 | 545 | |
72f5e08d | 546 | #ifdef CONFIG_X86_32 |
40e7f949 | 547 | per_cpu(cpu_entry_area, cpu) = get_cpu_entry_area(cpu); |
72f5e08d | 548 | #endif |
3386bc8a AL |
549 | |
550 | #ifdef CONFIG_X86_64 | |
40e7f949 AL |
551 | BUILD_BUG_ON(sizeof(exception_stacks) % PAGE_SIZE != 0); |
552 | BUILD_BUG_ON(sizeof(exception_stacks) != | |
553 | sizeof(((struct cpu_entry_area *)0)->exception_stacks)); | |
554 | set_percpu_fixmap_pages(get_cpu_entry_area_index(cpu, exception_stacks), | |
555 | &per_cpu(exception_stacks, cpu), | |
556 | sizeof(exception_stacks) / PAGE_SIZE, | |
557 | PAGE_KERNEL); | |
558 | ||
3386bc8a AL |
559 | __set_fixmap(get_cpu_entry_area_index(cpu, entry_trampoline), |
560 | __pa_symbol(_entry_trampoline), PAGE_KERNEL_RX); | |
561 | #endif | |
69218e47 TG |
562 | } |
563 | ||
40e7f949 AL |
564 | void __init setup_cpu_entry_areas(void) |
565 | { | |
566 | unsigned int cpu; | |
567 | ||
568 | for_each_possible_cpu(cpu) | |
569 | setup_cpu_entry_area(cpu); | |
570 | } | |
571 | ||
45fc8757 TG |
572 | /* Load the original GDT from the per-cpu structure */ |
573 | void load_direct_gdt(int cpu) | |
574 | { | |
575 | struct desc_ptr gdt_descr; | |
576 | ||
577 | gdt_descr.address = (long)get_cpu_gdt_rw(cpu); | |
578 | gdt_descr.size = GDT_SIZE - 1; | |
579 | load_gdt(&gdt_descr); | |
580 | } | |
581 | EXPORT_SYMBOL_GPL(load_direct_gdt); | |
582 | ||
69218e47 TG |
583 | /* Load a fixmap remapping of the per-cpu GDT */ |
584 | void load_fixmap_gdt(int cpu) | |
585 | { | |
586 | struct desc_ptr gdt_descr; | |
587 | ||
588 | gdt_descr.address = (long)get_cpu_gdt_ro(cpu); | |
589 | gdt_descr.size = GDT_SIZE - 1; | |
590 | load_gdt(&gdt_descr); | |
591 | } | |
45fc8757 | 592 | EXPORT_SYMBOL_GPL(load_fixmap_gdt); |
69218e47 | 593 | |
0f3fa48a IM |
594 | /* |
595 | * Current gdt points %fs at the "master" per-cpu area: after this, | |
596 | * it's on the real one. | |
597 | */ | |
552be871 | 598 | void switch_to_new_gdt(int cpu) |
9d31d35b | 599 | { |
45fc8757 TG |
600 | /* Load the original GDT */ |
601 | load_direct_gdt(cpu); | |
2697fbd5 | 602 | /* Reload the per-cpu base */ |
11e3a840 | 603 | load_percpu_segment(cpu); |
9d31d35b YL |
604 | } |
605 | ||
148f9bb8 | 606 | static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {}; |
1da177e4 | 607 | |
148f9bb8 | 608 | static void get_model_name(struct cpuinfo_x86 *c) |
1da177e4 LT |
609 | { |
610 | unsigned int *v; | |
ee098e1a | 611 | char *p, *q, *s; |
1da177e4 | 612 | |
3da99c97 | 613 | if (c->extended_cpuid_level < 0x80000004) |
1b05d60d | 614 | return; |
1da177e4 | 615 | |
0f3fa48a | 616 | v = (unsigned int *)c->x86_model_id; |
1da177e4 LT |
617 | cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); |
618 | cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); | |
619 | cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); | |
620 | c->x86_model_id[48] = 0; | |
621 | ||
ee098e1a BP |
622 | /* Trim whitespace */ |
623 | p = q = s = &c->x86_model_id[0]; | |
624 | ||
625 | while (*p == ' ') | |
626 | p++; | |
627 | ||
628 | while (*p) { | |
629 | /* Note the last non-whitespace index */ | |
630 | if (!isspace(*p)) | |
631 | s = q; | |
632 | ||
633 | *q++ = *p++; | |
634 | } | |
635 | ||
636 | *(s + 1) = '\0'; | |
1da177e4 LT |
637 | } |
638 | ||
148f9bb8 | 639 | void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) |
1da177e4 | 640 | { |
9d31d35b | 641 | unsigned int n, dummy, ebx, ecx, edx, l2size; |
1da177e4 | 642 | |
3da99c97 | 643 | n = c->extended_cpuid_level; |
1da177e4 LT |
644 | |
645 | if (n >= 0x80000005) { | |
9d31d35b | 646 | cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); |
9d31d35b | 647 | c->x86_cache_size = (ecx>>24) + (edx>>24); |
140fc727 YL |
648 | #ifdef CONFIG_X86_64 |
649 | /* On K8 L1 TLB is inclusive, so don't count it */ | |
650 | c->x86_tlbsize = 0; | |
651 | #endif | |
1da177e4 LT |
652 | } |
653 | ||
654 | if (n < 0x80000006) /* Some chips just has a large L1. */ | |
655 | return; | |
656 | ||
0a488a53 | 657 | cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); |
1da177e4 | 658 | l2size = ecx >> 16; |
34048c9e | 659 | |
140fc727 YL |
660 | #ifdef CONFIG_X86_64 |
661 | c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff); | |
662 | #else | |
1da177e4 | 663 | /* do processor-specific cache resizing */ |
09dc68d9 JB |
664 | if (this_cpu->legacy_cache_size) |
665 | l2size = this_cpu->legacy_cache_size(c, l2size); | |
1da177e4 LT |
666 | |
667 | /* Allow user to override all this if necessary. */ | |
668 | if (cachesize_override != -1) | |
669 | l2size = cachesize_override; | |
670 | ||
34048c9e | 671 | if (l2size == 0) |
1da177e4 | 672 | return; /* Again, no L2 cache is possible */ |
140fc727 | 673 | #endif |
1da177e4 LT |
674 | |
675 | c->x86_cache_size = l2size; | |
1da177e4 LT |
676 | } |
677 | ||
e0ba94f1 AS |
678 | u16 __read_mostly tlb_lli_4k[NR_INFO]; |
679 | u16 __read_mostly tlb_lli_2m[NR_INFO]; | |
680 | u16 __read_mostly tlb_lli_4m[NR_INFO]; | |
681 | u16 __read_mostly tlb_lld_4k[NR_INFO]; | |
682 | u16 __read_mostly tlb_lld_2m[NR_INFO]; | |
683 | u16 __read_mostly tlb_lld_4m[NR_INFO]; | |
dd360393 | 684 | u16 __read_mostly tlb_lld_1g[NR_INFO]; |
e0ba94f1 | 685 | |
f94fe119 | 686 | static void cpu_detect_tlb(struct cpuinfo_x86 *c) |
e0ba94f1 AS |
687 | { |
688 | if (this_cpu->c_detect_tlb) | |
689 | this_cpu->c_detect_tlb(c); | |
690 | ||
f94fe119 | 691 | pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n", |
e0ba94f1 | 692 | tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES], |
f94fe119 SH |
693 | tlb_lli_4m[ENTRIES]); |
694 | ||
695 | pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n", | |
696 | tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES], | |
697 | tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]); | |
e0ba94f1 AS |
698 | } |
699 | ||
148f9bb8 | 700 | void detect_ht(struct cpuinfo_x86 *c) |
1da177e4 | 701 | { |
c8e56d20 | 702 | #ifdef CONFIG_SMP |
0a488a53 YL |
703 | u32 eax, ebx, ecx, edx; |
704 | int index_msb, core_bits; | |
2eaad1fd | 705 | static bool printed; |
1da177e4 | 706 | |
0a488a53 | 707 | if (!cpu_has(c, X86_FEATURE_HT)) |
9d31d35b | 708 | return; |
1da177e4 | 709 | |
0a488a53 YL |
710 | if (cpu_has(c, X86_FEATURE_CMP_LEGACY)) |
711 | goto out; | |
1da177e4 | 712 | |
1cd78776 YL |
713 | if (cpu_has(c, X86_FEATURE_XTOPOLOGY)) |
714 | return; | |
1da177e4 | 715 | |
0a488a53 | 716 | cpuid(1, &eax, &ebx, &ecx, &edx); |
1da177e4 | 717 | |
9d31d35b YL |
718 | smp_num_siblings = (ebx & 0xff0000) >> 16; |
719 | ||
720 | if (smp_num_siblings == 1) { | |
1b74dde7 | 721 | pr_info_once("CPU0: Hyper-Threading is disabled\n"); |
0f3fa48a IM |
722 | goto out; |
723 | } | |
9d31d35b | 724 | |
0f3fa48a IM |
725 | if (smp_num_siblings <= 1) |
726 | goto out; | |
9d31d35b | 727 | |
0f3fa48a IM |
728 | index_msb = get_count_order(smp_num_siblings); |
729 | c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb); | |
9d31d35b | 730 | |
0f3fa48a | 731 | smp_num_siblings = smp_num_siblings / c->x86_max_cores; |
9d31d35b | 732 | |
0f3fa48a | 733 | index_msb = get_count_order(smp_num_siblings); |
9d31d35b | 734 | |
0f3fa48a | 735 | core_bits = get_count_order(c->x86_max_cores); |
9d31d35b | 736 | |
0f3fa48a IM |
737 | c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) & |
738 | ((1 << core_bits) - 1); | |
1da177e4 | 739 | |
0a488a53 | 740 | out: |
2eaad1fd | 741 | if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) { |
1b74dde7 CY |
742 | pr_info("CPU: Physical Processor ID: %d\n", |
743 | c->phys_proc_id); | |
744 | pr_info("CPU: Processor Core ID: %d\n", | |
745 | c->cpu_core_id); | |
2eaad1fd | 746 | printed = 1; |
9d31d35b | 747 | } |
9d31d35b | 748 | #endif |
97e4db7c | 749 | } |
1da177e4 | 750 | |
148f9bb8 | 751 | static void get_cpu_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
752 | { |
753 | char *v = c->x86_vendor_id; | |
0f3fa48a | 754 | int i; |
1da177e4 LT |
755 | |
756 | for (i = 0; i < X86_VENDOR_NUM; i++) { | |
10a434fc YL |
757 | if (!cpu_devs[i]) |
758 | break; | |
759 | ||
760 | if (!strcmp(v, cpu_devs[i]->c_ident[0]) || | |
761 | (cpu_devs[i]->c_ident[1] && | |
762 | !strcmp(v, cpu_devs[i]->c_ident[1]))) { | |
0f3fa48a | 763 | |
10a434fc YL |
764 | this_cpu = cpu_devs[i]; |
765 | c->x86_vendor = this_cpu->c_x86_vendor; | |
766 | return; | |
1da177e4 LT |
767 | } |
768 | } | |
10a434fc | 769 | |
1b74dde7 CY |
770 | pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \ |
771 | "CPU: Your system may be unstable.\n", v); | |
10a434fc | 772 | |
fe38d855 CE |
773 | c->x86_vendor = X86_VENDOR_UNKNOWN; |
774 | this_cpu = &default_cpu; | |
1da177e4 LT |
775 | } |
776 | ||
148f9bb8 | 777 | void cpu_detect(struct cpuinfo_x86 *c) |
1da177e4 | 778 | { |
1da177e4 | 779 | /* Get vendor name */ |
4a148513 HH |
780 | cpuid(0x00000000, (unsigned int *)&c->cpuid_level, |
781 | (unsigned int *)&c->x86_vendor_id[0], | |
782 | (unsigned int *)&c->x86_vendor_id[8], | |
783 | (unsigned int *)&c->x86_vendor_id[4]); | |
1da177e4 | 784 | |
1da177e4 | 785 | c->x86 = 4; |
9d31d35b | 786 | /* Intel-defined flags: level 0x00000001 */ |
1da177e4 LT |
787 | if (c->cpuid_level >= 0x00000001) { |
788 | u32 junk, tfms, cap0, misc; | |
0f3fa48a | 789 | |
1da177e4 | 790 | cpuid(0x00000001, &tfms, &misc, &junk, &cap0); |
99f925ce BP |
791 | c->x86 = x86_family(tfms); |
792 | c->x86_model = x86_model(tfms); | |
793 | c->x86_mask = x86_stepping(tfms); | |
0f3fa48a | 794 | |
d4387bd3 | 795 | if (cap0 & (1<<19)) { |
d4387bd3 | 796 | c->x86_clflush_size = ((misc >> 8) & 0xff) * 8; |
9d31d35b | 797 | c->x86_cache_alignment = c->x86_clflush_size; |
d4387bd3 | 798 | } |
1da177e4 | 799 | } |
1da177e4 | 800 | } |
3da99c97 | 801 | |
8bf1ebca AL |
802 | static void apply_forced_caps(struct cpuinfo_x86 *c) |
803 | { | |
804 | int i; | |
805 | ||
806 | for (i = 0; i < NCAPINTS; i++) { | |
807 | c->x86_capability[i] &= ~cpu_caps_cleared[i]; | |
808 | c->x86_capability[i] |= cpu_caps_set[i]; | |
809 | } | |
810 | } | |
811 | ||
148f9bb8 | 812 | void get_cpu_cap(struct cpuinfo_x86 *c) |
093af8d7 | 813 | { |
39c06df4 | 814 | u32 eax, ebx, ecx, edx; |
093af8d7 | 815 | |
3da99c97 YL |
816 | /* Intel-defined flags: level 0x00000001 */ |
817 | if (c->cpuid_level >= 0x00000001) { | |
39c06df4 | 818 | cpuid(0x00000001, &eax, &ebx, &ecx, &edx); |
0f3fa48a | 819 | |
39c06df4 BP |
820 | c->x86_capability[CPUID_1_ECX] = ecx; |
821 | c->x86_capability[CPUID_1_EDX] = edx; | |
3da99c97 | 822 | } |
093af8d7 | 823 | |
3df8d920 AL |
824 | /* Thermal and Power Management Leaf: level 0x00000006 (eax) */ |
825 | if (c->cpuid_level >= 0x00000006) | |
826 | c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006); | |
827 | ||
bdc802dc PA |
828 | /* Additional Intel-defined flags: level 0x00000007 */ |
829 | if (c->cpuid_level >= 0x00000007) { | |
bdc802dc | 830 | cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); |
39c06df4 | 831 | c->x86_capability[CPUID_7_0_EBX] = ebx; |
dfb4a70f | 832 | c->x86_capability[CPUID_7_ECX] = ecx; |
bdc802dc PA |
833 | } |
834 | ||
6229ad27 FY |
835 | /* Extended state features: level 0x0000000d */ |
836 | if (c->cpuid_level >= 0x0000000d) { | |
6229ad27 FY |
837 | cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); |
838 | ||
39c06df4 | 839 | c->x86_capability[CPUID_D_1_EAX] = eax; |
6229ad27 FY |
840 | } |
841 | ||
cbc82b17 PWJ |
842 | /* Additional Intel-defined flags: level 0x0000000F */ |
843 | if (c->cpuid_level >= 0x0000000F) { | |
cbc82b17 PWJ |
844 | |
845 | /* QoS sub-leaf, EAX=0Fh, ECX=0 */ | |
846 | cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx); | |
39c06df4 BP |
847 | c->x86_capability[CPUID_F_0_EDX] = edx; |
848 | ||
cbc82b17 PWJ |
849 | if (cpu_has(c, X86_FEATURE_CQM_LLC)) { |
850 | /* will be overridden if occupancy monitoring exists */ | |
851 | c->x86_cache_max_rmid = ebx; | |
852 | ||
853 | /* QoS sub-leaf, EAX=0Fh, ECX=1 */ | |
854 | cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx); | |
39c06df4 BP |
855 | c->x86_capability[CPUID_F_1_EDX] = edx; |
856 | ||
33c3cc7a VS |
857 | if ((cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) || |
858 | ((cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL)) || | |
859 | (cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)))) { | |
cbc82b17 PWJ |
860 | c->x86_cache_max_rmid = ecx; |
861 | c->x86_cache_occ_scale = ebx; | |
862 | } | |
863 | } else { | |
864 | c->x86_cache_max_rmid = -1; | |
865 | c->x86_cache_occ_scale = -1; | |
866 | } | |
867 | } | |
868 | ||
3da99c97 | 869 | /* AMD-defined flags: level 0x80000001 */ |
39c06df4 BP |
870 | eax = cpuid_eax(0x80000000); |
871 | c->extended_cpuid_level = eax; | |
872 | ||
873 | if ((eax & 0xffff0000) == 0x80000000) { | |
874 | if (eax >= 0x80000001) { | |
875 | cpuid(0x80000001, &eax, &ebx, &ecx, &edx); | |
0f3fa48a | 876 | |
39c06df4 BP |
877 | c->x86_capability[CPUID_8000_0001_ECX] = ecx; |
878 | c->x86_capability[CPUID_8000_0001_EDX] = edx; | |
093af8d7 | 879 | } |
093af8d7 | 880 | } |
093af8d7 | 881 | |
71faad43 YG |
882 | if (c->extended_cpuid_level >= 0x80000007) { |
883 | cpuid(0x80000007, &eax, &ebx, &ecx, &edx); | |
884 | ||
885 | c->x86_capability[CPUID_8000_0007_EBX] = ebx; | |
886 | c->x86_power = edx; | |
887 | } | |
888 | ||
5122c890 | 889 | if (c->extended_cpuid_level >= 0x80000008) { |
39c06df4 | 890 | cpuid(0x80000008, &eax, &ebx, &ecx, &edx); |
5122c890 YL |
891 | |
892 | c->x86_virt_bits = (eax >> 8) & 0xff; | |
893 | c->x86_phys_bits = eax & 0xff; | |
39c06df4 | 894 | c->x86_capability[CPUID_8000_0008_EBX] = ebx; |
093af8d7 | 895 | } |
13c6c532 JB |
896 | #ifdef CONFIG_X86_32 |
897 | else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36)) | |
898 | c->x86_phys_bits = 36; | |
5122c890 | 899 | #endif |
e3224234 | 900 | |
2ccd71f1 | 901 | if (c->extended_cpuid_level >= 0x8000000a) |
39c06df4 | 902 | c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a); |
093af8d7 | 903 | |
1dedefd1 | 904 | init_scattered_cpuid_features(c); |
60d34501 AL |
905 | |
906 | /* | |
907 | * Clear/Set all flags overridden by options, after probe. | |
908 | * This needs to happen each time we re-probe, which may happen | |
909 | * several times during CPU initialization. | |
910 | */ | |
911 | apply_forced_caps(c); | |
093af8d7 | 912 | } |
1da177e4 | 913 | |
148f9bb8 | 914 | static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c) |
aef93c8b YL |
915 | { |
916 | #ifdef CONFIG_X86_32 | |
917 | int i; | |
918 | ||
919 | /* | |
920 | * First of all, decide if this is a 486 or higher | |
921 | * It's a 486 if we can modify the AC flag | |
922 | */ | |
923 | if (flag_is_changeable_p(X86_EFLAGS_AC)) | |
924 | c->x86 = 4; | |
925 | else | |
926 | c->x86 = 3; | |
927 | ||
928 | for (i = 0; i < X86_VENDOR_NUM; i++) | |
929 | if (cpu_devs[i] && cpu_devs[i]->c_identify) { | |
930 | c->x86_vendor_id[0] = 0; | |
931 | cpu_devs[i]->c_identify(c); | |
932 | if (c->x86_vendor_id[0]) { | |
933 | get_cpu_vendor(c); | |
934 | break; | |
935 | } | |
936 | } | |
937 | #endif | |
938 | } | |
939 | ||
34048c9e PC |
940 | /* |
941 | * Do minimum CPU detection early. | |
942 | * Fields really needed: vendor, cpuid_level, family, model, mask, | |
943 | * cache alignment. | |
944 | * The others are not touched to avoid unwanted side effects. | |
945 | * | |
946 | * WARNING: this function is only called on the BP. Don't add code here | |
947 | * that is supposed to run on all CPUs. | |
948 | */ | |
3da99c97 | 949 | static void __init early_identify_cpu(struct cpuinfo_x86 *c) |
d7cd5611 | 950 | { |
6627d242 YL |
951 | #ifdef CONFIG_X86_64 |
952 | c->x86_clflush_size = 64; | |
13c6c532 JB |
953 | c->x86_phys_bits = 36; |
954 | c->x86_virt_bits = 48; | |
6627d242 | 955 | #else |
d4387bd3 | 956 | c->x86_clflush_size = 32; |
13c6c532 JB |
957 | c->x86_phys_bits = 32; |
958 | c->x86_virt_bits = 32; | |
6627d242 | 959 | #endif |
0a488a53 | 960 | c->x86_cache_alignment = c->x86_clflush_size; |
d7cd5611 | 961 | |
3da99c97 | 962 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
0a488a53 | 963 | c->extended_cpuid_level = 0; |
d7cd5611 | 964 | |
aef93c8b | 965 | /* cyrix could have cpuid enabled via c_identify()*/ |
05fb3c19 AL |
966 | if (have_cpuid_p()) { |
967 | cpu_detect(c); | |
968 | get_cpu_vendor(c); | |
969 | get_cpu_cap(c); | |
78d1b296 | 970 | setup_force_cpu_cap(X86_FEATURE_CPUID); |
d7cd5611 | 971 | |
05fb3c19 AL |
972 | if (this_cpu->c_early_init) |
973 | this_cpu->c_early_init(c); | |
12cf105c | 974 | |
05fb3c19 AL |
975 | c->cpu_index = 0; |
976 | filter_cpuid_features(c, false); | |
093af8d7 | 977 | |
05fb3c19 AL |
978 | if (this_cpu->c_bsp_init) |
979 | this_cpu->c_bsp_init(c); | |
78d1b296 BP |
980 | } else { |
981 | identify_cpu_without_cpuid(c); | |
982 | setup_clear_cpu_cap(X86_FEATURE_CPUID); | |
05fb3c19 | 983 | } |
c3b83598 BP |
984 | |
985 | setup_force_cpu_cap(X86_FEATURE_ALWAYS); | |
db52ef74 | 986 | fpu__init_system(c); |
b8b7abae AL |
987 | |
988 | #ifdef CONFIG_X86_32 | |
989 | /* | |
990 | * Regardless of whether PCID is enumerated, the SDM says | |
991 | * that it can't be enabled in 32-bit mode. | |
992 | */ | |
993 | setup_clear_cpu_cap(X86_FEATURE_PCID); | |
994 | #endif | |
d7cd5611 RR |
995 | } |
996 | ||
9d31d35b YL |
997 | void __init early_cpu_init(void) |
998 | { | |
02dde8b4 | 999 | const struct cpu_dev *const *cdev; |
10a434fc YL |
1000 | int count = 0; |
1001 | ||
ac23f253 | 1002 | #ifdef CONFIG_PROCESSOR_SELECT |
1b74dde7 | 1003 | pr_info("KERNEL supported cpus:\n"); |
31c997ca IM |
1004 | #endif |
1005 | ||
10a434fc | 1006 | for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) { |
02dde8b4 | 1007 | const struct cpu_dev *cpudev = *cdev; |
9d31d35b | 1008 | |
10a434fc YL |
1009 | if (count >= X86_VENDOR_NUM) |
1010 | break; | |
1011 | cpu_devs[count] = cpudev; | |
1012 | count++; | |
1013 | ||
ac23f253 | 1014 | #ifdef CONFIG_PROCESSOR_SELECT |
31c997ca IM |
1015 | { |
1016 | unsigned int j; | |
1017 | ||
1018 | for (j = 0; j < 2; j++) { | |
1019 | if (!cpudev->c_ident[j]) | |
1020 | continue; | |
1b74dde7 | 1021 | pr_info(" %s %s\n", cpudev->c_vendor, |
31c997ca IM |
1022 | cpudev->c_ident[j]); |
1023 | } | |
10a434fc | 1024 | } |
0388423d | 1025 | #endif |
10a434fc | 1026 | } |
9d31d35b | 1027 | early_identify_cpu(&boot_cpu_data); |
d7cd5611 | 1028 | } |
093af8d7 | 1029 | |
b6734c35 | 1030 | /* |
366d4a43 BP |
1031 | * The NOPL instruction is supposed to exist on all CPUs of family >= 6; |
1032 | * unfortunately, that's not true in practice because of early VIA | |
1033 | * chips and (more importantly) broken virtualizers that are not easy | |
1034 | * to detect. In the latter case it doesn't even *fail* reliably, so | |
1035 | * probing for it doesn't even work. Disable it completely on 32-bit | |
ba0593bf | 1036 | * unless we can find a reliable way to detect all the broken cases. |
366d4a43 | 1037 | * Enable it explicitly on 64-bit for non-constant inputs of cpu_has(). |
b6734c35 | 1038 | */ |
148f9bb8 | 1039 | static void detect_nopl(struct cpuinfo_x86 *c) |
b6734c35 | 1040 | { |
366d4a43 | 1041 | #ifdef CONFIG_X86_32 |
b6734c35 | 1042 | clear_cpu_cap(c, X86_FEATURE_NOPL); |
366d4a43 BP |
1043 | #else |
1044 | set_cpu_cap(c, X86_FEATURE_NOPL); | |
58a5aac5 | 1045 | #endif |
d7cd5611 | 1046 | } |
58a5aac5 | 1047 | |
7a5d6704 AL |
1048 | static void detect_null_seg_behavior(struct cpuinfo_x86 *c) |
1049 | { | |
1050 | #ifdef CONFIG_X86_64 | |
58a5aac5 | 1051 | /* |
7a5d6704 AL |
1052 | * Empirically, writing zero to a segment selector on AMD does |
1053 | * not clear the base, whereas writing zero to a segment | |
1054 | * selector on Intel does clear the base. Intel's behavior | |
1055 | * allows slightly faster context switches in the common case | |
1056 | * where GS is unused by the prev and next threads. | |
58a5aac5 | 1057 | * |
7a5d6704 AL |
1058 | * Since neither vendor documents this anywhere that I can see, |
1059 | * detect it directly instead of hardcoding the choice by | |
1060 | * vendor. | |
1061 | * | |
1062 | * I've designated AMD's behavior as the "bug" because it's | |
1063 | * counterintuitive and less friendly. | |
58a5aac5 | 1064 | */ |
7a5d6704 AL |
1065 | |
1066 | unsigned long old_base, tmp; | |
1067 | rdmsrl(MSR_FS_BASE, old_base); | |
1068 | wrmsrl(MSR_FS_BASE, 1); | |
1069 | loadsegment(fs, 0); | |
1070 | rdmsrl(MSR_FS_BASE, tmp); | |
1071 | if (tmp != 0) | |
1072 | set_cpu_bug(c, X86_BUG_NULL_SEG); | |
1073 | wrmsrl(MSR_FS_BASE, old_base); | |
366d4a43 | 1074 | #endif |
d7cd5611 RR |
1075 | } |
1076 | ||
148f9bb8 | 1077 | static void generic_identify(struct cpuinfo_x86 *c) |
1da177e4 | 1078 | { |
aef93c8b | 1079 | c->extended_cpuid_level = 0; |
1da177e4 | 1080 | |
3da99c97 | 1081 | if (!have_cpuid_p()) |
aef93c8b | 1082 | identify_cpu_without_cpuid(c); |
1d67953f | 1083 | |
aef93c8b | 1084 | /* cyrix could have cpuid enabled via c_identify()*/ |
a9853dd6 | 1085 | if (!have_cpuid_p()) |
aef93c8b | 1086 | return; |
1da177e4 | 1087 | |
3da99c97 | 1088 | cpu_detect(c); |
1da177e4 | 1089 | |
3da99c97 | 1090 | get_cpu_vendor(c); |
1da177e4 | 1091 | |
3da99c97 | 1092 | get_cpu_cap(c); |
1da177e4 | 1093 | |
3da99c97 YL |
1094 | if (c->cpuid_level >= 0x00000001) { |
1095 | c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF; | |
b89d3b3e | 1096 | #ifdef CONFIG_X86_32 |
c8e56d20 | 1097 | # ifdef CONFIG_SMP |
cb8cc442 | 1098 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
b89d3b3e | 1099 | # else |
3da99c97 | 1100 | c->apicid = c->initial_apicid; |
b89d3b3e YL |
1101 | # endif |
1102 | #endif | |
b89d3b3e | 1103 | c->phys_proc_id = c->initial_apicid; |
3da99c97 | 1104 | } |
1da177e4 | 1105 | |
1b05d60d | 1106 | get_model_name(c); /* Default name */ |
1da177e4 | 1107 | |
3da99c97 | 1108 | detect_nopl(c); |
7a5d6704 AL |
1109 | |
1110 | detect_null_seg_behavior(c); | |
0230bb03 AL |
1111 | |
1112 | /* | |
1113 | * ESPFIX is a strange bug. All real CPUs have it. Paravirt | |
1114 | * systems that run Linux at CPL > 0 may or may not have the | |
1115 | * issue, but, even if they have the issue, there's absolutely | |
1116 | * nothing we can do about it because we can't use the real IRET | |
1117 | * instruction. | |
1118 | * | |
1119 | * NB: For the time being, only 32-bit kernels support | |
1120 | * X86_BUG_ESPFIX as such. 64-bit kernels directly choose | |
1121 | * whether to apply espfix using paravirt hooks. If any | |
1122 | * non-paravirt system ever shows up that does *not* have the | |
1123 | * ESPFIX issue, we can change this. | |
1124 | */ | |
1125 | #ifdef CONFIG_X86_32 | |
1126 | # ifdef CONFIG_PARAVIRT | |
1127 | do { | |
1128 | extern void native_iret(void); | |
1129 | if (pv_cpu_ops.iret == native_iret) | |
1130 | set_cpu_bug(c, X86_BUG_ESPFIX); | |
1131 | } while (0); | |
1132 | # else | |
1133 | set_cpu_bug(c, X86_BUG_ESPFIX); | |
1134 | # endif | |
1135 | #endif | |
1da177e4 | 1136 | } |
1da177e4 | 1137 | |
cbc82b17 PWJ |
1138 | static void x86_init_cache_qos(struct cpuinfo_x86 *c) |
1139 | { | |
1140 | /* | |
1141 | * The heavy lifting of max_rmid and cache_occ_scale are handled | |
1142 | * in get_cpu_cap(). Here we just set the max_rmid for the boot_cpu | |
1143 | * in case CQM bits really aren't there in this CPU. | |
1144 | */ | |
1145 | if (c != &boot_cpu_data) { | |
1146 | boot_cpu_data.x86_cache_max_rmid = | |
1147 | min(boot_cpu_data.x86_cache_max_rmid, | |
1148 | c->x86_cache_max_rmid); | |
1149 | } | |
1150 | } | |
1151 | ||
d49597fd | 1152 | /* |
9d85eb91 TG |
1153 | * Validate that ACPI/mptables have the same information about the |
1154 | * effective APIC id and update the package map. | |
d49597fd | 1155 | */ |
9d85eb91 | 1156 | static void validate_apic_and_package_id(struct cpuinfo_x86 *c) |
d49597fd TG |
1157 | { |
1158 | #ifdef CONFIG_SMP | |
9d85eb91 | 1159 | unsigned int apicid, cpu = smp_processor_id(); |
d49597fd TG |
1160 | |
1161 | apicid = apic->cpu_present_to_apicid(cpu); | |
d49597fd | 1162 | |
9d85eb91 TG |
1163 | if (apicid != c->apicid) { |
1164 | pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n", | |
d49597fd | 1165 | cpu, apicid, c->initial_apicid); |
d49597fd | 1166 | } |
9d85eb91 | 1167 | BUG_ON(topology_update_package_map(c->phys_proc_id, cpu)); |
d49597fd TG |
1168 | #else |
1169 | c->logical_proc_id = 0; | |
1170 | #endif | |
1171 | } | |
1172 | ||
1da177e4 LT |
1173 | /* |
1174 | * This does the hard work of actually picking apart the CPU stuff... | |
1175 | */ | |
148f9bb8 | 1176 | static void identify_cpu(struct cpuinfo_x86 *c) |
1da177e4 LT |
1177 | { |
1178 | int i; | |
1179 | ||
1180 | c->loops_per_jiffy = loops_per_jiffy; | |
1181 | c->x86_cache_size = -1; | |
1182 | c->x86_vendor = X86_VENDOR_UNKNOWN; | |
1da177e4 LT |
1183 | c->x86_model = c->x86_mask = 0; /* So far unknown... */ |
1184 | c->x86_vendor_id[0] = '\0'; /* Unset */ | |
1185 | c->x86_model_id[0] = '\0'; /* Unset */ | |
94605eff | 1186 | c->x86_max_cores = 1; |
102bbe3a | 1187 | c->x86_coreid_bits = 0; |
79a8b9aa | 1188 | c->cu_id = 0xff; |
11fdd252 | 1189 | #ifdef CONFIG_X86_64 |
102bbe3a | 1190 | c->x86_clflush_size = 64; |
13c6c532 JB |
1191 | c->x86_phys_bits = 36; |
1192 | c->x86_virt_bits = 48; | |
102bbe3a YL |
1193 | #else |
1194 | c->cpuid_level = -1; /* CPUID not detected */ | |
770d132f | 1195 | c->x86_clflush_size = 32; |
13c6c532 JB |
1196 | c->x86_phys_bits = 32; |
1197 | c->x86_virt_bits = 32; | |
102bbe3a YL |
1198 | #endif |
1199 | c->x86_cache_alignment = c->x86_clflush_size; | |
1da177e4 LT |
1200 | memset(&c->x86_capability, 0, sizeof c->x86_capability); |
1201 | ||
1da177e4 LT |
1202 | generic_identify(c); |
1203 | ||
3898534d | 1204 | if (this_cpu->c_identify) |
1da177e4 LT |
1205 | this_cpu->c_identify(c); |
1206 | ||
6a6256f9 | 1207 | /* Clear/Set all flags overridden by options, after probe */ |
8bf1ebca | 1208 | apply_forced_caps(c); |
2759c328 | 1209 | |
102bbe3a | 1210 | #ifdef CONFIG_X86_64 |
cb8cc442 | 1211 | c->apicid = apic->phys_pkg_id(c->initial_apicid, 0); |
102bbe3a YL |
1212 | #endif |
1213 | ||
1da177e4 LT |
1214 | /* |
1215 | * Vendor-specific initialization. In this section we | |
1216 | * canonicalize the feature flags, meaning if there are | |
1217 | * features a certain CPU supports which CPUID doesn't | |
1218 | * tell us, CPUID claiming incorrect flags, or other bugs, | |
1219 | * we handle them here. | |
1220 | * | |
1221 | * At the end of this section, c->x86_capability better | |
1222 | * indicate the features this CPU genuinely supports! | |
1223 | */ | |
1224 | if (this_cpu->c_init) | |
1225 | this_cpu->c_init(c); | |
1226 | ||
1227 | /* Disable the PN if appropriate */ | |
1228 | squash_the_stupid_serial_number(c); | |
1229 | ||
b2cc2a07 PA |
1230 | /* Set up SMEP/SMAP */ |
1231 | setup_smep(c); | |
1232 | setup_smap(c); | |
1233 | ||
1da177e4 | 1234 | /* |
0f3fa48a IM |
1235 | * The vendor-specific functions might have changed features. |
1236 | * Now we do "generic changes." | |
1da177e4 LT |
1237 | */ |
1238 | ||
b38b0665 PA |
1239 | /* Filter out anything that depends on CPUID levels we don't have */ |
1240 | filter_cpuid_features(c, true); | |
1241 | ||
1da177e4 | 1242 | /* If the model name is still unset, do table lookup. */ |
34048c9e | 1243 | if (!c->x86_model_id[0]) { |
02dde8b4 | 1244 | const char *p; |
1da177e4 | 1245 | p = table_lookup_model(c); |
34048c9e | 1246 | if (p) |
1da177e4 LT |
1247 | strcpy(c->x86_model_id, p); |
1248 | else | |
1249 | /* Last resort... */ | |
1250 | sprintf(c->x86_model_id, "%02x/%02x", | |
54a20f8c | 1251 | c->x86, c->x86_model); |
1da177e4 LT |
1252 | } |
1253 | ||
102bbe3a YL |
1254 | #ifdef CONFIG_X86_64 |
1255 | detect_ht(c); | |
1256 | #endif | |
1257 | ||
49d859d7 | 1258 | x86_init_rdrand(c); |
cbc82b17 | 1259 | x86_init_cache_qos(c); |
06976945 | 1260 | setup_pku(c); |
3e0c3737 YL |
1261 | |
1262 | /* | |
6a6256f9 | 1263 | * Clear/Set all flags overridden by options, need do it |
3e0c3737 YL |
1264 | * before following smp all cpus cap AND. |
1265 | */ | |
8bf1ebca | 1266 | apply_forced_caps(c); |
3e0c3737 | 1267 | |
1da177e4 LT |
1268 | /* |
1269 | * On SMP, boot_cpu_data holds the common feature set between | |
1270 | * all CPUs; so make sure that we indicate which features are | |
1271 | * common between the CPUs. The first time this routine gets | |
1272 | * executed, c == &boot_cpu_data. | |
1273 | */ | |
34048c9e | 1274 | if (c != &boot_cpu_data) { |
1da177e4 | 1275 | /* AND the already accumulated flags with these */ |
9d31d35b | 1276 | for (i = 0; i < NCAPINTS; i++) |
1da177e4 | 1277 | boot_cpu_data.x86_capability[i] &= c->x86_capability[i]; |
65fc985b BP |
1278 | |
1279 | /* OR, i.e. replicate the bug flags */ | |
1280 | for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++) | |
1281 | c->x86_capability[i] |= boot_cpu_data.x86_capability[i]; | |
1da177e4 LT |
1282 | } |
1283 | ||
1284 | /* Init Machine Check Exception if available. */ | |
5e09954a | 1285 | mcheck_cpu_init(c); |
30d432df AK |
1286 | |
1287 | select_idle_routine(c); | |
102bbe3a | 1288 | |
de2d9445 | 1289 | #ifdef CONFIG_NUMA |
102bbe3a YL |
1290 | numa_add_cpu(smp_processor_id()); |
1291 | #endif | |
a6c4e076 | 1292 | } |
31ab269a | 1293 | |
8b6c0ab1 IM |
1294 | /* |
1295 | * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions | |
1296 | * on 32-bit kernels: | |
1297 | */ | |
cfda7bb9 AL |
1298 | #ifdef CONFIG_X86_32 |
1299 | void enable_sep_cpu(void) | |
1300 | { | |
8b6c0ab1 IM |
1301 | struct tss_struct *tss; |
1302 | int cpu; | |
cfda7bb9 | 1303 | |
b3edfda4 BP |
1304 | if (!boot_cpu_has(X86_FEATURE_SEP)) |
1305 | return; | |
1306 | ||
8b6c0ab1 IM |
1307 | cpu = get_cpu(); |
1308 | tss = &per_cpu(cpu_tss, cpu); | |
1309 | ||
8b6c0ab1 | 1310 | /* |
cf9328cc AL |
1311 | * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field -- |
1312 | * see the big comment in struct x86_hw_tss's definition. | |
8b6c0ab1 | 1313 | */ |
cfda7bb9 AL |
1314 | |
1315 | tss->x86_tss.ss1 = __KERNEL_CS; | |
8b6c0ab1 | 1316 | wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0); |
0f9a4810 | 1317 | wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_SYSENTER_stack(cpu) + 1), 0); |
4c8cd0c5 | 1318 | wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0); |
8b6c0ab1 | 1319 | |
cfda7bb9 AL |
1320 | put_cpu(); |
1321 | } | |
e04d645f GC |
1322 | #endif |
1323 | ||
a6c4e076 JF |
1324 | void __init identify_boot_cpu(void) |
1325 | { | |
1326 | identify_cpu(&boot_cpu_data); | |
102bbe3a | 1327 | #ifdef CONFIG_X86_32 |
a6c4e076 | 1328 | sysenter_setup(); |
6fe940d6 | 1329 | enable_sep_cpu(); |
102bbe3a | 1330 | #endif |
5b556332 | 1331 | cpu_detect_tlb(&boot_cpu_data); |
a6c4e076 | 1332 | } |
3b520b23 | 1333 | |
148f9bb8 | 1334 | void identify_secondary_cpu(struct cpuinfo_x86 *c) |
a6c4e076 JF |
1335 | { |
1336 | BUG_ON(c == &boot_cpu_data); | |
1337 | identify_cpu(c); | |
102bbe3a | 1338 | #ifdef CONFIG_X86_32 |
a6c4e076 | 1339 | enable_sep_cpu(); |
102bbe3a | 1340 | #endif |
a6c4e076 | 1341 | mtrr_ap_init(); |
9d85eb91 | 1342 | validate_apic_and_package_id(c); |
1da177e4 LT |
1343 | } |
1344 | ||
191679fd AK |
1345 | static __init int setup_noclflush(char *arg) |
1346 | { | |
840d2830 | 1347 | setup_clear_cpu_cap(X86_FEATURE_CLFLUSH); |
da4aaa7d | 1348 | setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT); |
191679fd AK |
1349 | return 1; |
1350 | } | |
1351 | __setup("noclflush", setup_noclflush); | |
1352 | ||
148f9bb8 | 1353 | void print_cpu_info(struct cpuinfo_x86 *c) |
1da177e4 | 1354 | { |
02dde8b4 | 1355 | const char *vendor = NULL; |
1da177e4 | 1356 | |
0f3fa48a | 1357 | if (c->x86_vendor < X86_VENDOR_NUM) { |
1da177e4 | 1358 | vendor = this_cpu->c_vendor; |
0f3fa48a IM |
1359 | } else { |
1360 | if (c->cpuid_level >= 0) | |
1361 | vendor = c->x86_vendor_id; | |
1362 | } | |
1da177e4 | 1363 | |
bd32a8cf | 1364 | if (vendor && !strstr(c->x86_model_id, vendor)) |
1b74dde7 | 1365 | pr_cont("%s ", vendor); |
1da177e4 | 1366 | |
9d31d35b | 1367 | if (c->x86_model_id[0]) |
1b74dde7 | 1368 | pr_cont("%s", c->x86_model_id); |
1da177e4 | 1369 | else |
1b74dde7 | 1370 | pr_cont("%d86", c->x86); |
1da177e4 | 1371 | |
1b74dde7 | 1372 | pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model); |
924e101a | 1373 | |
34048c9e | 1374 | if (c->x86_mask || c->cpuid_level >= 0) |
1b74dde7 | 1375 | pr_cont(", stepping: 0x%x)\n", c->x86_mask); |
1da177e4 | 1376 | else |
1b74dde7 | 1377 | pr_cont(")\n"); |
1da177e4 LT |
1378 | } |
1379 | ||
0c2a3913 AK |
1380 | /* |
1381 | * clearcpuid= was already parsed in fpu__init_parse_early_param. | |
1382 | * But we need to keep a dummy __setup around otherwise it would | |
1383 | * show up as an environment variable for init. | |
1384 | */ | |
1385 | static __init int setup_clearcpuid(char *arg) | |
ac72e788 | 1386 | { |
ac72e788 AK |
1387 | return 1; |
1388 | } | |
0c2a3913 | 1389 | __setup("clearcpuid=", setup_clearcpuid); |
ac72e788 | 1390 | |
d5494d4f | 1391 | #ifdef CONFIG_X86_64 |
947e76cd | 1392 | DEFINE_PER_CPU_FIRST(union irq_stack_union, |
277d5b40 | 1393 | irq_stack_union) __aligned(PAGE_SIZE) __visible; |
0f3fa48a | 1394 | |
bdf977b3 | 1395 | /* |
a7fcf28d AL |
1396 | * The following percpu variables are hot. Align current_task to |
1397 | * cacheline size such that they fall in the same cacheline. | |
bdf977b3 TH |
1398 | */ |
1399 | DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned = | |
1400 | &init_task; | |
1401 | EXPORT_PER_CPU_SYMBOL(current_task); | |
d5494d4f | 1402 | |
bdf977b3 | 1403 | DEFINE_PER_CPU(char *, irq_stack_ptr) = |
4950d6d4 | 1404 | init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE; |
bdf977b3 | 1405 | |
277d5b40 | 1406 | DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1; |
d5494d4f | 1407 | |
c2daa3be PZ |
1408 | DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; |
1409 | EXPORT_PER_CPU_SYMBOL(__preempt_count); | |
1410 | ||
d5494d4f YL |
1411 | /* May not be marked __init: used by software suspend */ |
1412 | void syscall_init(void) | |
1da177e4 | 1413 | { |
3386bc8a AL |
1414 | extern char _entry_trampoline[]; |
1415 | extern char entry_SYSCALL_64_trampoline[]; | |
1416 | ||
72f5e08d | 1417 | int cpu = smp_processor_id(); |
3386bc8a AL |
1418 | unsigned long SYSCALL64_entry_trampoline = |
1419 | (unsigned long)get_cpu_entry_area(cpu)->entry_trampoline + | |
1420 | (entry_SYSCALL_64_trampoline - _entry_trampoline); | |
72f5e08d | 1421 | |
31ac34ca | 1422 | wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS); |
3386bc8a | 1423 | wrmsrl(MSR_LSTAR, SYSCALL64_entry_trampoline); |
d56fe4bf IM |
1424 | |
1425 | #ifdef CONFIG_IA32_EMULATION | |
47edb651 | 1426 | wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat); |
a76c7f46 | 1427 | /* |
487d1edb DV |
1428 | * This only works on Intel CPUs. |
1429 | * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP. | |
1430 | * This does not cause SYSENTER to jump to the wrong location, because | |
1431 | * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit). | |
a76c7f46 DV |
1432 | */ |
1433 | wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); | |
0f9a4810 | 1434 | wrmsrl_safe(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_SYSENTER_stack(cpu) + 1)); |
4c8cd0c5 | 1435 | wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); |
d56fe4bf | 1436 | #else |
47edb651 | 1437 | wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret); |
6b51311c | 1438 | wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); |
d56fe4bf IM |
1439 | wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); |
1440 | wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); | |
d5494d4f | 1441 | #endif |
03ae5768 | 1442 | |
d5494d4f YL |
1443 | /* Flags to clear on syscall */ |
1444 | wrmsrl(MSR_SYSCALL_MASK, | |
63bcff2a | 1445 | X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF| |
8c7aa698 | 1446 | X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT); |
1da177e4 | 1447 | } |
62111195 | 1448 | |
d5494d4f YL |
1449 | /* |
1450 | * Copies of the original ist values from the tss are only accessed during | |
1451 | * debugging, no special alignment required. | |
1452 | */ | |
1453 | DEFINE_PER_CPU(struct orig_ist, orig_ist); | |
1454 | ||
228bdaa9 | 1455 | static DEFINE_PER_CPU(unsigned long, debug_stack_addr); |
42181186 | 1456 | DEFINE_PER_CPU(int, debug_stack_usage); |
228bdaa9 SR |
1457 | |
1458 | int is_debug_stack(unsigned long addr) | |
1459 | { | |
89cbc767 CL |
1460 | return __this_cpu_read(debug_stack_usage) || |
1461 | (addr <= __this_cpu_read(debug_stack_addr) && | |
1462 | addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ)); | |
228bdaa9 | 1463 | } |
0f46efeb | 1464 | NOKPROBE_SYMBOL(is_debug_stack); |
228bdaa9 | 1465 | |
629f4f9d | 1466 | DEFINE_PER_CPU(u32, debug_idt_ctr); |
f8988175 | 1467 | |
228bdaa9 SR |
1468 | void debug_stack_set_zero(void) |
1469 | { | |
629f4f9d SA |
1470 | this_cpu_inc(debug_idt_ctr); |
1471 | load_current_idt(); | |
228bdaa9 | 1472 | } |
0f46efeb | 1473 | NOKPROBE_SYMBOL(debug_stack_set_zero); |
228bdaa9 SR |
1474 | |
1475 | void debug_stack_reset(void) | |
1476 | { | |
629f4f9d | 1477 | if (WARN_ON(!this_cpu_read(debug_idt_ctr))) |
f8988175 | 1478 | return; |
629f4f9d SA |
1479 | if (this_cpu_dec_return(debug_idt_ctr) == 0) |
1480 | load_current_idt(); | |
228bdaa9 | 1481 | } |
0f46efeb | 1482 | NOKPROBE_SYMBOL(debug_stack_reset); |
228bdaa9 | 1483 | |
0f3fa48a | 1484 | #else /* CONFIG_X86_64 */ |
d5494d4f | 1485 | |
bdf977b3 TH |
1486 | DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task; |
1487 | EXPORT_PER_CPU_SYMBOL(current_task); | |
c2daa3be PZ |
1488 | DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT; |
1489 | EXPORT_PER_CPU_SYMBOL(__preempt_count); | |
bdf977b3 | 1490 | |
a7fcf28d AL |
1491 | /* |
1492 | * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find | |
1493 | * the top of the kernel stack. Use an extra percpu variable to track the | |
1494 | * top of the kernel stack directly. | |
1495 | */ | |
1496 | DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) = | |
1497 | (unsigned long)&init_thread_union + THREAD_SIZE; | |
1498 | EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack); | |
1499 | ||
60a5317f | 1500 | #ifdef CONFIG_CC_STACKPROTECTOR |
53f82452 | 1501 | DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary); |
60a5317f | 1502 | #endif |
d5494d4f | 1503 | |
0f3fa48a | 1504 | #endif /* CONFIG_X86_64 */ |
c5413fbe | 1505 | |
9766cdbc JSR |
1506 | /* |
1507 | * Clear all 6 debug registers: | |
1508 | */ | |
1509 | static void clear_all_debug_regs(void) | |
1510 | { | |
1511 | int i; | |
1512 | ||
1513 | for (i = 0; i < 8; i++) { | |
1514 | /* Ignore db4, db5 */ | |
1515 | if ((i == 4) || (i == 5)) | |
1516 | continue; | |
1517 | ||
1518 | set_debugreg(0, i); | |
1519 | } | |
1520 | } | |
c5413fbe | 1521 | |
0bb9fef9 JW |
1522 | #ifdef CONFIG_KGDB |
1523 | /* | |
1524 | * Restore debug regs if using kgdbwait and you have a kernel debugger | |
1525 | * connection established. | |
1526 | */ | |
1527 | static void dbg_restore_debug_regs(void) | |
1528 | { | |
1529 | if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break)) | |
1530 | arch_kgdb_ops.correct_hw_break(); | |
1531 | } | |
1532 | #else /* ! CONFIG_KGDB */ | |
1533 | #define dbg_restore_debug_regs() | |
1534 | #endif /* ! CONFIG_KGDB */ | |
1535 | ||
ce4b1b16 IM |
1536 | static void wait_for_master_cpu(int cpu) |
1537 | { | |
1538 | #ifdef CONFIG_SMP | |
1539 | /* | |
1540 | * wait for ACK from master CPU before continuing | |
1541 | * with AP initialization | |
1542 | */ | |
1543 | WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)); | |
1544 | while (!cpumask_test_cpu(cpu, cpu_callout_mask)) | |
1545 | cpu_relax(); | |
1546 | #endif | |
1547 | } | |
1548 | ||
d2cbcc49 RR |
1549 | /* |
1550 | * cpu_init() initializes state that is per-CPU. Some data is already | |
1551 | * initialized (naturally) in the bootstrap process, such as the GDT | |
1552 | * and IDT. We reload them nevertheless, this function acts as a | |
1553 | * 'CPU state barrier', nothing should get across. | |
1ba76586 | 1554 | * A lot of state is already set up in PDA init for 64 bit |
d2cbcc49 | 1555 | */ |
1ba76586 | 1556 | #ifdef CONFIG_X86_64 |
0f3fa48a | 1557 | |
148f9bb8 | 1558 | void cpu_init(void) |
1ba76586 | 1559 | { |
0fe1e009 | 1560 | struct orig_ist *oist; |
1ba76586 | 1561 | struct task_struct *me; |
0f3fa48a IM |
1562 | struct tss_struct *t; |
1563 | unsigned long v; | |
fb59831b | 1564 | int cpu = raw_smp_processor_id(); |
1ba76586 YL |
1565 | int i; |
1566 | ||
ce4b1b16 IM |
1567 | wait_for_master_cpu(cpu); |
1568 | ||
1e02ce4c AL |
1569 | /* |
1570 | * Initialize the CR4 shadow before doing anything that could | |
1571 | * try to read it. | |
1572 | */ | |
1573 | cr4_init_shadow(); | |
1574 | ||
777284b6 BP |
1575 | if (cpu) |
1576 | load_ucode_ap(); | |
e6ebf5de | 1577 | |
24933b82 | 1578 | t = &per_cpu(cpu_tss, cpu); |
0fe1e009 | 1579 | oist = &per_cpu(orig_ist, cpu); |
0f3fa48a | 1580 | |
e7a22c1e | 1581 | #ifdef CONFIG_NUMA |
27fd185f | 1582 | if (this_cpu_read(numa_node) == 0 && |
e534c7c5 LS |
1583 | early_cpu_to_node(cpu) != NUMA_NO_NODE) |
1584 | set_numa_node(early_cpu_to_node(cpu)); | |
e7a22c1e | 1585 | #endif |
1ba76586 YL |
1586 | |
1587 | me = current; | |
1588 | ||
2eaad1fd | 1589 | pr_debug("Initializing CPU#%d\n", cpu); |
1ba76586 | 1590 | |
375074cc | 1591 | cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); |
1ba76586 YL |
1592 | |
1593 | /* | |
1594 | * Initialize the per-CPU GDT with the boot GDT, | |
1595 | * and set up the GDT descriptor: | |
1596 | */ | |
1597 | ||
552be871 | 1598 | switch_to_new_gdt(cpu); |
2697fbd5 BG |
1599 | loadsegment(fs, 0); |
1600 | ||
cf910e83 | 1601 | load_current_idt(); |
1ba76586 YL |
1602 | |
1603 | memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8); | |
1604 | syscall_init(); | |
1605 | ||
1606 | wrmsrl(MSR_FS_BASE, 0); | |
1607 | wrmsrl(MSR_KERNEL_GS_BASE, 0); | |
1608 | barrier(); | |
1609 | ||
4763ed4d | 1610 | x86_configure_nx(); |
659006bf | 1611 | x2apic_setup(); |
1ba76586 YL |
1612 | |
1613 | /* | |
1614 | * set up and load the per-CPU TSS | |
1615 | */ | |
0fe1e009 | 1616 | if (!oist->ist[0]) { |
40e7f949 | 1617 | char *estacks = get_cpu_entry_area(cpu)->exception_stacks; |
0f3fa48a | 1618 | |
1ba76586 | 1619 | for (v = 0; v < N_EXCEPTION_STACKS; v++) { |
0f3fa48a | 1620 | estacks += exception_stack_sizes[v]; |
0fe1e009 | 1621 | oist->ist[v] = t->x86_tss.ist[v] = |
1ba76586 | 1622 | (unsigned long)estacks; |
228bdaa9 SR |
1623 | if (v == DEBUG_STACK-1) |
1624 | per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks; | |
1ba76586 YL |
1625 | } |
1626 | } | |
1627 | ||
7fb983b4 | 1628 | t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET; |
0f3fa48a | 1629 | |
1ba76586 YL |
1630 | /* |
1631 | * <= is required because the CPU will access up to | |
1632 | * 8 bits beyond the end of the IO permission bitmap. | |
1633 | */ | |
1634 | for (i = 0; i <= IO_BITMAP_LONGS; i++) | |
1635 | t->io_bitmap[i] = ~0UL; | |
1636 | ||
f1f10076 | 1637 | mmgrab(&init_mm); |
1ba76586 | 1638 | me->active_mm = &init_mm; |
8c5dfd25 | 1639 | BUG_ON(me->mm); |
72c0098d | 1640 | initialize_tlbstate_and_flush(); |
1ba76586 YL |
1641 | enter_lazy_tlb(&init_mm, me); |
1642 | ||
20bb8344 | 1643 | /* |
7f2590a1 AL |
1644 | * Initialize the TSS. sp0 points to the entry trampoline stack |
1645 | * regardless of what task is running. | |
20bb8344 | 1646 | */ |
72f5e08d | 1647 | set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); |
1ba76586 | 1648 | load_TR_desc(); |
0f9a4810 | 1649 | load_sp0((unsigned long)(cpu_SYSENTER_stack(cpu) + 1)); |
20bb8344 | 1650 | |
37868fe1 | 1651 | load_mm_ldt(&init_mm); |
1ba76586 | 1652 | |
0bb9fef9 JW |
1653 | clear_all_debug_regs(); |
1654 | dbg_restore_debug_regs(); | |
1ba76586 | 1655 | |
21c4cd10 | 1656 | fpu__init_cpu(); |
1ba76586 | 1657 | |
1ba76586 YL |
1658 | if (is_uv_system()) |
1659 | uv_cpu_init(); | |
69218e47 | 1660 | |
69218e47 | 1661 | load_fixmap_gdt(cpu); |
1ba76586 YL |
1662 | } |
1663 | ||
1664 | #else | |
1665 | ||
148f9bb8 | 1666 | void cpu_init(void) |
9ee79a3d | 1667 | { |
d2cbcc49 RR |
1668 | int cpu = smp_processor_id(); |
1669 | struct task_struct *curr = current; | |
24933b82 | 1670 | struct tss_struct *t = &per_cpu(cpu_tss, cpu); |
62111195 | 1671 | |
ce4b1b16 | 1672 | wait_for_master_cpu(cpu); |
e6ebf5de | 1673 | |
5b2bdbc8 SR |
1674 | /* |
1675 | * Initialize the CR4 shadow before doing anything that could | |
1676 | * try to read it. | |
1677 | */ | |
1678 | cr4_init_shadow(); | |
1679 | ||
ce4b1b16 | 1680 | show_ucode_info_early(); |
62111195 | 1681 | |
1b74dde7 | 1682 | pr_info("Initializing CPU#%d\n", cpu); |
62111195 | 1683 | |
362f924b | 1684 | if (cpu_feature_enabled(X86_FEATURE_VME) || |
59e21e3d | 1685 | boot_cpu_has(X86_FEATURE_TSC) || |
362f924b | 1686 | boot_cpu_has(X86_FEATURE_DE)) |
375074cc | 1687 | cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE); |
62111195 | 1688 | |
cf910e83 | 1689 | load_current_idt(); |
552be871 | 1690 | switch_to_new_gdt(cpu); |
1da177e4 | 1691 | |
1da177e4 LT |
1692 | /* |
1693 | * Set up and load the per-CPU TSS and LDT | |
1694 | */ | |
f1f10076 | 1695 | mmgrab(&init_mm); |
62111195 | 1696 | curr->active_mm = &init_mm; |
8c5dfd25 | 1697 | BUG_ON(curr->mm); |
72c0098d | 1698 | initialize_tlbstate_and_flush(); |
62111195 | 1699 | enter_lazy_tlb(&init_mm, curr); |
1da177e4 | 1700 | |
20bb8344 AL |
1701 | /* |
1702 | * Initialize the TSS. Don't bother initializing sp0, as the initial | |
1703 | * task never enters user mode. | |
1704 | */ | |
72f5e08d | 1705 | set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); |
1da177e4 | 1706 | load_TR_desc(); |
20bb8344 | 1707 | |
37868fe1 | 1708 | load_mm_ldt(&init_mm); |
1da177e4 | 1709 | |
7fb983b4 | 1710 | t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET; |
f9a196b8 | 1711 | |
22c4e308 | 1712 | #ifdef CONFIG_DOUBLEFAULT |
1da177e4 LT |
1713 | /* Set up doublefault TSS pointer in the GDT */ |
1714 | __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss); | |
22c4e308 | 1715 | #endif |
1da177e4 | 1716 | |
9766cdbc | 1717 | clear_all_debug_regs(); |
0bb9fef9 | 1718 | dbg_restore_debug_regs(); |
1da177e4 | 1719 | |
21c4cd10 | 1720 | fpu__init_cpu(); |
69218e47 | 1721 | |
69218e47 | 1722 | load_fixmap_gdt(cpu); |
1da177e4 | 1723 | } |
1ba76586 | 1724 | #endif |
5700f743 | 1725 | |
b51ef52d LA |
1726 | static void bsp_resume(void) |
1727 | { | |
1728 | if (this_cpu->c_bsp_resume) | |
1729 | this_cpu->c_bsp_resume(&boot_cpu_data); | |
1730 | } | |
1731 | ||
1732 | static struct syscore_ops cpu_syscore_ops = { | |
1733 | .resume = bsp_resume, | |
1734 | }; | |
1735 | ||
1736 | static int __init init_cpu_syscore(void) | |
1737 | { | |
1738 | register_syscore_ops(&cpu_syscore_ops); | |
1739 | return 0; | |
1740 | } | |
1741 | core_initcall(init_cpu_syscore); |