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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Machine check handler. | |
e9eee03e | 3 | * |
1da177e4 | 4 | * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs. |
d88203d1 TG |
5 | * Rest from unknown author(s). |
6 | * 2004 Andi Kleen. Rewrote most of it. | |
b79109c3 AK |
7 | * Copyright 2008 Intel Corporation |
8 | * Author: Andi Kleen | |
1da177e4 | 9 | */ |
c767a54b JP |
10 | |
11 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
12 | ||
e9eee03e IM |
13 | #include <linux/thread_info.h> |
14 | #include <linux/capability.h> | |
15 | #include <linux/miscdevice.h> | |
16 | #include <linux/ratelimit.h> | |
17 | #include <linux/kallsyms.h> | |
18 | #include <linux/rcupdate.h> | |
e9eee03e | 19 | #include <linux/kobject.h> |
14a02530 | 20 | #include <linux/uaccess.h> |
e9eee03e IM |
21 | #include <linux/kdebug.h> |
22 | #include <linux/kernel.h> | |
23 | #include <linux/percpu.h> | |
1da177e4 | 24 | #include <linux/string.h> |
8a25a2fd | 25 | #include <linux/device.h> |
f3c6ea1b | 26 | #include <linux/syscore_ops.h> |
3c079792 | 27 | #include <linux/delay.h> |
8c566ef5 | 28 | #include <linux/ctype.h> |
e9eee03e | 29 | #include <linux/sched.h> |
0d7482e3 | 30 | #include <linux/sysfs.h> |
e9eee03e | 31 | #include <linux/types.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
e9eee03e IM |
33 | #include <linux/init.h> |
34 | #include <linux/kmod.h> | |
35 | #include <linux/poll.h> | |
3c079792 | 36 | #include <linux/nmi.h> |
e9eee03e | 37 | #include <linux/cpu.h> |
14a02530 | 38 | #include <linux/smp.h> |
e9eee03e | 39 | #include <linux/fs.h> |
9b1beaf2 | 40 | #include <linux/mm.h> |
5be9ed25 | 41 | #include <linux/debugfs.h> |
b77e70bf | 42 | #include <linux/irq_work.h> |
69c60c88 | 43 | #include <linux/export.h> |
3637efb0 | 44 | #include <linux/jump_label.h> |
e9eee03e | 45 | |
d88203d1 | 46 | #include <asm/processor.h> |
95927475 | 47 | #include <asm/traps.h> |
375074cc | 48 | #include <asm/tlbflush.h> |
e9eee03e IM |
49 | #include <asm/mce.h> |
50 | #include <asm/msr.h> | |
1da177e4 | 51 | |
bd19a5e6 | 52 | #include "mce-internal.h" |
711c2e48 | 53 | |
93b62c3c | 54 | static DEFINE_MUTEX(mce_chrdev_read_mutex); |
2aa2b50d | 55 | |
9a7783d0 | 56 | #define mce_log_get_idx_check(p) \ |
e90328b8 | 57 | ({ \ |
f78f5b90 PM |
58 | RCU_LOCKDEP_WARN(!rcu_read_lock_sched_held() && \ |
59 | !lockdep_is_held(&mce_chrdev_read_mutex), \ | |
3959df1d | 60 | "suspicious mce_log_get_idx_check() usage"); \ |
e90328b8 PM |
61 | smp_load_acquire(&(p)); \ |
62 | }) | |
f56e8a07 | 63 | |
8968f9d3 HS |
64 | #define CREATE_TRACE_POINTS |
65 | #include <trace/events/mce.h> | |
66 | ||
3f2f0680 | 67 | #define SPINUNIT 100 /* 100ns */ |
3c079792 | 68 | |
01ca79f1 AK |
69 | DEFINE_PER_CPU(unsigned, mce_exception_count); |
70 | ||
1462594b | 71 | struct mce_bank *mce_banks __read_mostly; |
bf80bbd7 | 72 | struct mce_vendor_flags mce_flags __read_mostly; |
cebe1820 | 73 | |
d203f0b8 | 74 | struct mca_config mca_cfg __read_mostly = { |
84c2559d | 75 | .bootlog = -1, |
d203f0b8 BP |
76 | /* |
77 | * Tolerant levels: | |
78 | * 0: always panic on uncorrected errors, log corrected errors | |
79 | * 1: panic or SIGBUS on uncorrected errors, log corrected errors | |
80 | * 2: SIGBUS or log uncorrected errors (if possible), log corr. errors | |
81 | * 3: never panic or SIGBUS, log all errors (for testing only) | |
82 | */ | |
84c2559d BP |
83 | .tolerant = 1, |
84 | .monarch_timeout = -1 | |
d203f0b8 BP |
85 | }; |
86 | ||
1020bcbc HS |
87 | /* User mode helper program triggered by machine check event */ |
88 | static unsigned long mce_need_notify; | |
89 | static char mce_helper[128]; | |
90 | static char *mce_helper_argv[2] = { mce_helper, NULL }; | |
1da177e4 | 91 | |
93b62c3c HS |
92 | static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait); |
93 | ||
3c079792 AK |
94 | static DEFINE_PER_CPU(struct mce, mces_seen); |
95 | static int cpu_missing; | |
96 | ||
0644414e NR |
97 | /* |
98 | * MCA banks polled by the period polling timer for corrected events. | |
99 | * With Intel CMCI, this only has MCA banks which do not support CMCI (if any). | |
100 | */ | |
ee031c31 AK |
101 | DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { |
102 | [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL | |
103 | }; | |
104 | ||
c3d1fb56 NR |
105 | /* |
106 | * MCA banks controlled through firmware first for corrected errors. | |
107 | * This is a global list of banks for which we won't enable CMCI and we | |
108 | * won't poll. Firmware controls these banks and is responsible for | |
109 | * reporting corrected errors through GHES. Uncorrected/recoverable | |
110 | * errors are still notified through a machine check. | |
111 | */ | |
112 | mce_banks_t mce_banks_ce_disabled; | |
113 | ||
061120ae CG |
114 | static struct work_struct mce_work; |
115 | static struct irq_work mce_irq_work; | |
9b1beaf2 | 116 | |
61b0fccd TL |
117 | static void (*quirk_no_way_out)(int bank, struct mce *m, struct pt_regs *regs); |
118 | ||
3653ada5 BP |
119 | /* |
120 | * CPU/chipset specific EDAC code can register a notifier call here to print | |
121 | * MCE errors in a human-readable form. | |
122 | */ | |
648ed940 | 123 | ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain); |
3653ada5 | 124 | |
b5f2fa4e AK |
125 | /* Do initial initialization of a struct mce */ |
126 | void mce_setup(struct mce *m) | |
127 | { | |
128 | memset(m, 0, sizeof(struct mce)); | |
d620c67f | 129 | m->cpu = m->extcpu = smp_processor_id(); |
4ea1636b | 130 | m->tsc = rdtsc(); |
8ee08347 AK |
131 | /* We hope get_seconds stays lockless */ |
132 | m->time = get_seconds(); | |
133 | m->cpuvendor = boot_cpu_data.x86_vendor; | |
134 | m->cpuid = cpuid_eax(1); | |
8ee08347 | 135 | m->socketid = cpu_data(m->extcpu).phys_proc_id; |
8ee08347 AK |
136 | m->apicid = cpu_data(m->extcpu).initial_apicid; |
137 | rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap); | |
b5f2fa4e AK |
138 | } |
139 | ||
ea149b36 AK |
140 | DEFINE_PER_CPU(struct mce, injectm); |
141 | EXPORT_PER_CPU_SYMBOL_GPL(injectm); | |
142 | ||
1da177e4 LT |
143 | /* |
144 | * Lockless MCE logging infrastructure. | |
145 | * This avoids deadlocks on printk locks without having to break locks. Also | |
146 | * separate MCEs from kernel messages to avoid bogus bug reports. | |
147 | */ | |
148 | ||
231fd906 | 149 | static struct mce_log mcelog = { |
f6fb0ac0 AK |
150 | .signature = MCE_LOG_SIGNATURE, |
151 | .len = MCE_LOG_LEN, | |
152 | .recordlen = sizeof(struct mce), | |
d88203d1 | 153 | }; |
1da177e4 LT |
154 | |
155 | void mce_log(struct mce *mce) | |
156 | { | |
157 | unsigned next, entry; | |
e9eee03e | 158 | |
8968f9d3 HS |
159 | /* Emit the trace record: */ |
160 | trace_mce_record(mce); | |
161 | ||
f29a7aff CG |
162 | if (!mce_gen_pool_add(mce)) |
163 | irq_work_queue(&mce_irq_work); | |
f0cb5452 | 164 | |
7644143c | 165 | wmb(); |
1da177e4 | 166 | for (;;) { |
9a7783d0 | 167 | entry = mce_log_get_idx_check(mcelog.next); |
673242c1 | 168 | for (;;) { |
696e409d | 169 | |
e9eee03e IM |
170 | /* |
171 | * When the buffer fills up discard new entries. | |
172 | * Assume that the earlier errors are the more | |
173 | * interesting ones: | |
174 | */ | |
673242c1 | 175 | if (entry >= MCE_LOG_LEN) { |
14a02530 HS |
176 | set_bit(MCE_OVERFLOW, |
177 | (unsigned long *)&mcelog.flags); | |
673242c1 AK |
178 | return; |
179 | } | |
e9eee03e | 180 | /* Old left over entry. Skip: */ |
673242c1 AK |
181 | if (mcelog.entry[entry].finished) { |
182 | entry++; | |
183 | continue; | |
184 | } | |
7644143c | 185 | break; |
1da177e4 | 186 | } |
1da177e4 LT |
187 | smp_rmb(); |
188 | next = entry + 1; | |
189 | if (cmpxchg(&mcelog.next, entry, next) == entry) | |
190 | break; | |
191 | } | |
192 | memcpy(mcelog.entry + entry, mce, sizeof(struct mce)); | |
7644143c | 193 | wmb(); |
1da177e4 | 194 | mcelog.entry[entry].finished = 1; |
7644143c | 195 | wmb(); |
1da177e4 | 196 | |
1020bcbc | 197 | set_bit(0, &mce_need_notify); |
1da177e4 LT |
198 | } |
199 | ||
a79da384 | 200 | void mce_inject_log(struct mce *m) |
09371957 | 201 | { |
a79da384 BP |
202 | mutex_lock(&mce_chrdev_read_mutex); |
203 | mce_log(m); | |
204 | mutex_unlock(&mce_chrdev_read_mutex); | |
09371957 | 205 | } |
a79da384 | 206 | EXPORT_SYMBOL_GPL(mce_inject_log); |
09371957 | 207 | |
fd4cf79f | 208 | static struct notifier_block mce_srao_nb; |
09371957 | 209 | |
3653ada5 BP |
210 | void mce_register_decode_chain(struct notifier_block *nb) |
211 | { | |
fd4cf79f CG |
212 | /* Ensure SRAO notifier has the highest priority in the decode chain. */ |
213 | if (nb != &mce_srao_nb && nb->priority == INT_MAX) | |
214 | nb->priority -= 1; | |
215 | ||
3653ada5 BP |
216 | atomic_notifier_chain_register(&x86_mce_decoder_chain, nb); |
217 | } | |
218 | EXPORT_SYMBOL_GPL(mce_register_decode_chain); | |
219 | ||
220 | void mce_unregister_decode_chain(struct notifier_block *nb) | |
221 | { | |
222 | atomic_notifier_chain_unregister(&x86_mce_decoder_chain, nb); | |
223 | } | |
224 | EXPORT_SYMBOL_GPL(mce_unregister_decode_chain); | |
225 | ||
a9750a31 YG |
226 | static inline u32 ctl_reg(int bank) |
227 | { | |
228 | return MSR_IA32_MCx_CTL(bank); | |
229 | } | |
230 | ||
231 | static inline u32 status_reg(int bank) | |
232 | { | |
233 | return MSR_IA32_MCx_STATUS(bank); | |
234 | } | |
235 | ||
236 | static inline u32 addr_reg(int bank) | |
237 | { | |
238 | return MSR_IA32_MCx_ADDR(bank); | |
239 | } | |
240 | ||
241 | static inline u32 misc_reg(int bank) | |
242 | { | |
243 | return MSR_IA32_MCx_MISC(bank); | |
244 | } | |
245 | ||
246 | static inline u32 smca_ctl_reg(int bank) | |
247 | { | |
248 | return MSR_AMD64_SMCA_MCx_CTL(bank); | |
249 | } | |
250 | ||
251 | static inline u32 smca_status_reg(int bank) | |
252 | { | |
253 | return MSR_AMD64_SMCA_MCx_STATUS(bank); | |
254 | } | |
255 | ||
256 | static inline u32 smca_addr_reg(int bank) | |
257 | { | |
258 | return MSR_AMD64_SMCA_MCx_ADDR(bank); | |
259 | } | |
260 | ||
261 | static inline u32 smca_misc_reg(int bank) | |
262 | { | |
263 | return MSR_AMD64_SMCA_MCx_MISC(bank); | |
264 | } | |
265 | ||
266 | struct mca_msr_regs msr_ops = { | |
267 | .ctl = ctl_reg, | |
268 | .status = status_reg, | |
269 | .addr = addr_reg, | |
270 | .misc = misc_reg | |
271 | }; | |
272 | ||
77e26cca | 273 | static void print_mce(struct mce *m) |
1da177e4 | 274 | { |
dffa4b2f BP |
275 | int ret = 0; |
276 | ||
a2d7b0d4 | 277 | pr_emerg(HW_ERR "CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n", |
d620c67f | 278 | m->extcpu, m->mcgstatus, m->bank, m->status); |
f436f8bb | 279 | |
65ea5b03 | 280 | if (m->ip) { |
a2d7b0d4 | 281 | pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ", |
f436f8bb IM |
282 | !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "", |
283 | m->cs, m->ip); | |
284 | ||
1da177e4 | 285 | if (m->cs == __KERNEL_CS) |
65ea5b03 | 286 | print_symbol("{%s}", m->ip); |
f436f8bb | 287 | pr_cont("\n"); |
1da177e4 | 288 | } |
f436f8bb | 289 | |
a2d7b0d4 | 290 | pr_emerg(HW_ERR "TSC %llx ", m->tsc); |
1da177e4 | 291 | if (m->addr) |
f436f8bb | 292 | pr_cont("ADDR %llx ", m->addr); |
1da177e4 | 293 | if (m->misc) |
f436f8bb | 294 | pr_cont("MISC %llx ", m->misc); |
549d042d | 295 | |
4b711f92 YG |
296 | if (mce_flags.smca) { |
297 | if (m->synd) | |
298 | pr_cont("SYND %llx ", m->synd); | |
299 | if (m->ipid) | |
300 | pr_cont("IPID %llx ", m->ipid); | |
301 | } | |
302 | ||
f436f8bb | 303 | pr_cont("\n"); |
506ed6b5 AK |
304 | /* |
305 | * Note this output is parsed by external tools and old fields | |
306 | * should not be changed. | |
307 | */ | |
881e23e5 | 308 | pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n", |
506ed6b5 AK |
309 | m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid, |
310 | cpu_data(m->extcpu).microcode); | |
f436f8bb IM |
311 | |
312 | /* | |
313 | * Print out human-readable details about the MCE error, | |
fb253195 | 314 | * (if the CPU has an implementation for that) |
f436f8bb | 315 | */ |
dffa4b2f BP |
316 | ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m); |
317 | if (ret == NOTIFY_STOP) | |
318 | return; | |
319 | ||
320 | pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n"); | |
86503560 AK |
321 | } |
322 | ||
f94b61c2 AK |
323 | #define PANIC_TIMEOUT 5 /* 5 seconds */ |
324 | ||
c7c9b392 | 325 | static atomic_t mce_panicked; |
f94b61c2 | 326 | |
bf783f9f | 327 | static int fake_panic; |
c7c9b392 | 328 | static atomic_t mce_fake_panicked; |
bf783f9f | 329 | |
f94b61c2 AK |
330 | /* Panic in progress. Enable interrupts and wait for final IPI */ |
331 | static void wait_for_panic(void) | |
332 | { | |
333 | long timeout = PANIC_TIMEOUT*USEC_PER_SEC; | |
f436f8bb | 334 | |
f94b61c2 AK |
335 | preempt_disable(); |
336 | local_irq_enable(); | |
337 | while (timeout-- > 0) | |
338 | udelay(1); | |
29b0f591 | 339 | if (panic_timeout == 0) |
7af19e4a | 340 | panic_timeout = mca_cfg.panic_timeout; |
f94b61c2 AK |
341 | panic("Panicing machine check CPU died"); |
342 | } | |
343 | ||
6c80f87e | 344 | static void mce_panic(const char *msg, struct mce *final, char *exp) |
d88203d1 | 345 | { |
5541c93c TL |
346 | int apei_err = 0; |
347 | struct llist_node *pending; | |
348 | struct mce_evt_llist *l; | |
e02e68d3 | 349 | |
bf783f9f HY |
350 | if (!fake_panic) { |
351 | /* | |
352 | * Make sure only one CPU runs in machine check panic | |
353 | */ | |
c7c9b392 | 354 | if (atomic_inc_return(&mce_panicked) > 1) |
bf783f9f HY |
355 | wait_for_panic(); |
356 | barrier(); | |
f94b61c2 | 357 | |
bf783f9f HY |
358 | bust_spinlocks(1); |
359 | console_verbose(); | |
360 | } else { | |
361 | /* Don't log too much for fake panic */ | |
c7c9b392 | 362 | if (atomic_inc_return(&mce_fake_panicked) > 1) |
bf783f9f HY |
363 | return; |
364 | } | |
5541c93c | 365 | pending = mce_gen_pool_prepare_records(); |
a0189c70 | 366 | /* First print corrected ones that are still unlogged */ |
5541c93c TL |
367 | llist_for_each_entry(l, pending, llnode) { |
368 | struct mce *m = &l->mce; | |
482908b4 | 369 | if (!(m->status & MCI_STATUS_UC)) { |
77e26cca | 370 | print_mce(m); |
482908b4 HY |
371 | if (!apei_err) |
372 | apei_err = apei_write_mce(m); | |
373 | } | |
a0189c70 AK |
374 | } |
375 | /* Now print uncorrected but with the final one last */ | |
5541c93c TL |
376 | llist_for_each_entry(l, pending, llnode) { |
377 | struct mce *m = &l->mce; | |
77e26cca HS |
378 | if (!(m->status & MCI_STATUS_UC)) |
379 | continue; | |
5541c93c | 380 | if (!final || mce_cmp(m, final)) { |
77e26cca | 381 | print_mce(m); |
482908b4 HY |
382 | if (!apei_err) |
383 | apei_err = apei_write_mce(m); | |
384 | } | |
1da177e4 | 385 | } |
482908b4 | 386 | if (final) { |
77e26cca | 387 | print_mce(final); |
482908b4 HY |
388 | if (!apei_err) |
389 | apei_err = apei_write_mce(final); | |
390 | } | |
3c079792 | 391 | if (cpu_missing) |
a2d7b0d4 | 392 | pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n"); |
bd19a5e6 | 393 | if (exp) |
a2d7b0d4 | 394 | pr_emerg(HW_ERR "Machine check: %s\n", exp); |
bf783f9f HY |
395 | if (!fake_panic) { |
396 | if (panic_timeout == 0) | |
7af19e4a | 397 | panic_timeout = mca_cfg.panic_timeout; |
bf783f9f HY |
398 | panic(msg); |
399 | } else | |
a2d7b0d4 | 400 | pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg); |
d88203d1 | 401 | } |
1da177e4 | 402 | |
ea149b36 AK |
403 | /* Support code for software error injection */ |
404 | ||
405 | static int msr_to_offset(u32 msr) | |
406 | { | |
0a3aee0d | 407 | unsigned bank = __this_cpu_read(injectm.bank); |
f436f8bb | 408 | |
84c2559d | 409 | if (msr == mca_cfg.rip_msr) |
ea149b36 | 410 | return offsetof(struct mce, ip); |
d9d73fcc | 411 | if (msr == msr_ops.status(bank)) |
ea149b36 | 412 | return offsetof(struct mce, status); |
d9d73fcc | 413 | if (msr == msr_ops.addr(bank)) |
ea149b36 | 414 | return offsetof(struct mce, addr); |
d9d73fcc | 415 | if (msr == msr_ops.misc(bank)) |
ea149b36 AK |
416 | return offsetof(struct mce, misc); |
417 | if (msr == MSR_IA32_MCG_STATUS) | |
418 | return offsetof(struct mce, mcgstatus); | |
419 | return -1; | |
420 | } | |
421 | ||
5f8c1a54 AK |
422 | /* MSR access wrappers used for error injection */ |
423 | static u64 mce_rdmsrl(u32 msr) | |
424 | { | |
425 | u64 v; | |
11868a2d | 426 | |
0a3aee0d | 427 | if (__this_cpu_read(injectm.finished)) { |
ea149b36 | 428 | int offset = msr_to_offset(msr); |
11868a2d | 429 | |
ea149b36 AK |
430 | if (offset < 0) |
431 | return 0; | |
89cbc767 | 432 | return *(u64 *)((char *)this_cpu_ptr(&injectm) + offset); |
ea149b36 | 433 | } |
11868a2d IM |
434 | |
435 | if (rdmsrl_safe(msr, &v)) { | |
38c54ccb | 436 | WARN_ONCE(1, "mce: Unable to read MSR 0x%x!\n", msr); |
11868a2d IM |
437 | /* |
438 | * Return zero in case the access faulted. This should | |
439 | * not happen normally but can happen if the CPU does | |
440 | * something weird, or if the code is buggy. | |
441 | */ | |
442 | v = 0; | |
443 | } | |
444 | ||
5f8c1a54 AK |
445 | return v; |
446 | } | |
447 | ||
448 | static void mce_wrmsrl(u32 msr, u64 v) | |
449 | { | |
0a3aee0d | 450 | if (__this_cpu_read(injectm.finished)) { |
ea149b36 | 451 | int offset = msr_to_offset(msr); |
11868a2d | 452 | |
ea149b36 | 453 | if (offset >= 0) |
89cbc767 | 454 | *(u64 *)((char *)this_cpu_ptr(&injectm) + offset) = v; |
ea149b36 AK |
455 | return; |
456 | } | |
5f8c1a54 AK |
457 | wrmsrl(msr, v); |
458 | } | |
459 | ||
b8325c5b HS |
460 | /* |
461 | * Collect all global (w.r.t. this processor) status about this machine | |
462 | * check into our "mce" struct so that we can use it later to assess | |
463 | * the severity of the problem as we read per-bank specific details. | |
464 | */ | |
465 | static inline void mce_gather_info(struct mce *m, struct pt_regs *regs) | |
466 | { | |
467 | mce_setup(m); | |
468 | ||
469 | m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); | |
470 | if (regs) { | |
471 | /* | |
472 | * Get the address of the instruction at the time of | |
473 | * the machine check error. | |
474 | */ | |
475 | if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) { | |
476 | m->ip = regs->ip; | |
477 | m->cs = regs->cs; | |
a129a7c8 AK |
478 | |
479 | /* | |
480 | * When in VM86 mode make the cs look like ring 3 | |
481 | * always. This is a lie, but it's better than passing | |
482 | * the additional vm86 bit around everywhere. | |
483 | */ | |
484 | if (v8086_mode(regs)) | |
485 | m->cs |= 3; | |
b8325c5b HS |
486 | } |
487 | /* Use accurate RIP reporting if available. */ | |
84c2559d BP |
488 | if (mca_cfg.rip_msr) |
489 | m->ip = mce_rdmsrl(mca_cfg.rip_msr); | |
b8325c5b HS |
490 | } |
491 | } | |
492 | ||
88ccbedd | 493 | int mce_available(struct cpuinfo_x86 *c) |
1da177e4 | 494 | { |
1462594b | 495 | if (mca_cfg.disabled) |
5b4408fd | 496 | return 0; |
3d1712c9 | 497 | return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); |
1da177e4 LT |
498 | } |
499 | ||
9b1beaf2 AK |
500 | static void mce_schedule_work(void) |
501 | { | |
fd4cf79f | 502 | if (!mce_gen_pool_empty() && keventd_up()) |
061120ae | 503 | schedule_work(&mce_work); |
9b1beaf2 AK |
504 | } |
505 | ||
b77e70bf | 506 | static void mce_irq_work_cb(struct irq_work *entry) |
ccc3c319 | 507 | { |
9ff36ee9 | 508 | mce_notify_irq(); |
9b1beaf2 | 509 | mce_schedule_work(); |
ccc3c319 | 510 | } |
ccc3c319 AK |
511 | |
512 | static void mce_report_event(struct pt_regs *regs) | |
513 | { | |
514 | if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) { | |
9ff36ee9 | 515 | mce_notify_irq(); |
9b1beaf2 AK |
516 | /* |
517 | * Triggering the work queue here is just an insurance | |
518 | * policy in case the syscall exit notify handler | |
519 | * doesn't run soon enough or ends up running on the | |
520 | * wrong CPU (can happen when audit sleeps) | |
521 | */ | |
522 | mce_schedule_work(); | |
ccc3c319 AK |
523 | return; |
524 | } | |
525 | ||
061120ae | 526 | irq_work_queue(&mce_irq_work); |
ccc3c319 AK |
527 | } |
528 | ||
feab21f8 BP |
529 | /* |
530 | * Check if the address reported by the CPU is in a format we can parse. | |
531 | * It would be possible to add code for most other cases, but all would | |
532 | * be somewhat complicated (e.g. segment offset would require an instruction | |
533 | * parser). So only support physical addresses up to page granuality for now. | |
534 | */ | |
535 | static int mce_usable_address(struct mce *m) | |
536 | { | |
537 | if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV)) | |
538 | return 0; | |
539 | ||
540 | /* Checks after this one are Intel-specific: */ | |
541 | if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) | |
542 | return 1; | |
543 | ||
544 | if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT) | |
545 | return 0; | |
546 | if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS) | |
547 | return 0; | |
548 | return 1; | |
549 | } | |
550 | ||
fd4cf79f CG |
551 | static int srao_decode_notifier(struct notifier_block *nb, unsigned long val, |
552 | void *data) | |
553 | { | |
554 | struct mce *mce = (struct mce *)data; | |
555 | unsigned long pfn; | |
556 | ||
557 | if (!mce) | |
558 | return NOTIFY_DONE; | |
559 | ||
c0ec382e | 560 | if (mce_usable_address(mce) && (mce->severity == MCE_AO_SEVERITY)) { |
fd4cf79f CG |
561 | pfn = mce->addr >> PAGE_SHIFT; |
562 | memory_failure(pfn, MCE_VECTOR, 0); | |
563 | } | |
564 | ||
565 | return NOTIFY_OK; | |
ccc3c319 | 566 | } |
fd4cf79f CG |
567 | static struct notifier_block mce_srao_nb = { |
568 | .notifier_call = srao_decode_notifier, | |
569 | .priority = INT_MAX, | |
570 | }; | |
ccc3c319 | 571 | |
85f92694 TL |
572 | /* |
573 | * Read ADDR and MISC registers. | |
574 | */ | |
575 | static void mce_read_aux(struct mce *m, int i) | |
576 | { | |
577 | if (m->status & MCI_STATUS_MISCV) | |
d9d73fcc | 578 | m->misc = mce_rdmsrl(msr_ops.misc(i)); |
db819d60 | 579 | |
85f92694 | 580 | if (m->status & MCI_STATUS_ADDRV) { |
d9d73fcc | 581 | m->addr = mce_rdmsrl(msr_ops.addr(i)); |
85f92694 TL |
582 | |
583 | /* | |
584 | * Mask the reported address by the reported granularity. | |
585 | */ | |
1462594b | 586 | if (mca_cfg.ser && (m->status & MCI_STATUS_MISCV)) { |
85f92694 TL |
587 | u8 shift = MCI_MISC_ADDR_LSB(m->misc); |
588 | m->addr >>= shift; | |
589 | m->addr <<= shift; | |
590 | } | |
4f29b73b YG |
591 | |
592 | /* | |
593 | * Extract [55:<lsb>] where lsb is the least significant | |
594 | * *valid* bit of the address bits. | |
595 | */ | |
596 | if (mce_flags.smca) { | |
597 | u8 lsb = (m->addr >> 56) & 0x3f; | |
598 | ||
599 | m->addr &= GENMASK_ULL(55, lsb); | |
600 | } | |
85f92694 | 601 | } |
db819d60 | 602 | |
5828c46f YG |
603 | if (mce_flags.smca) { |
604 | m->ipid = mce_rdmsrl(MSR_AMD64_SMCA_MCx_IPID(i)); | |
605 | ||
606 | if (m->status & MCI_STATUS_SYNDV) | |
607 | m->synd = mce_rdmsrl(MSR_AMD64_SMCA_MCx_SYND(i)); | |
608 | } | |
85f92694 TL |
609 | } |
610 | ||
fa92c586 CY |
611 | static bool memory_error(struct mce *m) |
612 | { | |
613 | struct cpuinfo_x86 *c = &boot_cpu_data; | |
614 | ||
615 | if (c->x86_vendor == X86_VENDOR_AMD) { | |
db548a28 BP |
616 | /* ErrCodeExt[20:16] */ |
617 | u8 xec = (m->status >> 16) & 0x1f; | |
618 | ||
619 | return (xec == 0x0 || xec == 0x8); | |
fa92c586 CY |
620 | } else if (c->x86_vendor == X86_VENDOR_INTEL) { |
621 | /* | |
622 | * Intel SDM Volume 3B - 15.9.2 Compound Error Codes | |
623 | * | |
624 | * Bit 7 of the MCACOD field of IA32_MCi_STATUS is used for | |
625 | * indicating a memory error. Bit 8 is used for indicating a | |
626 | * cache hierarchy error. The combination of bit 2 and bit 3 | |
627 | * is used for indicating a `generic' cache hierarchy error | |
628 | * But we can't just blindly check the above bits, because if | |
629 | * bit 11 is set, then it is a bus/interconnect error - and | |
630 | * either way the above bits just gives more detail on what | |
631 | * bus/interconnect error happened. Note that bit 12 can be | |
632 | * ignored, as it's the "filter" bit. | |
633 | */ | |
634 | return (m->status & 0xef80) == BIT(7) || | |
635 | (m->status & 0xef00) == BIT(8) || | |
636 | (m->status & 0xeffc) == 0xc; | |
637 | } | |
638 | ||
639 | return false; | |
640 | } | |
641 | ||
ca84f696 AK |
642 | DEFINE_PER_CPU(unsigned, mce_poll_count); |
643 | ||
d88203d1 | 644 | /* |
b79109c3 AK |
645 | * Poll for corrected events or events that happened before reset. |
646 | * Those are just logged through /dev/mcelog. | |
647 | * | |
648 | * This is executed in standard interrupt context. | |
ed7290d0 AK |
649 | * |
650 | * Note: spec recommends to panic for fatal unsignalled | |
651 | * errors here. However this would be quite problematic -- | |
652 | * we would need to reimplement the Monarch handling and | |
653 | * it would mess up the exclusion between exception handler | |
654 | * and poll hander -- * so we skip this for now. | |
655 | * These cases should not happen anyways, or only when the CPU | |
656 | * is already totally * confused. In this case it's likely it will | |
657 | * not fully execute the machine check handler either. | |
b79109c3 | 658 | */ |
3f2f0680 | 659 | bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b) |
b79109c3 | 660 | { |
8b38937b | 661 | bool error_seen = false; |
b79109c3 | 662 | struct mce m; |
fa92c586 | 663 | int severity; |
b79109c3 AK |
664 | int i; |
665 | ||
c6ae41e7 | 666 | this_cpu_inc(mce_poll_count); |
ca84f696 | 667 | |
b8325c5b | 668 | mce_gather_info(&m, NULL); |
b79109c3 | 669 | |
d203f0b8 | 670 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 671 | if (!mce_banks[i].ctl || !test_bit(i, *b)) |
b79109c3 AK |
672 | continue; |
673 | ||
674 | m.misc = 0; | |
675 | m.addr = 0; | |
676 | m.bank = i; | |
677 | m.tsc = 0; | |
678 | ||
679 | barrier(); | |
d9d73fcc | 680 | m.status = mce_rdmsrl(msr_ops.status(i)); |
b79109c3 AK |
681 | if (!(m.status & MCI_STATUS_VAL)) |
682 | continue; | |
683 | ||
3f2f0680 | 684 | |
b79109c3 | 685 | /* |
ed7290d0 AK |
686 | * Uncorrected or signalled events are handled by the exception |
687 | * handler when it is enabled, so don't process those here. | |
b79109c3 AK |
688 | * |
689 | * TBD do the same check for MCI_STATUS_EN here? | |
690 | */ | |
ed7290d0 | 691 | if (!(flags & MCP_UC) && |
1462594b | 692 | (m.status & (mca_cfg.ser ? MCI_STATUS_S : MCI_STATUS_UC))) |
b79109c3 AK |
693 | continue; |
694 | ||
8b38937b TL |
695 | error_seen = true; |
696 | ||
85f92694 | 697 | mce_read_aux(&m, i); |
b79109c3 AK |
698 | |
699 | if (!(flags & MCP_TIMESTAMP)) | |
700 | m.tsc = 0; | |
fa92c586 CY |
701 | |
702 | severity = mce_severity(&m, mca_cfg.tolerant, NULL, false); | |
703 | ||
c0ec382e BP |
704 | if (severity == MCE_DEFERRED_SEVERITY && memory_error(&m)) |
705 | if (m.status & MCI_STATUS_ADDRV) | |
fd4cf79f | 706 | m.severity = severity; |
fa92c586 | 707 | |
b79109c3 AK |
708 | /* |
709 | * Don't get the IP here because it's unlikely to | |
710 | * have anything to do with the actual error location. | |
711 | */ | |
8b38937b | 712 | if (!(flags & MCP_DONTLOG) && !mca_cfg.dont_log_ce) |
5679af4c | 713 | mce_log(&m); |
c0ec382e | 714 | else if (mce_usable_address(&m)) { |
8b38937b TL |
715 | /* |
716 | * Although we skipped logging this, we still want | |
717 | * to take action. Add to the pool so the registered | |
718 | * notifiers will see it. | |
719 | */ | |
720 | if (!mce_gen_pool_add(&m)) | |
721 | mce_schedule_work(); | |
3f2f0680 | 722 | } |
b79109c3 AK |
723 | |
724 | /* | |
725 | * Clear state for this bank. | |
726 | */ | |
d9d73fcc | 727 | mce_wrmsrl(msr_ops.status(i), 0); |
b79109c3 AK |
728 | } |
729 | ||
730 | /* | |
731 | * Don't clear MCG_STATUS here because it's only defined for | |
732 | * exceptions. | |
733 | */ | |
88921be3 AK |
734 | |
735 | sync_core(); | |
3f2f0680 | 736 | |
8b38937b | 737 | return error_seen; |
b79109c3 | 738 | } |
ea149b36 | 739 | EXPORT_SYMBOL_GPL(machine_check_poll); |
b79109c3 | 740 | |
bd19a5e6 AK |
741 | /* |
742 | * Do a quick check if any of the events requires a panic. | |
743 | * This decides if we keep the events around or clear them. | |
744 | */ | |
61b0fccd TL |
745 | static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp, |
746 | struct pt_regs *regs) | |
bd19a5e6 | 747 | { |
95022b8c | 748 | int i, ret = 0; |
17fea54b | 749 | char *tmp; |
bd19a5e6 | 750 | |
d203f0b8 | 751 | for (i = 0; i < mca_cfg.banks; i++) { |
d9d73fcc | 752 | m->status = mce_rdmsrl(msr_ops.status(i)); |
61b0fccd | 753 | if (m->status & MCI_STATUS_VAL) { |
95022b8c | 754 | __set_bit(i, validp); |
61b0fccd TL |
755 | if (quirk_no_way_out) |
756 | quirk_no_way_out(i, m, regs); | |
757 | } | |
17fea54b BP |
758 | |
759 | if (mce_severity(m, mca_cfg.tolerant, &tmp, true) >= MCE_PANIC_SEVERITY) { | |
760 | *msg = tmp; | |
95022b8c | 761 | ret = 1; |
17fea54b | 762 | } |
bd19a5e6 | 763 | } |
95022b8c | 764 | return ret; |
bd19a5e6 AK |
765 | } |
766 | ||
3c079792 AK |
767 | /* |
768 | * Variable to establish order between CPUs while scanning. | |
769 | * Each CPU spins initially until executing is equal its number. | |
770 | */ | |
771 | static atomic_t mce_executing; | |
772 | ||
773 | /* | |
774 | * Defines order of CPUs on entry. First CPU becomes Monarch. | |
775 | */ | |
776 | static atomic_t mce_callin; | |
777 | ||
778 | /* | |
779 | * Check if a timeout waiting for other CPUs happened. | |
780 | */ | |
6c80f87e | 781 | static int mce_timed_out(u64 *t, const char *msg) |
3c079792 AK |
782 | { |
783 | /* | |
784 | * The others already did panic for some reason. | |
785 | * Bail out like in a timeout. | |
786 | * rmb() to tell the compiler that system_state | |
787 | * might have been modified by someone else. | |
788 | */ | |
789 | rmb(); | |
c7c9b392 | 790 | if (atomic_read(&mce_panicked)) |
3c079792 | 791 | wait_for_panic(); |
84c2559d | 792 | if (!mca_cfg.monarch_timeout) |
3c079792 AK |
793 | goto out; |
794 | if ((s64)*t < SPINUNIT) { | |
716079f6 | 795 | if (mca_cfg.tolerant <= 1) |
6c80f87e | 796 | mce_panic(msg, NULL, NULL); |
3c079792 AK |
797 | cpu_missing = 1; |
798 | return 1; | |
799 | } | |
800 | *t -= SPINUNIT; | |
801 | out: | |
802 | touch_nmi_watchdog(); | |
803 | return 0; | |
804 | } | |
805 | ||
806 | /* | |
807 | * The Monarch's reign. The Monarch is the CPU who entered | |
808 | * the machine check handler first. It waits for the others to | |
809 | * raise the exception too and then grades them. When any | |
810 | * error is fatal panic. Only then let the others continue. | |
811 | * | |
812 | * The other CPUs entering the MCE handler will be controlled by the | |
813 | * Monarch. They are called Subjects. | |
814 | * | |
815 | * This way we prevent any potential data corruption in a unrecoverable case | |
816 | * and also makes sure always all CPU's errors are examined. | |
817 | * | |
680b6cfd | 818 | * Also this detects the case of a machine check event coming from outer |
3c079792 AK |
819 | * space (not detected by any CPUs) In this case some external agent wants |
820 | * us to shut down, so panic too. | |
821 | * | |
822 | * The other CPUs might still decide to panic if the handler happens | |
823 | * in a unrecoverable place, but in this case the system is in a semi-stable | |
824 | * state and won't corrupt anything by itself. It's ok to let the others | |
825 | * continue for a bit first. | |
826 | * | |
827 | * All the spin loops have timeouts; when a timeout happens a CPU | |
828 | * typically elects itself to be Monarch. | |
829 | */ | |
830 | static void mce_reign(void) | |
831 | { | |
832 | int cpu; | |
833 | struct mce *m = NULL; | |
834 | int global_worst = 0; | |
835 | char *msg = NULL; | |
836 | char *nmsg = NULL; | |
837 | ||
838 | /* | |
839 | * This CPU is the Monarch and the other CPUs have run | |
840 | * through their handlers. | |
841 | * Grade the severity of the errors of all the CPUs. | |
842 | */ | |
843 | for_each_possible_cpu(cpu) { | |
d203f0b8 BP |
844 | int severity = mce_severity(&per_cpu(mces_seen, cpu), |
845 | mca_cfg.tolerant, | |
e3480271 | 846 | &nmsg, true); |
3c079792 AK |
847 | if (severity > global_worst) { |
848 | msg = nmsg; | |
849 | global_worst = severity; | |
850 | m = &per_cpu(mces_seen, cpu); | |
851 | } | |
852 | } | |
853 | ||
854 | /* | |
855 | * Cannot recover? Panic here then. | |
856 | * This dumps all the mces in the log buffer and stops the | |
857 | * other CPUs. | |
858 | */ | |
d203f0b8 | 859 | if (m && global_worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3) |
8af7043a | 860 | mce_panic("Fatal machine check", m, msg); |
3c079792 AK |
861 | |
862 | /* | |
863 | * For UC somewhere we let the CPU who detects it handle it. | |
864 | * Also must let continue the others, otherwise the handling | |
865 | * CPU could deadlock on a lock. | |
866 | */ | |
867 | ||
868 | /* | |
869 | * No machine check event found. Must be some external | |
870 | * source or one CPU is hung. Panic. | |
871 | */ | |
d203f0b8 | 872 | if (global_worst <= MCE_KEEP_SEVERITY && mca_cfg.tolerant < 3) |
8af7043a | 873 | mce_panic("Fatal machine check from unknown source", NULL, NULL); |
3c079792 AK |
874 | |
875 | /* | |
876 | * Now clear all the mces_seen so that they don't reappear on | |
877 | * the next mce. | |
878 | */ | |
879 | for_each_possible_cpu(cpu) | |
880 | memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce)); | |
881 | } | |
882 | ||
883 | static atomic_t global_nwo; | |
884 | ||
885 | /* | |
886 | * Start of Monarch synchronization. This waits until all CPUs have | |
887 | * entered the exception handler and then determines if any of them | |
888 | * saw a fatal event that requires panic. Then it executes them | |
889 | * in the entry order. | |
890 | * TBD double check parallel CPU hotunplug | |
891 | */ | |
7fb06fc9 | 892 | static int mce_start(int *no_way_out) |
3c079792 | 893 | { |
7fb06fc9 | 894 | int order; |
3c079792 | 895 | int cpus = num_online_cpus(); |
84c2559d | 896 | u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC; |
3c079792 | 897 | |
7fb06fc9 HS |
898 | if (!timeout) |
899 | return -1; | |
3c079792 | 900 | |
7fb06fc9 | 901 | atomic_add(*no_way_out, &global_nwo); |
184e1fdf | 902 | /* |
bf92b1fe DB |
903 | * Rely on the implied barrier below, such that global_nwo |
904 | * is updated before mce_callin. | |
184e1fdf | 905 | */ |
a95436e4 | 906 | order = atomic_inc_return(&mce_callin); |
3c079792 AK |
907 | |
908 | /* | |
909 | * Wait for everyone. | |
910 | */ | |
911 | while (atomic_read(&mce_callin) != cpus) { | |
6c80f87e AL |
912 | if (mce_timed_out(&timeout, |
913 | "Timeout: Not all CPUs entered broadcast exception handler")) { | |
3c079792 | 914 | atomic_set(&global_nwo, 0); |
7fb06fc9 | 915 | return -1; |
3c079792 AK |
916 | } |
917 | ndelay(SPINUNIT); | |
918 | } | |
919 | ||
184e1fdf HY |
920 | /* |
921 | * mce_callin should be read before global_nwo | |
922 | */ | |
923 | smp_rmb(); | |
3c079792 | 924 | |
7fb06fc9 HS |
925 | if (order == 1) { |
926 | /* | |
927 | * Monarch: Starts executing now, the others wait. | |
928 | */ | |
3c079792 | 929 | atomic_set(&mce_executing, 1); |
7fb06fc9 HS |
930 | } else { |
931 | /* | |
932 | * Subject: Now start the scanning loop one by one in | |
933 | * the original callin order. | |
934 | * This way when there are any shared banks it will be | |
935 | * only seen by one CPU before cleared, avoiding duplicates. | |
936 | */ | |
937 | while (atomic_read(&mce_executing) < order) { | |
6c80f87e AL |
938 | if (mce_timed_out(&timeout, |
939 | "Timeout: Subject CPUs unable to finish machine check processing")) { | |
7fb06fc9 HS |
940 | atomic_set(&global_nwo, 0); |
941 | return -1; | |
942 | } | |
943 | ndelay(SPINUNIT); | |
944 | } | |
3c079792 AK |
945 | } |
946 | ||
947 | /* | |
7fb06fc9 | 948 | * Cache the global no_way_out state. |
3c079792 | 949 | */ |
7fb06fc9 HS |
950 | *no_way_out = atomic_read(&global_nwo); |
951 | ||
952 | return order; | |
3c079792 AK |
953 | } |
954 | ||
955 | /* | |
956 | * Synchronize between CPUs after main scanning loop. | |
957 | * This invokes the bulk of the Monarch processing. | |
958 | */ | |
959 | static int mce_end(int order) | |
960 | { | |
961 | int ret = -1; | |
84c2559d | 962 | u64 timeout = (u64)mca_cfg.monarch_timeout * NSEC_PER_USEC; |
3c079792 AK |
963 | |
964 | if (!timeout) | |
965 | goto reset; | |
966 | if (order < 0) | |
967 | goto reset; | |
968 | ||
969 | /* | |
970 | * Allow others to run. | |
971 | */ | |
972 | atomic_inc(&mce_executing); | |
973 | ||
974 | if (order == 1) { | |
975 | /* CHECKME: Can this race with a parallel hotplug? */ | |
976 | int cpus = num_online_cpus(); | |
977 | ||
978 | /* | |
979 | * Monarch: Wait for everyone to go through their scanning | |
980 | * loops. | |
981 | */ | |
982 | while (atomic_read(&mce_executing) <= cpus) { | |
6c80f87e AL |
983 | if (mce_timed_out(&timeout, |
984 | "Timeout: Monarch CPU unable to finish machine check processing")) | |
3c079792 AK |
985 | goto reset; |
986 | ndelay(SPINUNIT); | |
987 | } | |
988 | ||
989 | mce_reign(); | |
990 | barrier(); | |
991 | ret = 0; | |
992 | } else { | |
993 | /* | |
994 | * Subject: Wait for Monarch to finish. | |
995 | */ | |
996 | while (atomic_read(&mce_executing) != 0) { | |
6c80f87e AL |
997 | if (mce_timed_out(&timeout, |
998 | "Timeout: Monarch CPU did not finish machine check processing")) | |
3c079792 AK |
999 | goto reset; |
1000 | ndelay(SPINUNIT); | |
1001 | } | |
1002 | ||
1003 | /* | |
1004 | * Don't reset anything. That's done by the Monarch. | |
1005 | */ | |
1006 | return 0; | |
1007 | } | |
1008 | ||
1009 | /* | |
1010 | * Reset all global state. | |
1011 | */ | |
1012 | reset: | |
1013 | atomic_set(&global_nwo, 0); | |
1014 | atomic_set(&mce_callin, 0); | |
1015 | barrier(); | |
1016 | ||
1017 | /* | |
1018 | * Let others run again. | |
1019 | */ | |
1020 | atomic_set(&mce_executing, 0); | |
1021 | return ret; | |
1022 | } | |
1023 | ||
1024 | static void mce_clear_state(unsigned long *toclear) | |
1025 | { | |
1026 | int i; | |
1027 | ||
d203f0b8 | 1028 | for (i = 0; i < mca_cfg.banks; i++) { |
3c079792 | 1029 | if (test_bit(i, toclear)) |
d9d73fcc | 1030 | mce_wrmsrl(msr_ops.status(i), 0); |
3c079792 AK |
1031 | } |
1032 | } | |
1033 | ||
b2f9d678 TL |
1034 | static int do_memory_failure(struct mce *m) |
1035 | { | |
1036 | int flags = MF_ACTION_REQUIRED; | |
1037 | int ret; | |
1038 | ||
1039 | pr_err("Uncorrected hardware memory error in user-access at %llx", m->addr); | |
1040 | if (!(m->mcgstatus & MCG_STATUS_RIPV)) | |
1041 | flags |= MF_MUST_KILL; | |
1042 | ret = memory_failure(m->addr >> PAGE_SHIFT, MCE_VECTOR, flags); | |
1043 | if (ret) | |
1044 | pr_err("Memory error not recovered"); | |
1045 | return ret; | |
1046 | } | |
1047 | ||
b79109c3 AK |
1048 | /* |
1049 | * The actual machine check handler. This only handles real | |
1050 | * exceptions when something got corrupted coming in through int 18. | |
1051 | * | |
1052 | * This is executed in NMI context not subject to normal locking rules. This | |
1053 | * implies that most kernel services cannot be safely used. Don't even | |
1054 | * think about putting a printk in there! | |
3c079792 AK |
1055 | * |
1056 | * On Intel systems this is entered on all CPUs in parallel through | |
1057 | * MCE broadcast. However some CPUs might be broken beyond repair, | |
1058 | * so be always careful when synchronizing with others. | |
1da177e4 | 1059 | */ |
e9eee03e | 1060 | void do_machine_check(struct pt_regs *regs, long error_code) |
1da177e4 | 1061 | { |
1462594b | 1062 | struct mca_config *cfg = &mca_cfg; |
3c079792 | 1063 | struct mce m, *final; |
1da177e4 | 1064 | int i; |
3c079792 AK |
1065 | int worst = 0; |
1066 | int severity; | |
fead35c6 | 1067 | |
3c079792 AK |
1068 | /* |
1069 | * Establish sequential order between the CPUs entering the machine | |
1070 | * check handler. | |
1071 | */ | |
fead35c6 | 1072 | int order = -1; |
bd78432c TH |
1073 | /* |
1074 | * If no_way_out gets set, there is no safe way to recover from this | |
d203f0b8 | 1075 | * MCE. If mca_cfg.tolerant is cranked up, we'll try anyway. |
bd78432c TH |
1076 | */ |
1077 | int no_way_out = 0; | |
1078 | /* | |
1079 | * If kill_it gets set, there might be a way to recover from this | |
1080 | * error. | |
1081 | */ | |
1082 | int kill_it = 0; | |
b79109c3 | 1083 | DECLARE_BITMAP(toclear, MAX_NR_BANKS); |
95022b8c | 1084 | DECLARE_BITMAP(valid_banks, MAX_NR_BANKS); |
bd19a5e6 | 1085 | char *msg = "Unknown"; |
fead35c6 YG |
1086 | |
1087 | /* | |
1088 | * MCEs are always local on AMD. Same is determined by MCG_STATUS_LMCES | |
1089 | * on Intel. | |
1090 | */ | |
1091 | int lmce = 1; | |
1da177e4 | 1092 | |
d90167a9 AR |
1093 | /* If this CPU is offline, just bail out. */ |
1094 | if (cpu_is_offline(smp_processor_id())) { | |
1095 | u64 mcgstatus; | |
1096 | ||
1097 | mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS); | |
1098 | if (mcgstatus & MCG_STATUS_RIPV) { | |
1099 | mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); | |
1100 | return; | |
1101 | } | |
1102 | } | |
1103 | ||
8c84014f | 1104 | ist_enter(regs); |
95927475 | 1105 | |
c6ae41e7 | 1106 | this_cpu_inc(mce_exception_count); |
01ca79f1 | 1107 | |
1462594b | 1108 | if (!cfg->banks) |
32561696 | 1109 | goto out; |
1da177e4 | 1110 | |
b8325c5b | 1111 | mce_gather_info(&m, regs); |
b5f2fa4e | 1112 | |
89cbc767 | 1113 | final = this_cpu_ptr(&mces_seen); |
3c079792 AK |
1114 | *final = m; |
1115 | ||
95022b8c | 1116 | memset(valid_banks, 0, sizeof(valid_banks)); |
61b0fccd | 1117 | no_way_out = mce_no_way_out(&m, &msg, valid_banks, regs); |
680b6cfd | 1118 | |
1da177e4 LT |
1119 | barrier(); |
1120 | ||
ed7290d0 | 1121 | /* |
a8c321fb TL |
1122 | * When no restart IP might need to kill or panic. |
1123 | * Assume the worst for now, but if we find the | |
1124 | * severity is MCE_AR_SEVERITY we have other options. | |
ed7290d0 AK |
1125 | */ |
1126 | if (!(m.mcgstatus & MCG_STATUS_RIPV)) | |
1127 | kill_it = 1; | |
1128 | ||
3c079792 | 1129 | /* |
fead35c6 YG |
1130 | * Check if this MCE is signaled to only this logical processor, |
1131 | * on Intel only. | |
3c079792 | 1132 | */ |
fead35c6 YG |
1133 | if (m.cpuvendor == X86_VENDOR_INTEL) |
1134 | lmce = m.mcgstatus & MCG_STATUS_LMCES; | |
1135 | ||
1136 | /* | |
1137 | * Go through all banks in exclusion of the other CPUs. This way we | |
1138 | * don't report duplicated events on shared banks because the first one | |
1139 | * to see it will clear it. If this is a Local MCE, then no need to | |
1140 | * perform rendezvous. | |
1141 | */ | |
1142 | if (!lmce) | |
243d657e | 1143 | order = mce_start(&no_way_out); |
243d657e | 1144 | |
1462594b | 1145 | for (i = 0; i < cfg->banks; i++) { |
b79109c3 | 1146 | __clear_bit(i, toclear); |
95022b8c TL |
1147 | if (!test_bit(i, valid_banks)) |
1148 | continue; | |
cebe1820 | 1149 | if (!mce_banks[i].ctl) |
1da177e4 | 1150 | continue; |
d88203d1 TG |
1151 | |
1152 | m.misc = 0; | |
1da177e4 LT |
1153 | m.addr = 0; |
1154 | m.bank = i; | |
1da177e4 | 1155 | |
d9d73fcc | 1156 | m.status = mce_rdmsrl(msr_ops.status(i)); |
1da177e4 LT |
1157 | if ((m.status & MCI_STATUS_VAL) == 0) |
1158 | continue; | |
1159 | ||
b79109c3 | 1160 | /* |
ed7290d0 AK |
1161 | * Non uncorrected or non signaled errors are handled by |
1162 | * machine_check_poll. Leave them alone, unless this panics. | |
b79109c3 | 1163 | */ |
1462594b | 1164 | if (!(m.status & (cfg->ser ? MCI_STATUS_S : MCI_STATUS_UC)) && |
ed7290d0 | 1165 | !no_way_out) |
b79109c3 AK |
1166 | continue; |
1167 | ||
1168 | /* | |
1169 | * Set taint even when machine check was not enabled. | |
1170 | */ | |
373d4d09 | 1171 | add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE); |
b79109c3 | 1172 | |
e3480271 | 1173 | severity = mce_severity(&m, cfg->tolerant, NULL, true); |
b79109c3 | 1174 | |
ed7290d0 | 1175 | /* |
e3480271 CY |
1176 | * When machine check was for corrected/deferred handler don't |
1177 | * touch, unless we're panicing. | |
ed7290d0 | 1178 | */ |
e3480271 CY |
1179 | if ((severity == MCE_KEEP_SEVERITY || |
1180 | severity == MCE_UCNA_SEVERITY) && !no_way_out) | |
ed7290d0 AK |
1181 | continue; |
1182 | __set_bit(i, toclear); | |
1183 | if (severity == MCE_NO_SEVERITY) { | |
b79109c3 AK |
1184 | /* |
1185 | * Machine check event was not enabled. Clear, but | |
1186 | * ignore. | |
1187 | */ | |
1188 | continue; | |
1da177e4 LT |
1189 | } |
1190 | ||
85f92694 | 1191 | mce_read_aux(&m, i); |
1da177e4 | 1192 | |
fd4cf79f CG |
1193 | /* assuming valid severity level != 0 */ |
1194 | m.severity = severity; | |
9b1beaf2 | 1195 | |
b79109c3 | 1196 | mce_log(&m); |
1da177e4 | 1197 | |
3c079792 AK |
1198 | if (severity > worst) { |
1199 | *final = m; | |
1200 | worst = severity; | |
1da177e4 | 1201 | } |
1da177e4 LT |
1202 | } |
1203 | ||
a8c321fb TL |
1204 | /* mce_clear_state will clear *final, save locally for use later */ |
1205 | m = *final; | |
1206 | ||
3c079792 AK |
1207 | if (!no_way_out) |
1208 | mce_clear_state(toclear); | |
1209 | ||
e9eee03e | 1210 | /* |
3c079792 AK |
1211 | * Do most of the synchronization with other CPUs. |
1212 | * When there's any problem use only local no_way_out state. | |
e9eee03e | 1213 | */ |
243d657e AR |
1214 | if (!lmce) { |
1215 | if (mce_end(order) < 0) | |
1216 | no_way_out = worst >= MCE_PANIC_SEVERITY; | |
1217 | } else { | |
1218 | /* | |
1219 | * Local MCE skipped calling mce_reign() | |
1220 | * If we found a fatal error, we need to panic here. | |
1221 | */ | |
1222 | if (worst >= MCE_PANIC_SEVERITY && mca_cfg.tolerant < 3) | |
1223 | mce_panic("Machine check from unknown source", | |
1224 | NULL, NULL); | |
1225 | } | |
bd78432c TH |
1226 | |
1227 | /* | |
b2f9d678 TL |
1228 | * If tolerant is at an insane level we drop requests to kill |
1229 | * processes and continue even when there is no way out. | |
bd78432c | 1230 | */ |
b2f9d678 TL |
1231 | if (cfg->tolerant == 3) |
1232 | kill_it = 0; | |
1233 | else if (no_way_out) | |
1234 | mce_panic("Fatal machine check on current CPU", &m, msg); | |
e02e68d3 | 1235 | |
3c079792 AK |
1236 | if (worst > 0) |
1237 | mce_report_event(regs); | |
5f8c1a54 | 1238 | mce_wrmsrl(MSR_IA32_MCG_STATUS, 0); |
32561696 | 1239 | out: |
88921be3 | 1240 | sync_core(); |
d4812e16 | 1241 | |
b2f9d678 TL |
1242 | if (worst != MCE_AR_SEVERITY && !kill_it) |
1243 | goto out_ist; | |
d4812e16 | 1244 | |
b2f9d678 TL |
1245 | /* Fault was in user mode and we need to take some action */ |
1246 | if ((m.cs & 3) == 3) { | |
1247 | ist_begin_non_atomic(regs); | |
1248 | local_irq_enable(); | |
1249 | ||
1250 | if (kill_it || do_memory_failure(&m)) | |
1251 | force_sig(SIGBUS, current); | |
1252 | local_irq_disable(); | |
1253 | ist_end_non_atomic(); | |
1254 | } else { | |
1255 | if (!fixup_exception(regs, X86_TRAP_MC)) | |
1256 | mce_panic("Failed kernel mode recovery", &m, NULL); | |
d4812e16 | 1257 | } |
b2f9d678 TL |
1258 | |
1259 | out_ist: | |
8c84014f | 1260 | ist_exit(regs); |
1da177e4 | 1261 | } |
ea149b36 | 1262 | EXPORT_SYMBOL_GPL(do_machine_check); |
1da177e4 | 1263 | |
cd42f4a3 TL |
1264 | #ifndef CONFIG_MEMORY_FAILURE |
1265 | int memory_failure(unsigned long pfn, int vector, int flags) | |
9b1beaf2 | 1266 | { |
a8c321fb TL |
1267 | /* mce_severity() should not hand us an ACTION_REQUIRED error */ |
1268 | BUG_ON(flags & MF_ACTION_REQUIRED); | |
c767a54b JP |
1269 | pr_err("Uncorrected memory error in page 0x%lx ignored\n" |
1270 | "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n", | |
1271 | pfn); | |
cd42f4a3 TL |
1272 | |
1273 | return 0; | |
9b1beaf2 | 1274 | } |
cd42f4a3 | 1275 | #endif |
9b1beaf2 | 1276 | |
a8c321fb TL |
1277 | /* |
1278 | * Action optional processing happens here (picking up | |
1279 | * from the list of faulting pages that do_machine_check() | |
fd4cf79f | 1280 | * placed into the genpool). |
a8c321fb | 1281 | */ |
9b1beaf2 AK |
1282 | static void mce_process_work(struct work_struct *dummy) |
1283 | { | |
fd4cf79f | 1284 | mce_gen_pool_process(); |
9b1beaf2 AK |
1285 | } |
1286 | ||
15d5f839 DZ |
1287 | #ifdef CONFIG_X86_MCE_INTEL |
1288 | /*** | |
1289 | * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog | |
676b1855 | 1290 | * @cpu: The CPU on which the event occurred. |
15d5f839 DZ |
1291 | * @status: Event status information |
1292 | * | |
1293 | * This function should be called by the thermal interrupt after the | |
1294 | * event has been processed and the decision was made to log the event | |
1295 | * further. | |
1296 | * | |
1297 | * The status parameter will be saved to the 'status' field of 'struct mce' | |
1298 | * and historically has been the register value of the | |
1299 | * MSR_IA32_THERMAL_STATUS (Intel) msr. | |
1300 | */ | |
b5f2fa4e | 1301 | void mce_log_therm_throt_event(__u64 status) |
15d5f839 DZ |
1302 | { |
1303 | struct mce m; | |
1304 | ||
b5f2fa4e | 1305 | mce_setup(&m); |
15d5f839 DZ |
1306 | m.bank = MCE_THERMAL_BANK; |
1307 | m.status = status; | |
15d5f839 DZ |
1308 | mce_log(&m); |
1309 | } | |
1310 | #endif /* CONFIG_X86_MCE_INTEL */ | |
1311 | ||
1da177e4 | 1312 | /* |
8a336b0a TH |
1313 | * Periodic polling timer for "silent" machine check errors. If the |
1314 | * poller finds an MCE, poll 2x faster. When the poller finds no more | |
1315 | * errors, poll 2x slower (up to check_interval seconds). | |
1da177e4 | 1316 | */ |
3f2f0680 | 1317 | static unsigned long check_interval = INITIAL_CHECK_INTERVAL; |
e9eee03e | 1318 | |
82f7af09 | 1319 | static DEFINE_PER_CPU(unsigned long, mce_next_interval); /* in jiffies */ |
52d168e2 | 1320 | static DEFINE_PER_CPU(struct timer_list, mce_timer); |
1da177e4 | 1321 | |
55babd8f CG |
1322 | static unsigned long mce_adjust_timer_default(unsigned long interval) |
1323 | { | |
1324 | return interval; | |
1325 | } | |
1326 | ||
3f2f0680 | 1327 | static unsigned long (*mce_adjust_timer)(unsigned long interval) = mce_adjust_timer_default; |
55babd8f | 1328 | |
3f2f0680 | 1329 | static void __restart_timer(struct timer_list *t, unsigned long interval) |
27f6c573 | 1330 | { |
3f2f0680 BP |
1331 | unsigned long when = jiffies + interval; |
1332 | unsigned long flags; | |
27f6c573 | 1333 | |
3f2f0680 | 1334 | local_irq_save(flags); |
27f6c573 | 1335 | |
3f2f0680 BP |
1336 | if (timer_pending(t)) { |
1337 | if (time_before(when, t->expires)) | |
f9c287ba | 1338 | mod_timer(t, when); |
3f2f0680 BP |
1339 | } else { |
1340 | t->expires = round_jiffies(when); | |
1341 | add_timer_on(t, smp_processor_id()); | |
1342 | } | |
1343 | ||
1344 | local_irq_restore(flags); | |
27f6c573 CG |
1345 | } |
1346 | ||
82f7af09 | 1347 | static void mce_timer_fn(unsigned long data) |
1da177e4 | 1348 | { |
89cbc767 | 1349 | struct timer_list *t = this_cpu_ptr(&mce_timer); |
3f2f0680 | 1350 | int cpu = smp_processor_id(); |
82f7af09 | 1351 | unsigned long iv; |
52d168e2 | 1352 | |
3f2f0680 BP |
1353 | WARN_ON(cpu != data); |
1354 | ||
1355 | iv = __this_cpu_read(mce_next_interval); | |
52d168e2 | 1356 | |
89cbc767 | 1357 | if (mce_available(this_cpu_ptr(&cpu_info))) { |
3f2f0680 BP |
1358 | machine_check_poll(MCP_TIMESTAMP, this_cpu_ptr(&mce_poll_banks)); |
1359 | ||
1360 | if (mce_intel_cmci_poll()) { | |
1361 | iv = mce_adjust_timer(iv); | |
1362 | goto done; | |
1363 | } | |
e9eee03e | 1364 | } |
1da177e4 LT |
1365 | |
1366 | /* | |
3f2f0680 BP |
1367 | * Alert userspace if needed. If we logged an MCE, reduce the polling |
1368 | * interval, otherwise increase the polling interval. | |
1da177e4 | 1369 | */ |
3f2f0680 | 1370 | if (mce_notify_irq()) |
958fb3c5 | 1371 | iv = max(iv / 2, (unsigned long) HZ/100); |
3f2f0680 | 1372 | else |
82f7af09 | 1373 | iv = min(iv * 2, round_jiffies_relative(check_interval * HZ)); |
3f2f0680 BP |
1374 | |
1375 | done: | |
82f7af09 | 1376 | __this_cpu_write(mce_next_interval, iv); |
3f2f0680 | 1377 | __restart_timer(t, iv); |
55babd8f | 1378 | } |
e02e68d3 | 1379 | |
55babd8f CG |
1380 | /* |
1381 | * Ensure that the timer is firing in @interval from now. | |
1382 | */ | |
1383 | void mce_timer_kick(unsigned long interval) | |
1384 | { | |
89cbc767 | 1385 | struct timer_list *t = this_cpu_ptr(&mce_timer); |
55babd8f CG |
1386 | unsigned long iv = __this_cpu_read(mce_next_interval); |
1387 | ||
3f2f0680 BP |
1388 | __restart_timer(t, interval); |
1389 | ||
55babd8f CG |
1390 | if (interval < iv) |
1391 | __this_cpu_write(mce_next_interval, interval); | |
e02e68d3 TH |
1392 | } |
1393 | ||
9aaef96f HS |
1394 | /* Must not be called in IRQ context where del_timer_sync() can deadlock */ |
1395 | static void mce_timer_delete_all(void) | |
1396 | { | |
1397 | int cpu; | |
1398 | ||
1399 | for_each_online_cpu(cpu) | |
1400 | del_timer_sync(&per_cpu(mce_timer, cpu)); | |
1401 | } | |
1402 | ||
9bd98405 AK |
1403 | static void mce_do_trigger(struct work_struct *work) |
1404 | { | |
1020bcbc | 1405 | call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT); |
9bd98405 AK |
1406 | } |
1407 | ||
1408 | static DECLARE_WORK(mce_trigger_work, mce_do_trigger); | |
1409 | ||
e02e68d3 | 1410 | /* |
9bd98405 AK |
1411 | * Notify the user(s) about new machine check events. |
1412 | * Can be called from interrupt context, but not from machine check/NMI | |
1413 | * context. | |
e02e68d3 | 1414 | */ |
9ff36ee9 | 1415 | int mce_notify_irq(void) |
e02e68d3 | 1416 | { |
8457c84d AK |
1417 | /* Not more than two messages every minute */ |
1418 | static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); | |
1419 | ||
1020bcbc | 1420 | if (test_and_clear_bit(0, &mce_need_notify)) { |
93b62c3c HS |
1421 | /* wake processes polling /dev/mcelog */ |
1422 | wake_up_interruptible(&mce_chrdev_wait); | |
9bd98405 | 1423 | |
4d899be5 | 1424 | if (mce_helper[0]) |
9bd98405 | 1425 | schedule_work(&mce_trigger_work); |
e02e68d3 | 1426 | |
8457c84d | 1427 | if (__ratelimit(&ratelimit)) |
a2d7b0d4 | 1428 | pr_info(HW_ERR "Machine check events logged\n"); |
e02e68d3 TH |
1429 | |
1430 | return 1; | |
1da177e4 | 1431 | } |
e02e68d3 TH |
1432 | return 0; |
1433 | } | |
9ff36ee9 | 1434 | EXPORT_SYMBOL_GPL(mce_notify_irq); |
8a336b0a | 1435 | |
148f9bb8 | 1436 | static int __mcheck_cpu_mce_banks_init(void) |
cebe1820 AK |
1437 | { |
1438 | int i; | |
d203f0b8 | 1439 | u8 num_banks = mca_cfg.banks; |
cebe1820 | 1440 | |
d203f0b8 | 1441 | mce_banks = kzalloc(num_banks * sizeof(struct mce_bank), GFP_KERNEL); |
cebe1820 AK |
1442 | if (!mce_banks) |
1443 | return -ENOMEM; | |
d203f0b8 BP |
1444 | |
1445 | for (i = 0; i < num_banks; i++) { | |
cebe1820 | 1446 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1447 | |
cebe1820 AK |
1448 | b->ctl = -1ULL; |
1449 | b->init = 1; | |
1450 | } | |
1451 | return 0; | |
1452 | } | |
1453 | ||
d88203d1 | 1454 | /* |
1da177e4 LT |
1455 | * Initialize Machine Checks for a CPU. |
1456 | */ | |
148f9bb8 | 1457 | static int __mcheck_cpu_cap_init(void) |
1da177e4 | 1458 | { |
0d7482e3 | 1459 | unsigned b; |
e9eee03e | 1460 | u64 cap; |
1da177e4 LT |
1461 | |
1462 | rdmsrl(MSR_IA32_MCG_CAP, cap); | |
01c6680a TG |
1463 | |
1464 | b = cap & MCG_BANKCNT_MASK; | |
d203f0b8 | 1465 | if (!mca_cfg.banks) |
c767a54b | 1466 | pr_info("CPU supports %d MCE banks\n", b); |
b659294b | 1467 | |
0d7482e3 | 1468 | if (b > MAX_NR_BANKS) { |
c767a54b | 1469 | pr_warn("Using only %u machine check banks out of %u\n", |
0d7482e3 AK |
1470 | MAX_NR_BANKS, b); |
1471 | b = MAX_NR_BANKS; | |
1472 | } | |
1473 | ||
1474 | /* Don't support asymmetric configurations today */ | |
d203f0b8 BP |
1475 | WARN_ON(mca_cfg.banks != 0 && b != mca_cfg.banks); |
1476 | mca_cfg.banks = b; | |
1477 | ||
cebe1820 | 1478 | if (!mce_banks) { |
cffd377e | 1479 | int err = __mcheck_cpu_mce_banks_init(); |
11868a2d | 1480 | |
cebe1820 AK |
1481 | if (err) |
1482 | return err; | |
1da177e4 | 1483 | } |
0d7482e3 | 1484 | |
94ad8474 | 1485 | /* Use accurate RIP reporting if available. */ |
01c6680a | 1486 | if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9) |
84c2559d | 1487 | mca_cfg.rip_msr = MSR_IA32_MCG_EIP; |
1da177e4 | 1488 | |
ed7290d0 | 1489 | if (cap & MCG_SER_P) |
1462594b | 1490 | mca_cfg.ser = true; |
ed7290d0 | 1491 | |
0d7482e3 AK |
1492 | return 0; |
1493 | } | |
1494 | ||
5e09954a | 1495 | static void __mcheck_cpu_init_generic(void) |
0d7482e3 | 1496 | { |
84c2559d | 1497 | enum mcp_flags m_fl = 0; |
e9eee03e | 1498 | mce_banks_t all_banks; |
0d7482e3 | 1499 | u64 cap; |
0d7482e3 | 1500 | |
84c2559d BP |
1501 | if (!mca_cfg.bootlog) |
1502 | m_fl = MCP_DONTLOG; | |
1503 | ||
b79109c3 AK |
1504 | /* |
1505 | * Log the machine checks left over from the previous reset. | |
1506 | */ | |
ee031c31 | 1507 | bitmap_fill(all_banks, MAX_NR_BANKS); |
84c2559d | 1508 | machine_check_poll(MCP_UC | m_fl, &all_banks); |
1da177e4 | 1509 | |
375074cc | 1510 | cr4_set_bits(X86_CR4_MCE); |
1da177e4 | 1511 | |
0d7482e3 | 1512 | rdmsrl(MSR_IA32_MCG_CAP, cap); |
1da177e4 LT |
1513 | if (cap & MCG_CTL_P) |
1514 | wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); | |
bb91f8c0 AG |
1515 | } |
1516 | ||
1517 | static void __mcheck_cpu_init_clear_banks(void) | |
1518 | { | |
1519 | int i; | |
1da177e4 | 1520 | |
d203f0b8 | 1521 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 1522 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 1523 | |
cebe1820 | 1524 | if (!b->init) |
06b7a7a5 | 1525 | continue; |
d9d73fcc YG |
1526 | wrmsrl(msr_ops.ctl(i), b->ctl); |
1527 | wrmsrl(msr_ops.status(i), 0); | |
d88203d1 | 1528 | } |
1da177e4 LT |
1529 | } |
1530 | ||
61b0fccd TL |
1531 | /* |
1532 | * During IFU recovery Sandy Bridge -EP4S processors set the RIPV and | |
1533 | * EIPV bits in MCG_STATUS to zero on the affected logical processor (SDM | |
1534 | * Vol 3B Table 15-20). But this confuses both the code that determines | |
1535 | * whether the machine check occurred in kernel or user mode, and also | |
1536 | * the severity assessment code. Pretend that EIPV was set, and take the | |
1537 | * ip/cs values from the pt_regs that mce_gather_info() ignored earlier. | |
1538 | */ | |
1539 | static void quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs) | |
1540 | { | |
1541 | if (bank != 0) | |
1542 | return; | |
1543 | if ((m->mcgstatus & (MCG_STATUS_EIPV|MCG_STATUS_RIPV)) != 0) | |
1544 | return; | |
1545 | if ((m->status & (MCI_STATUS_OVER|MCI_STATUS_UC| | |
1546 | MCI_STATUS_EN|MCI_STATUS_MISCV|MCI_STATUS_ADDRV| | |
1547 | MCI_STATUS_PCC|MCI_STATUS_S|MCI_STATUS_AR| | |
1548 | MCACOD)) != | |
1549 | (MCI_STATUS_UC|MCI_STATUS_EN| | |
1550 | MCI_STATUS_MISCV|MCI_STATUS_ADDRV|MCI_STATUS_S| | |
1551 | MCI_STATUS_AR|MCACOD_INSTR)) | |
1552 | return; | |
1553 | ||
1554 | m->mcgstatus |= MCG_STATUS_EIPV; | |
1555 | m->ip = regs->ip; | |
1556 | m->cs = regs->cs; | |
1557 | } | |
1558 | ||
1da177e4 | 1559 | /* Add per CPU specific workarounds here */ |
148f9bb8 | 1560 | static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) |
d88203d1 | 1561 | { |
d203f0b8 BP |
1562 | struct mca_config *cfg = &mca_cfg; |
1563 | ||
e412cd25 | 1564 | if (c->x86_vendor == X86_VENDOR_UNKNOWN) { |
c767a54b | 1565 | pr_info("unknown CPU type - not enabling MCE support\n"); |
e412cd25 IM |
1566 | return -EOPNOTSUPP; |
1567 | } | |
1568 | ||
1da177e4 | 1569 | /* This should be disabled by the BIOS, but isn't always */ |
911f6a7b | 1570 | if (c->x86_vendor == X86_VENDOR_AMD) { |
d203f0b8 | 1571 | if (c->x86 == 15 && cfg->banks > 4) { |
e9eee03e IM |
1572 | /* |
1573 | * disable GART TBL walk error reporting, which | |
1574 | * trips off incorrectly with the IOMMU & 3ware | |
1575 | * & Cerberus: | |
1576 | */ | |
cebe1820 | 1577 | clear_bit(10, (unsigned long *)&mce_banks[4].ctl); |
e9eee03e | 1578 | } |
10001d91 | 1579 | if (c->x86 < 17 && cfg->bootlog < 0) { |
e9eee03e IM |
1580 | /* |
1581 | * Lots of broken BIOS around that don't clear them | |
1582 | * by default and leave crap in there. Don't log: | |
1583 | */ | |
84c2559d | 1584 | cfg->bootlog = 0; |
e9eee03e | 1585 | } |
2e6f694f AK |
1586 | /* |
1587 | * Various K7s with broken bank 0 around. Always disable | |
1588 | * by default. | |
1589 | */ | |
c9ce8712 | 1590 | if (c->x86 == 6 && cfg->banks > 0) |
cebe1820 | 1591 | mce_banks[0].ctl = 0; |
575203b4 | 1592 | |
bf80bbd7 AG |
1593 | /* |
1594 | * overflow_recov is supported for F15h Models 00h-0fh | |
1595 | * even though we don't have a CPUID bit for it. | |
1596 | */ | |
1597 | if (c->x86 == 0x15 && c->x86_model <= 0xf) | |
1598 | mce_flags.overflow_recov = 1; | |
1599 | ||
c9ce8712 BP |
1600 | /* |
1601 | * Turn off MC4_MISC thresholding banks on those models since | |
1602 | * they're not supported there. | |
1603 | */ | |
1604 | if (c->x86 == 0x15 && | |
1605 | (c->x86_model >= 0x10 && c->x86_model <= 0x1f)) { | |
1606 | int i; | |
1607 | u64 hwcr; | |
1608 | bool need_toggle; | |
1609 | u32 msrs[] = { | |
575203b4 BP |
1610 | 0x00000413, /* MC4_MISC0 */ |
1611 | 0xc0000408, /* MC4_MISC1 */ | |
c9ce8712 | 1612 | }; |
575203b4 | 1613 | |
c9ce8712 | 1614 | rdmsrl(MSR_K7_HWCR, hwcr); |
575203b4 | 1615 | |
c9ce8712 BP |
1616 | /* McStatusWrEn has to be set */ |
1617 | need_toggle = !(hwcr & BIT(18)); | |
575203b4 | 1618 | |
c9ce8712 BP |
1619 | if (need_toggle) |
1620 | wrmsrl(MSR_K7_HWCR, hwcr | BIT(18)); | |
575203b4 | 1621 | |
c9ce8712 BP |
1622 | /* Clear CntP bit safely */ |
1623 | for (i = 0; i < ARRAY_SIZE(msrs); i++) | |
1624 | msr_clear_bit(msrs[i], 62); | |
575203b4 | 1625 | |
c9ce8712 BP |
1626 | /* restore old settings */ |
1627 | if (need_toggle) | |
1628 | wrmsrl(MSR_K7_HWCR, hwcr); | |
1629 | } | |
1da177e4 | 1630 | } |
e583538f | 1631 | |
06b7a7a5 AK |
1632 | if (c->x86_vendor == X86_VENDOR_INTEL) { |
1633 | /* | |
1634 | * SDM documents that on family 6 bank 0 should not be written | |
1635 | * because it aliases to another special BIOS controlled | |
1636 | * register. | |
1637 | * But it's not aliased anymore on model 0x1a+ | |
1638 | * Don't ignore bank 0 completely because there could be a | |
1639 | * valid event later, merely don't write CTL0. | |
1640 | */ | |
1641 | ||
d203f0b8 | 1642 | if (c->x86 == 6 && c->x86_model < 0x1A && cfg->banks > 0) |
cebe1820 | 1643 | mce_banks[0].init = 0; |
3c079792 AK |
1644 | |
1645 | /* | |
1646 | * All newer Intel systems support MCE broadcasting. Enable | |
1647 | * synchronization with a one second timeout. | |
1648 | */ | |
1649 | if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) && | |
84c2559d BP |
1650 | cfg->monarch_timeout < 0) |
1651 | cfg->monarch_timeout = USEC_PER_SEC; | |
c7f6fa44 | 1652 | |
e412cd25 IM |
1653 | /* |
1654 | * There are also broken BIOSes on some Pentium M and | |
1655 | * earlier systems: | |
1656 | */ | |
84c2559d BP |
1657 | if (c->x86 == 6 && c->x86_model <= 13 && cfg->bootlog < 0) |
1658 | cfg->bootlog = 0; | |
61b0fccd TL |
1659 | |
1660 | if (c->x86 == 6 && c->x86_model == 45) | |
1661 | quirk_no_way_out = quirk_sandybridge_ifu; | |
06b7a7a5 | 1662 | } |
84c2559d BP |
1663 | if (cfg->monarch_timeout < 0) |
1664 | cfg->monarch_timeout = 0; | |
1665 | if (cfg->bootlog != 0) | |
7af19e4a | 1666 | cfg->panic_timeout = 30; |
e412cd25 IM |
1667 | |
1668 | return 0; | |
d88203d1 | 1669 | } |
1da177e4 | 1670 | |
148f9bb8 | 1671 | static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) |
4efc0670 AK |
1672 | { |
1673 | if (c->x86 != 5) | |
3a97fc34 HS |
1674 | return 0; |
1675 | ||
4efc0670 AK |
1676 | switch (c->x86_vendor) { |
1677 | case X86_VENDOR_INTEL: | |
c6978369 | 1678 | intel_p5_mcheck_init(c); |
3a97fc34 | 1679 | return 1; |
4efc0670 AK |
1680 | break; |
1681 | case X86_VENDOR_CENTAUR: | |
1682 | winchip_mcheck_init(c); | |
3a97fc34 | 1683 | return 1; |
4efc0670 | 1684 | break; |
dc34bdd2 BP |
1685 | default: |
1686 | return 0; | |
4efc0670 | 1687 | } |
3a97fc34 HS |
1688 | |
1689 | return 0; | |
4efc0670 AK |
1690 | } |
1691 | ||
5e09954a | 1692 | static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) |
1da177e4 LT |
1693 | { |
1694 | switch (c->x86_vendor) { | |
1695 | case X86_VENDOR_INTEL: | |
1696 | mce_intel_feature_init(c); | |
3f2f0680 | 1697 | mce_adjust_timer = cmci_intel_adjust_timer; |
1da177e4 | 1698 | break; |
7559e13f AG |
1699 | |
1700 | case X86_VENDOR_AMD: { | |
14cddfd5 YG |
1701 | mce_flags.overflow_recov = !!cpu_has(c, X86_FEATURE_OVERFLOW_RECOV); |
1702 | mce_flags.succor = !!cpu_has(c, X86_FEATURE_SUCCOR); | |
1703 | mce_flags.smca = !!cpu_has(c, X86_FEATURE_SMCA); | |
d9d73fcc YG |
1704 | |
1705 | /* | |
1706 | * Install proper ops for Scalable MCA enabled processors | |
1707 | */ | |
1708 | if (mce_flags.smca) { | |
1709 | msr_ops.ctl = smca_ctl_reg; | |
1710 | msr_ops.status = smca_status_reg; | |
1711 | msr_ops.addr = smca_addr_reg; | |
1712 | msr_ops.misc = smca_misc_reg; | |
1713 | } | |
bfbe0eeb | 1714 | mce_amd_feature_init(c); |
c7f54d21 | 1715 | |
89b831ef | 1716 | break; |
7559e13f AG |
1717 | } |
1718 | ||
1da177e4 LT |
1719 | default: |
1720 | break; | |
1721 | } | |
1722 | } | |
1723 | ||
8838eb6c AR |
1724 | static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86 *c) |
1725 | { | |
1726 | switch (c->x86_vendor) { | |
1727 | case X86_VENDOR_INTEL: | |
1728 | mce_intel_feature_clear(c); | |
1729 | break; | |
1730 | default: | |
1731 | break; | |
1732 | } | |
1733 | } | |
1734 | ||
26c3c283 | 1735 | static void mce_start_timer(unsigned int cpu, struct timer_list *t) |
52d168e2 | 1736 | { |
4f75d841 | 1737 | unsigned long iv = check_interval * HZ; |
bc09effa | 1738 | |
7af19e4a | 1739 | if (mca_cfg.ignore_ce || !iv) |
62fdac59 HS |
1740 | return; |
1741 | ||
4f75d841 BP |
1742 | per_cpu(mce_next_interval, cpu) = iv; |
1743 | ||
82f7af09 | 1744 | t->expires = round_jiffies(jiffies + iv); |
4f75d841 | 1745 | add_timer_on(t, cpu); |
52d168e2 AK |
1746 | } |
1747 | ||
39f152ff SAS |
1748 | static void __mcheck_cpu_setup_timer(void) |
1749 | { | |
1750 | struct timer_list *t = this_cpu_ptr(&mce_timer); | |
1751 | unsigned int cpu = smp_processor_id(); | |
1752 | ||
1753 | setup_pinned_timer(t, mce_timer_fn, cpu); | |
1754 | } | |
1755 | ||
26c3c283 TG |
1756 | static void __mcheck_cpu_init_timer(void) |
1757 | { | |
89cbc767 | 1758 | struct timer_list *t = this_cpu_ptr(&mce_timer); |
26c3c283 TG |
1759 | unsigned int cpu = smp_processor_id(); |
1760 | ||
f9c287ba | 1761 | setup_pinned_timer(t, mce_timer_fn, cpu); |
26c3c283 TG |
1762 | mce_start_timer(cpu, t); |
1763 | } | |
1764 | ||
9eda8cb3 AK |
1765 | /* Handle unconfigured int18 (should never happen) */ |
1766 | static void unexpected_machine_check(struct pt_regs *regs, long error_code) | |
1767 | { | |
c767a54b | 1768 | pr_err("CPU#%d: Unexpected int18 (Machine Check)\n", |
9eda8cb3 AK |
1769 | smp_processor_id()); |
1770 | } | |
1771 | ||
1772 | /* Call the installed machine check handler for this CPU setup. */ | |
1773 | void (*machine_check_vector)(struct pt_regs *, long error_code) = | |
1774 | unexpected_machine_check; | |
1775 | ||
d88203d1 | 1776 | /* |
1da177e4 | 1777 | * Called for each booted CPU to set up machine checks. |
e9eee03e | 1778 | * Must be called with preempt off: |
1da177e4 | 1779 | */ |
148f9bb8 | 1780 | void mcheck_cpu_init(struct cpuinfo_x86 *c) |
1da177e4 | 1781 | { |
1462594b | 1782 | if (mca_cfg.disabled) |
4efc0670 AK |
1783 | return; |
1784 | ||
3a97fc34 HS |
1785 | if (__mcheck_cpu_ancient_init(c)) |
1786 | return; | |
4efc0670 | 1787 | |
5b4408fd | 1788 | if (!mce_available(c)) |
1da177e4 LT |
1789 | return; |
1790 | ||
5e09954a | 1791 | if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) { |
1462594b | 1792 | mca_cfg.disabled = true; |
0d7482e3 AK |
1793 | return; |
1794 | } | |
0d7482e3 | 1795 | |
648ed940 CG |
1796 | if (mce_gen_pool_init()) { |
1797 | mca_cfg.disabled = true; | |
1798 | pr_emerg("Couldn't allocate MCE records pool!\n"); | |
1799 | return; | |
1800 | } | |
1801 | ||
5d727926 AK |
1802 | machine_check_vector = do_machine_check; |
1803 | ||
5e09954a BP |
1804 | __mcheck_cpu_init_generic(); |
1805 | __mcheck_cpu_init_vendor(c); | |
bb91f8c0 | 1806 | __mcheck_cpu_init_clear_banks(); |
39f152ff | 1807 | __mcheck_cpu_setup_timer(); |
1da177e4 LT |
1808 | } |
1809 | ||
8838eb6c AR |
1810 | /* |
1811 | * Called for each booted CPU to clear some machine checks opt-ins | |
1812 | */ | |
1813 | void mcheck_cpu_clear(struct cpuinfo_x86 *c) | |
1814 | { | |
1815 | if (mca_cfg.disabled) | |
1816 | return; | |
1817 | ||
1818 | if (!mce_available(c)) | |
1819 | return; | |
1820 | ||
1821 | /* | |
1822 | * Possibly to clear general settings generic to x86 | |
1823 | * __mcheck_cpu_clear_generic(c); | |
1824 | */ | |
1825 | __mcheck_cpu_clear_vendor(c); | |
1826 | ||
1da177e4 LT |
1827 | } |
1828 | ||
1829 | /* | |
93b62c3c | 1830 | * mce_chrdev: Character device /dev/mcelog to read and clear the MCE log. |
1da177e4 LT |
1831 | */ |
1832 | ||
93b62c3c HS |
1833 | static DEFINE_SPINLOCK(mce_chrdev_state_lock); |
1834 | static int mce_chrdev_open_count; /* #times opened */ | |
1835 | static int mce_chrdev_open_exclu; /* already open exclusive? */ | |
f528e7ba | 1836 | |
93b62c3c | 1837 | static int mce_chrdev_open(struct inode *inode, struct file *file) |
f528e7ba | 1838 | { |
93b62c3c | 1839 | spin_lock(&mce_chrdev_state_lock); |
f528e7ba | 1840 | |
93b62c3c HS |
1841 | if (mce_chrdev_open_exclu || |
1842 | (mce_chrdev_open_count && (file->f_flags & O_EXCL))) { | |
1843 | spin_unlock(&mce_chrdev_state_lock); | |
e9eee03e | 1844 | |
f528e7ba TH |
1845 | return -EBUSY; |
1846 | } | |
1847 | ||
1848 | if (file->f_flags & O_EXCL) | |
93b62c3c HS |
1849 | mce_chrdev_open_exclu = 1; |
1850 | mce_chrdev_open_count++; | |
f528e7ba | 1851 | |
93b62c3c | 1852 | spin_unlock(&mce_chrdev_state_lock); |
f528e7ba | 1853 | |
bd78432c | 1854 | return nonseekable_open(inode, file); |
f528e7ba TH |
1855 | } |
1856 | ||
93b62c3c | 1857 | static int mce_chrdev_release(struct inode *inode, struct file *file) |
f528e7ba | 1858 | { |
93b62c3c | 1859 | spin_lock(&mce_chrdev_state_lock); |
f528e7ba | 1860 | |
93b62c3c HS |
1861 | mce_chrdev_open_count--; |
1862 | mce_chrdev_open_exclu = 0; | |
f528e7ba | 1863 | |
93b62c3c | 1864 | spin_unlock(&mce_chrdev_state_lock); |
f528e7ba TH |
1865 | |
1866 | return 0; | |
1867 | } | |
1868 | ||
d88203d1 TG |
1869 | static void collect_tscs(void *data) |
1870 | { | |
1da177e4 | 1871 | unsigned long *cpu_tsc = (unsigned long *)data; |
d88203d1 | 1872 | |
4ea1636b | 1873 | cpu_tsc[smp_processor_id()] = rdtsc(); |
d88203d1 | 1874 | } |
1da177e4 | 1875 | |
482908b4 HY |
1876 | static int mce_apei_read_done; |
1877 | ||
1878 | /* Collect MCE record of previous boot in persistent storage via APEI ERST. */ | |
1879 | static int __mce_read_apei(char __user **ubuf, size_t usize) | |
1880 | { | |
1881 | int rc; | |
1882 | u64 record_id; | |
1883 | struct mce m; | |
1884 | ||
1885 | if (usize < sizeof(struct mce)) | |
1886 | return -EINVAL; | |
1887 | ||
1888 | rc = apei_read_mce(&m, &record_id); | |
1889 | /* Error or no more MCE record */ | |
1890 | if (rc <= 0) { | |
1891 | mce_apei_read_done = 1; | |
fadd85f1 NH |
1892 | /* |
1893 | * When ERST is disabled, mce_chrdev_read() should return | |
1894 | * "no record" instead of "no device." | |
1895 | */ | |
1896 | if (rc == -ENODEV) | |
1897 | return 0; | |
482908b4 HY |
1898 | return rc; |
1899 | } | |
1900 | rc = -EFAULT; | |
1901 | if (copy_to_user(*ubuf, &m, sizeof(struct mce))) | |
1902 | return rc; | |
1903 | /* | |
1904 | * In fact, we should have cleared the record after that has | |
1905 | * been flushed to the disk or sent to network in | |
1906 | * /sbin/mcelog, but we have no interface to support that now, | |
1907 | * so just clear it to avoid duplication. | |
1908 | */ | |
1909 | rc = apei_clear_mce(record_id); | |
1910 | if (rc) { | |
1911 | mce_apei_read_done = 1; | |
1912 | return rc; | |
1913 | } | |
1914 | *ubuf += sizeof(struct mce); | |
1915 | ||
1916 | return 0; | |
1917 | } | |
1918 | ||
93b62c3c HS |
1919 | static ssize_t mce_chrdev_read(struct file *filp, char __user *ubuf, |
1920 | size_t usize, loff_t *off) | |
1da177e4 | 1921 | { |
e9eee03e | 1922 | char __user *buf = ubuf; |
f0de53bb | 1923 | unsigned long *cpu_tsc; |
ef41df43 | 1924 | unsigned prev, next; |
1da177e4 LT |
1925 | int i, err; |
1926 | ||
6bca67f9 | 1927 | cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL); |
f0de53bb AK |
1928 | if (!cpu_tsc) |
1929 | return -ENOMEM; | |
1930 | ||
93b62c3c | 1931 | mutex_lock(&mce_chrdev_read_mutex); |
482908b4 HY |
1932 | |
1933 | if (!mce_apei_read_done) { | |
1934 | err = __mce_read_apei(&buf, usize); | |
1935 | if (err || buf != ubuf) | |
1936 | goto out; | |
1937 | } | |
1938 | ||
9a7783d0 | 1939 | next = mce_log_get_idx_check(mcelog.next); |
1da177e4 LT |
1940 | |
1941 | /* Only supports full reads right now */ | |
482908b4 HY |
1942 | err = -EINVAL; |
1943 | if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) | |
1944 | goto out; | |
1da177e4 LT |
1945 | |
1946 | err = 0; | |
ef41df43 HY |
1947 | prev = 0; |
1948 | do { | |
1949 | for (i = prev; i < next; i++) { | |
1950 | unsigned long start = jiffies; | |
559faa6b | 1951 | struct mce *m = &mcelog.entry[i]; |
ef41df43 | 1952 | |
559faa6b | 1953 | while (!m->finished) { |
ef41df43 | 1954 | if (time_after_eq(jiffies, start + 2)) { |
559faa6b | 1955 | memset(m, 0, sizeof(*m)); |
ef41df43 HY |
1956 | goto timeout; |
1957 | } | |
1958 | cpu_relax(); | |
673242c1 | 1959 | } |
ef41df43 | 1960 | smp_rmb(); |
559faa6b HS |
1961 | err |= copy_to_user(buf, m, sizeof(*m)); |
1962 | buf += sizeof(*m); | |
ef41df43 HY |
1963 | timeout: |
1964 | ; | |
673242c1 | 1965 | } |
1da177e4 | 1966 | |
ef41df43 HY |
1967 | memset(mcelog.entry + prev, 0, |
1968 | (next - prev) * sizeof(struct mce)); | |
1969 | prev = next; | |
1970 | next = cmpxchg(&mcelog.next, prev, 0); | |
1971 | } while (next != prev); | |
1da177e4 | 1972 | |
b2b18660 | 1973 | synchronize_sched(); |
1da177e4 | 1974 | |
d88203d1 TG |
1975 | /* |
1976 | * Collect entries that were still getting written before the | |
1977 | * synchronize. | |
1978 | */ | |
15c8b6c1 | 1979 | on_each_cpu(collect_tscs, cpu_tsc, 1); |
e9eee03e | 1980 | |
d88203d1 | 1981 | for (i = next; i < MCE_LOG_LEN; i++) { |
559faa6b HS |
1982 | struct mce *m = &mcelog.entry[i]; |
1983 | ||
1984 | if (m->finished && m->tsc < cpu_tsc[m->cpu]) { | |
1985 | err |= copy_to_user(buf, m, sizeof(*m)); | |
1da177e4 | 1986 | smp_rmb(); |
559faa6b HS |
1987 | buf += sizeof(*m); |
1988 | memset(m, 0, sizeof(*m)); | |
1da177e4 | 1989 | } |
d88203d1 | 1990 | } |
482908b4 HY |
1991 | |
1992 | if (err) | |
1993 | err = -EFAULT; | |
1994 | ||
1995 | out: | |
93b62c3c | 1996 | mutex_unlock(&mce_chrdev_read_mutex); |
f0de53bb | 1997 | kfree(cpu_tsc); |
e9eee03e | 1998 | |
482908b4 | 1999 | return err ? err : buf - ubuf; |
1da177e4 LT |
2000 | } |
2001 | ||
93b62c3c | 2002 | static unsigned int mce_chrdev_poll(struct file *file, poll_table *wait) |
e02e68d3 | 2003 | { |
93b62c3c | 2004 | poll_wait(file, &mce_chrdev_wait, wait); |
e90328b8 | 2005 | if (READ_ONCE(mcelog.next)) |
e02e68d3 | 2006 | return POLLIN | POLLRDNORM; |
482908b4 HY |
2007 | if (!mce_apei_read_done && apei_check_mce()) |
2008 | return POLLIN | POLLRDNORM; | |
e02e68d3 TH |
2009 | return 0; |
2010 | } | |
2011 | ||
93b62c3c HS |
2012 | static long mce_chrdev_ioctl(struct file *f, unsigned int cmd, |
2013 | unsigned long arg) | |
1da177e4 LT |
2014 | { |
2015 | int __user *p = (int __user *)arg; | |
d88203d1 | 2016 | |
1da177e4 | 2017 | if (!capable(CAP_SYS_ADMIN)) |
d88203d1 | 2018 | return -EPERM; |
e9eee03e | 2019 | |
1da177e4 | 2020 | switch (cmd) { |
d88203d1 | 2021 | case MCE_GET_RECORD_LEN: |
1da177e4 LT |
2022 | return put_user(sizeof(struct mce), p); |
2023 | case MCE_GET_LOG_LEN: | |
d88203d1 | 2024 | return put_user(MCE_LOG_LEN, p); |
1da177e4 LT |
2025 | case MCE_GETCLEAR_FLAGS: { |
2026 | unsigned flags; | |
d88203d1 TG |
2027 | |
2028 | do { | |
1da177e4 | 2029 | flags = mcelog.flags; |
d88203d1 | 2030 | } while (cmpxchg(&mcelog.flags, flags, 0) != flags); |
e9eee03e | 2031 | |
d88203d1 | 2032 | return put_user(flags, p); |
1da177e4 LT |
2033 | } |
2034 | default: | |
d88203d1 TG |
2035 | return -ENOTTY; |
2036 | } | |
1da177e4 LT |
2037 | } |
2038 | ||
66f5ddf3 LT |
2039 | static ssize_t (*mce_write)(struct file *filp, const char __user *ubuf, |
2040 | size_t usize, loff_t *off); | |
2041 | ||
2042 | void register_mce_write_callback(ssize_t (*fn)(struct file *filp, | |
2043 | const char __user *ubuf, | |
2044 | size_t usize, loff_t *off)) | |
2045 | { | |
2046 | mce_write = fn; | |
2047 | } | |
2048 | EXPORT_SYMBOL_GPL(register_mce_write_callback); | |
2049 | ||
29c6820f PM |
2050 | static ssize_t mce_chrdev_write(struct file *filp, const char __user *ubuf, |
2051 | size_t usize, loff_t *off) | |
66f5ddf3 LT |
2052 | { |
2053 | if (mce_write) | |
2054 | return mce_write(filp, ubuf, usize, off); | |
2055 | else | |
2056 | return -EINVAL; | |
2057 | } | |
2058 | ||
2059 | static const struct file_operations mce_chrdev_ops = { | |
93b62c3c HS |
2060 | .open = mce_chrdev_open, |
2061 | .release = mce_chrdev_release, | |
2062 | .read = mce_chrdev_read, | |
66f5ddf3 | 2063 | .write = mce_chrdev_write, |
93b62c3c HS |
2064 | .poll = mce_chrdev_poll, |
2065 | .unlocked_ioctl = mce_chrdev_ioctl, | |
2066 | .llseek = no_llseek, | |
1da177e4 LT |
2067 | }; |
2068 | ||
93b62c3c | 2069 | static struct miscdevice mce_chrdev_device = { |
1da177e4 LT |
2070 | MISC_MCELOG_MINOR, |
2071 | "mcelog", | |
2072 | &mce_chrdev_ops, | |
2073 | }; | |
2074 | ||
c3d1fb56 NR |
2075 | static void __mce_disable_bank(void *arg) |
2076 | { | |
2077 | int bank = *((int *)arg); | |
89cbc767 | 2078 | __clear_bit(bank, this_cpu_ptr(mce_poll_banks)); |
c3d1fb56 NR |
2079 | cmci_disable_bank(bank); |
2080 | } | |
2081 | ||
2082 | void mce_disable_bank(int bank) | |
2083 | { | |
2084 | if (bank >= mca_cfg.banks) { | |
2085 | pr_warn(FW_BUG | |
2086 | "Ignoring request to disable invalid MCA bank %d.\n", | |
2087 | bank); | |
2088 | return; | |
2089 | } | |
2090 | set_bit(bank, mce_banks_ce_disabled); | |
2091 | on_each_cpu(__mce_disable_bank, &bank, 1); | |
2092 | } | |
2093 | ||
13503fa9 | 2094 | /* |
62fdac59 HS |
2095 | * mce=off Disables machine check |
2096 | * mce=no_cmci Disables CMCI | |
88d53867 | 2097 | * mce=no_lmce Disables LMCE |
62fdac59 HS |
2098 | * mce=dont_log_ce Clears corrected events silently, no log created for CEs. |
2099 | * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared. | |
3c079792 AK |
2100 | * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above) |
2101 | * monarchtimeout is how long to wait for other CPUs on machine | |
2102 | * check, or 0 to not wait | |
13503fa9 HS |
2103 | * mce=bootlog Log MCEs from before booting. Disabled by default on AMD. |
2104 | * mce=nobootlog Don't log MCEs from before booting. | |
450cc201 | 2105 | * mce=bios_cmci_threshold Don't program the CMCI threshold |
3637efb0 | 2106 | * mce=recovery force enable memcpy_mcsafe() |
13503fa9 | 2107 | */ |
1da177e4 LT |
2108 | static int __init mcheck_enable(char *str) |
2109 | { | |
d203f0b8 BP |
2110 | struct mca_config *cfg = &mca_cfg; |
2111 | ||
e3346fc4 | 2112 | if (*str == 0) { |
4efc0670 | 2113 | enable_p5_mce(); |
e3346fc4 BZ |
2114 | return 1; |
2115 | } | |
4efc0670 AK |
2116 | if (*str == '=') |
2117 | str++; | |
1da177e4 | 2118 | if (!strcmp(str, "off")) |
1462594b | 2119 | cfg->disabled = true; |
62fdac59 | 2120 | else if (!strcmp(str, "no_cmci")) |
7af19e4a | 2121 | cfg->cmci_disabled = true; |
88d53867 AR |
2122 | else if (!strcmp(str, "no_lmce")) |
2123 | cfg->lmce_disabled = true; | |
62fdac59 | 2124 | else if (!strcmp(str, "dont_log_ce")) |
d203f0b8 | 2125 | cfg->dont_log_ce = true; |
62fdac59 | 2126 | else if (!strcmp(str, "ignore_ce")) |
7af19e4a | 2127 | cfg->ignore_ce = true; |
13503fa9 | 2128 | else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog")) |
84c2559d | 2129 | cfg->bootlog = (str[0] == 'b'); |
450cc201 | 2130 | else if (!strcmp(str, "bios_cmci_threshold")) |
1462594b | 2131 | cfg->bios_cmci_threshold = true; |
0f68c088 TL |
2132 | else if (!strcmp(str, "recovery")) |
2133 | cfg->recovery = true; | |
3c079792 | 2134 | else if (isdigit(str[0])) { |
5c31b280 | 2135 | if (get_option(&str, &cfg->tolerant) == 2) |
84c2559d | 2136 | get_option(&str, &(cfg->monarch_timeout)); |
3c079792 | 2137 | } else { |
c767a54b | 2138 | pr_info("mce argument %s ignored. Please use /sys\n", str); |
13503fa9 HS |
2139 | return 0; |
2140 | } | |
9b41046c | 2141 | return 1; |
1da177e4 | 2142 | } |
4efc0670 | 2143 | __setup("mce", mcheck_enable); |
1da177e4 | 2144 | |
a2202aa2 | 2145 | int __init mcheck_init(void) |
b33a6363 | 2146 | { |
a2202aa2 | 2147 | mcheck_intel_therm_init(); |
eef4dfa0 | 2148 | mce_register_decode_chain(&mce_srao_nb); |
43eaa2a1 | 2149 | mcheck_vendor_init_severity(); |
a2202aa2 | 2150 | |
061120ae CG |
2151 | INIT_WORK(&mce_work, mce_process_work); |
2152 | init_irq_work(&mce_irq_work, mce_irq_work_cb); | |
2153 | ||
b33a6363 BP |
2154 | return 0; |
2155 | } | |
b33a6363 | 2156 | |
d88203d1 | 2157 | /* |
c7cece89 | 2158 | * mce_syscore: PM support |
d88203d1 | 2159 | */ |
1da177e4 | 2160 | |
973a2dd1 AK |
2161 | /* |
2162 | * Disable machine checks on suspend and shutdown. We can't really handle | |
2163 | * them later. | |
2164 | */ | |
6e06780a | 2165 | static void mce_disable_error_reporting(void) |
973a2dd1 AK |
2166 | { |
2167 | int i; | |
2168 | ||
d203f0b8 | 2169 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 2170 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 2171 | |
cebe1820 | 2172 | if (b->init) |
d9d73fcc | 2173 | wrmsrl(msr_ops.ctl(i), 0); |
06b7a7a5 | 2174 | } |
6e06780a AR |
2175 | return; |
2176 | } | |
2177 | ||
2178 | static void vendor_disable_error_reporting(void) | |
2179 | { | |
2180 | /* | |
2181 | * Don't clear on Intel CPUs. Some of these MSRs are socket-wide. | |
2182 | * Disabling them for just a single offlined CPU is bad, since it will | |
2183 | * inhibit reporting for all shared resources on the socket like the | |
2184 | * last level cache (LLC), the integrated memory controller (iMC), etc. | |
2185 | */ | |
2186 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) | |
2187 | return; | |
2188 | ||
2189 | mce_disable_error_reporting(); | |
973a2dd1 AK |
2190 | } |
2191 | ||
c7cece89 | 2192 | static int mce_syscore_suspend(void) |
973a2dd1 | 2193 | { |
6e06780a AR |
2194 | vendor_disable_error_reporting(); |
2195 | return 0; | |
973a2dd1 AK |
2196 | } |
2197 | ||
c7cece89 | 2198 | static void mce_syscore_shutdown(void) |
973a2dd1 | 2199 | { |
6e06780a | 2200 | vendor_disable_error_reporting(); |
973a2dd1 AK |
2201 | } |
2202 | ||
e9eee03e IM |
2203 | /* |
2204 | * On resume clear all MCE state. Don't want to see leftovers from the BIOS. | |
2205 | * Only one CPU is active at this time, the others get re-added later using | |
2206 | * CPU hotplug: | |
2207 | */ | |
c7cece89 | 2208 | static void mce_syscore_resume(void) |
1da177e4 | 2209 | { |
5e09954a | 2210 | __mcheck_cpu_init_generic(); |
89cbc767 | 2211 | __mcheck_cpu_init_vendor(raw_cpu_ptr(&cpu_info)); |
bb91f8c0 | 2212 | __mcheck_cpu_init_clear_banks(); |
1da177e4 LT |
2213 | } |
2214 | ||
f3c6ea1b | 2215 | static struct syscore_ops mce_syscore_ops = { |
c7cece89 HS |
2216 | .suspend = mce_syscore_suspend, |
2217 | .shutdown = mce_syscore_shutdown, | |
2218 | .resume = mce_syscore_resume, | |
f3c6ea1b RW |
2219 | }; |
2220 | ||
c7cece89 | 2221 | /* |
8a25a2fd | 2222 | * mce_device: Sysfs support |
c7cece89 HS |
2223 | */ |
2224 | ||
52d168e2 AK |
2225 | static void mce_cpu_restart(void *data) |
2226 | { | |
89cbc767 | 2227 | if (!mce_available(raw_cpu_ptr(&cpu_info))) |
33edbf02 | 2228 | return; |
5e09954a | 2229 | __mcheck_cpu_init_generic(); |
bb91f8c0 | 2230 | __mcheck_cpu_init_clear_banks(); |
5e09954a | 2231 | __mcheck_cpu_init_timer(); |
52d168e2 AK |
2232 | } |
2233 | ||
1da177e4 | 2234 | /* Reinit MCEs after user configuration changes */ |
d88203d1 TG |
2235 | static void mce_restart(void) |
2236 | { | |
9aaef96f | 2237 | mce_timer_delete_all(); |
52d168e2 | 2238 | on_each_cpu(mce_cpu_restart, NULL, 1); |
1da177e4 LT |
2239 | } |
2240 | ||
9af43b54 | 2241 | /* Toggle features for corrected errors */ |
9aaef96f | 2242 | static void mce_disable_cmci(void *data) |
9af43b54 | 2243 | { |
89cbc767 | 2244 | if (!mce_available(raw_cpu_ptr(&cpu_info))) |
9af43b54 | 2245 | return; |
9af43b54 HS |
2246 | cmci_clear(); |
2247 | } | |
2248 | ||
2249 | static void mce_enable_ce(void *all) | |
2250 | { | |
89cbc767 | 2251 | if (!mce_available(raw_cpu_ptr(&cpu_info))) |
9af43b54 HS |
2252 | return; |
2253 | cmci_reenable(); | |
2254 | cmci_recheck(); | |
2255 | if (all) | |
5e09954a | 2256 | __mcheck_cpu_init_timer(); |
9af43b54 HS |
2257 | } |
2258 | ||
8a25a2fd | 2259 | static struct bus_type mce_subsys = { |
e9eee03e | 2260 | .name = "machinecheck", |
8a25a2fd | 2261 | .dev_name = "machinecheck", |
1da177e4 LT |
2262 | }; |
2263 | ||
d6126ef5 | 2264 | DEFINE_PER_CPU(struct device *, mce_device); |
e9eee03e | 2265 | |
8a25a2fd | 2266 | static inline struct mce_bank *attr_to_bank(struct device_attribute *attr) |
cebe1820 AK |
2267 | { |
2268 | return container_of(attr, struct mce_bank, attr); | |
2269 | } | |
0d7482e3 | 2270 | |
8a25a2fd | 2271 | static ssize_t show_bank(struct device *s, struct device_attribute *attr, |
0d7482e3 AK |
2272 | char *buf) |
2273 | { | |
cebe1820 | 2274 | return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl); |
0d7482e3 AK |
2275 | } |
2276 | ||
8a25a2fd | 2277 | static ssize_t set_bank(struct device *s, struct device_attribute *attr, |
9319cec8 | 2278 | const char *buf, size_t size) |
0d7482e3 | 2279 | { |
9319cec8 | 2280 | u64 new; |
e9eee03e | 2281 | |
164109e3 | 2282 | if (kstrtou64(buf, 0, &new) < 0) |
0d7482e3 | 2283 | return -EINVAL; |
e9eee03e | 2284 | |
cebe1820 | 2285 | attr_to_bank(attr)->ctl = new; |
0d7482e3 | 2286 | mce_restart(); |
e9eee03e | 2287 | |
9319cec8 | 2288 | return size; |
0d7482e3 | 2289 | } |
a98f0dd3 | 2290 | |
e9eee03e | 2291 | static ssize_t |
8a25a2fd | 2292 | show_trigger(struct device *s, struct device_attribute *attr, char *buf) |
a98f0dd3 | 2293 | { |
1020bcbc | 2294 | strcpy(buf, mce_helper); |
a98f0dd3 | 2295 | strcat(buf, "\n"); |
1020bcbc | 2296 | return strlen(mce_helper) + 1; |
a98f0dd3 AK |
2297 | } |
2298 | ||
8a25a2fd | 2299 | static ssize_t set_trigger(struct device *s, struct device_attribute *attr, |
e9eee03e | 2300 | const char *buf, size_t siz) |
a98f0dd3 AK |
2301 | { |
2302 | char *p; | |
e9eee03e | 2303 | |
1020bcbc HS |
2304 | strncpy(mce_helper, buf, sizeof(mce_helper)); |
2305 | mce_helper[sizeof(mce_helper)-1] = 0; | |
1020bcbc | 2306 | p = strchr(mce_helper, '\n'); |
e9eee03e | 2307 | |
e9084ec9 | 2308 | if (p) |
e9eee03e IM |
2309 | *p = 0; |
2310 | ||
e9084ec9 | 2311 | return strlen(mce_helper) + !!p; |
a98f0dd3 AK |
2312 | } |
2313 | ||
8a25a2fd KS |
2314 | static ssize_t set_ignore_ce(struct device *s, |
2315 | struct device_attribute *attr, | |
9af43b54 HS |
2316 | const char *buf, size_t size) |
2317 | { | |
2318 | u64 new; | |
2319 | ||
164109e3 | 2320 | if (kstrtou64(buf, 0, &new) < 0) |
9af43b54 HS |
2321 | return -EINVAL; |
2322 | ||
7af19e4a | 2323 | if (mca_cfg.ignore_ce ^ !!new) { |
9af43b54 HS |
2324 | if (new) { |
2325 | /* disable ce features */ | |
9aaef96f HS |
2326 | mce_timer_delete_all(); |
2327 | on_each_cpu(mce_disable_cmci, NULL, 1); | |
7af19e4a | 2328 | mca_cfg.ignore_ce = true; |
9af43b54 HS |
2329 | } else { |
2330 | /* enable ce features */ | |
7af19e4a | 2331 | mca_cfg.ignore_ce = false; |
9af43b54 HS |
2332 | on_each_cpu(mce_enable_ce, (void *)1, 1); |
2333 | } | |
2334 | } | |
2335 | return size; | |
2336 | } | |
2337 | ||
8a25a2fd KS |
2338 | static ssize_t set_cmci_disabled(struct device *s, |
2339 | struct device_attribute *attr, | |
9af43b54 HS |
2340 | const char *buf, size_t size) |
2341 | { | |
2342 | u64 new; | |
2343 | ||
164109e3 | 2344 | if (kstrtou64(buf, 0, &new) < 0) |
9af43b54 HS |
2345 | return -EINVAL; |
2346 | ||
7af19e4a | 2347 | if (mca_cfg.cmci_disabled ^ !!new) { |
9af43b54 HS |
2348 | if (new) { |
2349 | /* disable cmci */ | |
9aaef96f | 2350 | on_each_cpu(mce_disable_cmci, NULL, 1); |
7af19e4a | 2351 | mca_cfg.cmci_disabled = true; |
9af43b54 HS |
2352 | } else { |
2353 | /* enable cmci */ | |
7af19e4a | 2354 | mca_cfg.cmci_disabled = false; |
9af43b54 HS |
2355 | on_each_cpu(mce_enable_ce, NULL, 1); |
2356 | } | |
2357 | } | |
2358 | return size; | |
2359 | } | |
2360 | ||
8a25a2fd KS |
2361 | static ssize_t store_int_with_restart(struct device *s, |
2362 | struct device_attribute *attr, | |
b56f642d AK |
2363 | const char *buf, size_t size) |
2364 | { | |
8a25a2fd | 2365 | ssize_t ret = device_store_int(s, attr, buf, size); |
b56f642d AK |
2366 | mce_restart(); |
2367 | return ret; | |
2368 | } | |
2369 | ||
8a25a2fd | 2370 | static DEVICE_ATTR(trigger, 0644, show_trigger, set_trigger); |
d203f0b8 | 2371 | static DEVICE_INT_ATTR(tolerant, 0644, mca_cfg.tolerant); |
84c2559d | 2372 | static DEVICE_INT_ATTR(monarch_timeout, 0644, mca_cfg.monarch_timeout); |
d203f0b8 | 2373 | static DEVICE_BOOL_ATTR(dont_log_ce, 0644, mca_cfg.dont_log_ce); |
e9eee03e | 2374 | |
8a25a2fd KS |
2375 | static struct dev_ext_attribute dev_attr_check_interval = { |
2376 | __ATTR(check_interval, 0644, device_show_int, store_int_with_restart), | |
b56f642d AK |
2377 | &check_interval |
2378 | }; | |
e9eee03e | 2379 | |
8a25a2fd | 2380 | static struct dev_ext_attribute dev_attr_ignore_ce = { |
7af19e4a BP |
2381 | __ATTR(ignore_ce, 0644, device_show_bool, set_ignore_ce), |
2382 | &mca_cfg.ignore_ce | |
9af43b54 HS |
2383 | }; |
2384 | ||
8a25a2fd | 2385 | static struct dev_ext_attribute dev_attr_cmci_disabled = { |
7af19e4a BP |
2386 | __ATTR(cmci_disabled, 0644, device_show_bool, set_cmci_disabled), |
2387 | &mca_cfg.cmci_disabled | |
9af43b54 HS |
2388 | }; |
2389 | ||
8a25a2fd KS |
2390 | static struct device_attribute *mce_device_attrs[] = { |
2391 | &dev_attr_tolerant.attr, | |
2392 | &dev_attr_check_interval.attr, | |
2393 | &dev_attr_trigger, | |
2394 | &dev_attr_monarch_timeout.attr, | |
2395 | &dev_attr_dont_log_ce.attr, | |
2396 | &dev_attr_ignore_ce.attr, | |
2397 | &dev_attr_cmci_disabled.attr, | |
a98f0dd3 AK |
2398 | NULL |
2399 | }; | |
1da177e4 | 2400 | |
8a25a2fd | 2401 | static cpumask_var_t mce_device_initialized; |
bae19fe0 | 2402 | |
e032d807 GKH |
2403 | static void mce_device_release(struct device *dev) |
2404 | { | |
2405 | kfree(dev); | |
2406 | } | |
2407 | ||
8a25a2fd | 2408 | /* Per cpu device init. All of the cpus still share the same ctrl bank: */ |
148f9bb8 | 2409 | static int mce_device_create(unsigned int cpu) |
1da177e4 | 2410 | { |
e032d807 | 2411 | struct device *dev; |
1da177e4 | 2412 | int err; |
b1f49f95 | 2413 | int i, j; |
92cb7612 | 2414 | |
90367556 | 2415 | if (!mce_available(&boot_cpu_data)) |
91c6d400 AK |
2416 | return -EIO; |
2417 | ||
7f34b935 SAS |
2418 | dev = per_cpu(mce_device, cpu); |
2419 | if (dev) | |
2420 | return 0; | |
2421 | ||
e032d807 GKH |
2422 | dev = kzalloc(sizeof *dev, GFP_KERNEL); |
2423 | if (!dev) | |
2424 | return -ENOMEM; | |
8a25a2fd KS |
2425 | dev->id = cpu; |
2426 | dev->bus = &mce_subsys; | |
e032d807 | 2427 | dev->release = &mce_device_release; |
91c6d400 | 2428 | |
8a25a2fd | 2429 | err = device_register(dev); |
853d9b18 LK |
2430 | if (err) { |
2431 | put_device(dev); | |
d435d862 | 2432 | return err; |
853d9b18 | 2433 | } |
d435d862 | 2434 | |
8a25a2fd KS |
2435 | for (i = 0; mce_device_attrs[i]; i++) { |
2436 | err = device_create_file(dev, mce_device_attrs[i]); | |
d435d862 AM |
2437 | if (err) |
2438 | goto error; | |
2439 | } | |
d203f0b8 | 2440 | for (j = 0; j < mca_cfg.banks; j++) { |
8a25a2fd | 2441 | err = device_create_file(dev, &mce_banks[j].attr); |
0d7482e3 AK |
2442 | if (err) |
2443 | goto error2; | |
2444 | } | |
8a25a2fd | 2445 | cpumask_set_cpu(cpu, mce_device_initialized); |
d6126ef5 | 2446 | per_cpu(mce_device, cpu) = dev; |
91c6d400 | 2447 | |
d435d862 | 2448 | return 0; |
0d7482e3 | 2449 | error2: |
b1f49f95 | 2450 | while (--j >= 0) |
8a25a2fd | 2451 | device_remove_file(dev, &mce_banks[j].attr); |
d435d862 | 2452 | error: |
cb491fca | 2453 | while (--i >= 0) |
8a25a2fd | 2454 | device_remove_file(dev, mce_device_attrs[i]); |
cb491fca | 2455 | |
8a25a2fd | 2456 | device_unregister(dev); |
d435d862 | 2457 | |
91c6d400 AK |
2458 | return err; |
2459 | } | |
2460 | ||
148f9bb8 | 2461 | static void mce_device_remove(unsigned int cpu) |
91c6d400 | 2462 | { |
d6126ef5 | 2463 | struct device *dev = per_cpu(mce_device, cpu); |
73ca5358 SL |
2464 | int i; |
2465 | ||
8a25a2fd | 2466 | if (!cpumask_test_cpu(cpu, mce_device_initialized)) |
bae19fe0 AH |
2467 | return; |
2468 | ||
8a25a2fd KS |
2469 | for (i = 0; mce_device_attrs[i]; i++) |
2470 | device_remove_file(dev, mce_device_attrs[i]); | |
cb491fca | 2471 | |
d203f0b8 | 2472 | for (i = 0; i < mca_cfg.banks; i++) |
8a25a2fd | 2473 | device_remove_file(dev, &mce_banks[i].attr); |
cb491fca | 2474 | |
8a25a2fd KS |
2475 | device_unregister(dev); |
2476 | cpumask_clear_cpu(cpu, mce_device_initialized); | |
d6126ef5 | 2477 | per_cpu(mce_device, cpu) = NULL; |
91c6d400 | 2478 | } |
91c6d400 | 2479 | |
d6b75584 | 2480 | /* Make sure there are no machine checks on offlined CPUs. */ |
39f152ff | 2481 | static void mce_disable_cpu(void) |
d6b75584 | 2482 | { |
89cbc767 | 2483 | if (!mce_available(raw_cpu_ptr(&cpu_info))) |
d6b75584 | 2484 | return; |
767df1bd | 2485 | |
39f152ff | 2486 | if (!cpuhp_tasks_frozen) |
88ccbedd | 2487 | cmci_clear(); |
11868a2d | 2488 | |
6e06780a | 2489 | vendor_disable_error_reporting(); |
d6b75584 AK |
2490 | } |
2491 | ||
39f152ff | 2492 | static void mce_reenable_cpu(void) |
d6b75584 | 2493 | { |
e9eee03e | 2494 | int i; |
d6b75584 | 2495 | |
89cbc767 | 2496 | if (!mce_available(raw_cpu_ptr(&cpu_info))) |
d6b75584 | 2497 | return; |
e9eee03e | 2498 | |
39f152ff | 2499 | if (!cpuhp_tasks_frozen) |
88ccbedd | 2500 | cmci_reenable(); |
d203f0b8 | 2501 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 2502 | struct mce_bank *b = &mce_banks[i]; |
11868a2d | 2503 | |
cebe1820 | 2504 | if (b->init) |
d9d73fcc | 2505 | wrmsrl(msr_ops.ctl(i), b->ctl); |
06b7a7a5 | 2506 | } |
d6b75584 AK |
2507 | } |
2508 | ||
0e285d36 | 2509 | static int mce_cpu_dead(unsigned int cpu) |
91c6d400 | 2510 | { |
0e285d36 | 2511 | mce_intel_hcpu_update(cpu); |
91c6d400 | 2512 | |
0e285d36 SAS |
2513 | /* intentionally ignoring frozen here */ |
2514 | if (!cpuhp_tasks_frozen) | |
2515 | cmci_rediscover(); | |
2516 | return 0; | |
91c6d400 AK |
2517 | } |
2518 | ||
8c0eeac8 SAS |
2519 | static int mce_cpu_online(unsigned int cpu) |
2520 | { | |
2521 | struct timer_list *t = &per_cpu(mce_timer, cpu); | |
2522 | int ret; | |
2523 | ||
2524 | mce_device_create(cpu); | |
2525 | ||
2526 | ret = mce_threshold_create_device(cpu); | |
2527 | if (ret) { | |
2528 | mce_device_remove(cpu); | |
2529 | return ret; | |
2530 | } | |
2531 | mce_reenable_cpu(); | |
2532 | mce_start_timer(cpu, t); | |
2533 | return 0; | |
2534 | } | |
2535 | ||
2536 | static int mce_cpu_pre_down(unsigned int cpu) | |
2537 | { | |
2538 | struct timer_list *t = &per_cpu(mce_timer, cpu); | |
2539 | ||
2540 | mce_disable_cpu(); | |
2541 | del_timer_sync(t); | |
2542 | mce_threshold_remove_device(cpu); | |
2543 | mce_device_remove(cpu); | |
2544 | return 0; | |
2545 | } | |
2546 | ||
cebe1820 | 2547 | static __init void mce_init_banks(void) |
0d7482e3 AK |
2548 | { |
2549 | int i; | |
2550 | ||
d203f0b8 | 2551 | for (i = 0; i < mca_cfg.banks; i++) { |
cebe1820 | 2552 | struct mce_bank *b = &mce_banks[i]; |
8a25a2fd | 2553 | struct device_attribute *a = &b->attr; |
e9eee03e | 2554 | |
a07e4156 | 2555 | sysfs_attr_init(&a->attr); |
cebe1820 AK |
2556 | a->attr.name = b->attrname; |
2557 | snprintf(b->attrname, ATTR_LEN, "bank%d", i); | |
e9eee03e IM |
2558 | |
2559 | a->attr.mode = 0644; | |
2560 | a->show = show_bank; | |
2561 | a->store = set_bank; | |
0d7482e3 | 2562 | } |
0d7482e3 AK |
2563 | } |
2564 | ||
5e09954a | 2565 | static __init int mcheck_init_device(void) |
91c6d400 | 2566 | { |
8c0eeac8 | 2567 | enum cpuhp_state hp_online; |
91c6d400 | 2568 | int err; |
91c6d400 | 2569 | |
9c15a24b MS |
2570 | if (!mce_available(&boot_cpu_data)) { |
2571 | err = -EIO; | |
2572 | goto err_out; | |
2573 | } | |
0d7482e3 | 2574 | |
9c15a24b MS |
2575 | if (!zalloc_cpumask_var(&mce_device_initialized, GFP_KERNEL)) { |
2576 | err = -ENOMEM; | |
2577 | goto err_out; | |
2578 | } | |
996867d0 | 2579 | |
cebe1820 | 2580 | mce_init_banks(); |
0d7482e3 | 2581 | |
8a25a2fd | 2582 | err = subsys_system_register(&mce_subsys, NULL); |
d435d862 | 2583 | if (err) |
9c15a24b | 2584 | goto err_out_mem; |
91c6d400 | 2585 | |
0e285d36 SAS |
2586 | err = cpuhp_setup_state(CPUHP_X86_MCE_DEAD, "x86/mce:dead", NULL, |
2587 | mce_cpu_dead); | |
2588 | if (err) | |
2589 | goto err_out_mem; | |
2590 | ||
8c0eeac8 SAS |
2591 | err = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/mce:online", |
2592 | mce_cpu_online, mce_cpu_pre_down); | |
2593 | if (err < 0) | |
0e285d36 | 2594 | goto err_out_online; |
8c0eeac8 | 2595 | hp_online = err; |
91c6d400 | 2596 | |
9c15a24b MS |
2597 | register_syscore_ops(&mce_syscore_ops); |
2598 | ||
93b62c3c | 2599 | /* register character device /dev/mcelog */ |
9c15a24b MS |
2600 | err = misc_register(&mce_chrdev_device); |
2601 | if (err) | |
2602 | goto err_register; | |
2603 | ||
2604 | return 0; | |
2605 | ||
2606 | err_register: | |
2607 | unregister_syscore_ops(&mce_syscore_ops); | |
8c0eeac8 | 2608 | cpuhp_remove_state(hp_online); |
9c15a24b | 2609 | |
0e285d36 SAS |
2610 | err_out_online: |
2611 | cpuhp_remove_state(CPUHP_X86_MCE_DEAD); | |
2612 | ||
9c15a24b MS |
2613 | err_out_mem: |
2614 | free_cpumask_var(mce_device_initialized); | |
2615 | ||
2616 | err_out: | |
2617 | pr_err("Unable to init device /dev/mcelog (rc: %d)\n", err); | |
e9eee03e | 2618 | |
1da177e4 | 2619 | return err; |
1da177e4 | 2620 | } |
cef12ee5 | 2621 | device_initcall_sync(mcheck_init_device); |
a988d334 | 2622 | |
d7c3c9a6 AK |
2623 | /* |
2624 | * Old style boot options parsing. Only for compatibility. | |
2625 | */ | |
2626 | static int __init mcheck_disable(char *str) | |
2627 | { | |
1462594b | 2628 | mca_cfg.disabled = true; |
d7c3c9a6 AK |
2629 | return 1; |
2630 | } | |
2631 | __setup("nomce", mcheck_disable); | |
a988d334 | 2632 | |
5be9ed25 HY |
2633 | #ifdef CONFIG_DEBUG_FS |
2634 | struct dentry *mce_get_debugfs_dir(void) | |
a988d334 | 2635 | { |
5be9ed25 | 2636 | static struct dentry *dmce; |
a988d334 | 2637 | |
5be9ed25 HY |
2638 | if (!dmce) |
2639 | dmce = debugfs_create_dir("mce", NULL); | |
a988d334 | 2640 | |
5be9ed25 HY |
2641 | return dmce; |
2642 | } | |
a988d334 | 2643 | |
bf783f9f HY |
2644 | static void mce_reset(void) |
2645 | { | |
2646 | cpu_missing = 0; | |
c7c9b392 | 2647 | atomic_set(&mce_fake_panicked, 0); |
bf783f9f HY |
2648 | atomic_set(&mce_executing, 0); |
2649 | atomic_set(&mce_callin, 0); | |
2650 | atomic_set(&global_nwo, 0); | |
2651 | } | |
a988d334 | 2652 | |
bf783f9f HY |
2653 | static int fake_panic_get(void *data, u64 *val) |
2654 | { | |
2655 | *val = fake_panic; | |
2656 | return 0; | |
a988d334 IM |
2657 | } |
2658 | ||
bf783f9f | 2659 | static int fake_panic_set(void *data, u64 val) |
a988d334 | 2660 | { |
bf783f9f HY |
2661 | mce_reset(); |
2662 | fake_panic = val; | |
2663 | return 0; | |
a988d334 | 2664 | } |
a988d334 | 2665 | |
bf783f9f HY |
2666 | DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get, |
2667 | fake_panic_set, "%llu\n"); | |
d7c3c9a6 | 2668 | |
5e09954a | 2669 | static int __init mcheck_debugfs_init(void) |
d7c3c9a6 | 2670 | { |
bf783f9f HY |
2671 | struct dentry *dmce, *ffake_panic; |
2672 | ||
2673 | dmce = mce_get_debugfs_dir(); | |
2674 | if (!dmce) | |
2675 | return -ENOMEM; | |
2676 | ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL, | |
2677 | &fake_panic_fops); | |
2678 | if (!ffake_panic) | |
2679 | return -ENOMEM; | |
2680 | ||
2681 | return 0; | |
d7c3c9a6 | 2682 | } |
fd4cf79f CG |
2683 | #else |
2684 | static int __init mcheck_debugfs_init(void) { return -EINVAL; } | |
5be9ed25 | 2685 | #endif |
fd4cf79f | 2686 | |
3637efb0 TL |
2687 | DEFINE_STATIC_KEY_FALSE(mcsafe_key); |
2688 | EXPORT_SYMBOL_GPL(mcsafe_key); | |
2689 | ||
fd4cf79f CG |
2690 | static int __init mcheck_late_init(void) |
2691 | { | |
3637efb0 TL |
2692 | if (mca_cfg.recovery) |
2693 | static_branch_inc(&mcsafe_key); | |
2694 | ||
fd4cf79f CG |
2695 | mcheck_debugfs_init(); |
2696 | ||
2697 | /* | |
2698 | * Flush out everything that has been logged during early boot, now that | |
2699 | * everything has been initialized (workqueues, decoders, ...). | |
2700 | */ | |
2701 | mce_schedule_work(); | |
2702 | ||
2703 | return 0; | |
2704 | } | |
2705 | late_initcall(mcheck_late_init); |