]>
Commit | Line | Data |
---|---|---|
2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
3e135d88 | 2 | /* |
6b44e72a | 3 | * CPU Microcode Update Driver for Linux |
3e135d88 | 4 | * |
cea58224 | 5 | * Copyright (C) 2000-2006 Tigran Aivazian <aivazian.tigran@gmail.com> |
6b44e72a | 6 | * 2006 Shaohua Li <shaohua.li@intel.com> |
14cfbe55 | 7 | * 2013-2016 Borislav Petkov <bp@alien8.de> |
3e135d88 | 8 | * |
fe055896 BP |
9 | * X86 CPU microcode early update for Linux: |
10 | * | |
11 | * Copyright (C) 2012 Fenghua Yu <fenghua.yu@intel.com> | |
12 | * H Peter Anvin" <hpa@zytor.com> | |
13 | * (C) 2015 Borislav Petkov <bp@alien8.de> | |
14 | * | |
6b44e72a | 15 | * This driver allows to upgrade microcode on x86 processors. |
3e135d88 | 16 | */ |
f58e1f53 | 17 | |
6b26e1bf | 18 | #define pr_fmt(fmt) "microcode: " fmt |
f58e1f53 | 19 | |
4bae1967 | 20 | #include <linux/platform_device.h> |
a5321aec | 21 | #include <linux/stop_machine.h> |
fe055896 | 22 | #include <linux/syscore_ops.h> |
4bae1967 | 23 | #include <linux/miscdevice.h> |
871b72dd | 24 | #include <linux/capability.h> |
fe055896 | 25 | #include <linux/firmware.h> |
4bae1967 | 26 | #include <linux/kernel.h> |
a5321aec | 27 | #include <linux/delay.h> |
3e135d88 PO |
28 | #include <linux/mutex.h> |
29 | #include <linux/cpu.h> | |
a5321aec | 30 | #include <linux/nmi.h> |
4bae1967 IM |
31 | #include <linux/fs.h> |
32 | #include <linux/mm.h> | |
3e135d88 | 33 | |
fe055896 | 34 | #include <asm/microcode_intel.h> |
78ff123b | 35 | #include <asm/cpu_device_id.h> |
fe055896 | 36 | #include <asm/microcode_amd.h> |
c93dc84c | 37 | #include <asm/perf_event.h> |
fe055896 BP |
38 | #include <asm/microcode.h> |
39 | #include <asm/processor.h> | |
40 | #include <asm/cmdline.h> | |
06b8534c | 41 | #include <asm/setup.h> |
3e135d88 | 42 | |
14cfbe55 | 43 | #define DRIVER_VERSION "2.2" |
3e135d88 | 44 | |
4bae1967 | 45 | static struct microcode_ops *microcode_ops; |
a15a7535 | 46 | static bool dis_ucode_ldr = true; |
6b26e1bf | 47 | |
24c25032 BP |
48 | bool initrd_gone; |
49 | ||
058dc498 BP |
50 | LIST_HEAD(microcode_cache); |
51 | ||
871b72dd DA |
52 | /* |
53 | * Synchronization. | |
54 | * | |
55 | * All non cpu-hotplug-callback call sites use: | |
56 | * | |
57 | * - microcode_mutex to synchronize with each other; | |
58 | * - get/put_online_cpus() to synchronize with | |
59 | * the cpu-hotplug-callback call sites. | |
60 | * | |
61 | * We guarantee that only a single cpu is being | |
62 | * updated at any particular moment of time. | |
63 | */ | |
d45de409 | 64 | static DEFINE_MUTEX(microcode_mutex); |
3e135d88 | 65 | |
4bae1967 | 66 | struct ucode_cpu_info ucode_cpu_info[NR_CPUS]; |
3e135d88 | 67 | |
871b72dd DA |
68 | struct cpu_info_ctx { |
69 | struct cpu_signature *cpu_sig; | |
70 | int err; | |
71 | }; | |
72 | ||
f3ad136d BP |
73 | /* |
74 | * Those patch levels cannot be updated to newer ones and thus should be final. | |
75 | */ | |
76 | static u32 final_levels[] = { | |
77 | 0x01000098, | |
78 | 0x0100009f, | |
79 | 0x010000af, | |
80 | 0, /* T-101 terminator */ | |
81 | }; | |
82 | ||
83 | /* | |
84 | * Check the current patch level on this CPU. | |
85 | * | |
86 | * Returns: | |
87 | * - true: if update should stop | |
88 | * - false: otherwise | |
89 | */ | |
90 | static bool amd_check_current_patch_level(void) | |
91 | { | |
92 | u32 lvl, dummy, i; | |
93 | u32 *levels; | |
94 | ||
95 | native_rdmsr(MSR_AMD64_PATCH_LEVEL, lvl, dummy); | |
96 | ||
97 | if (IS_ENABLED(CONFIG_X86_32)) | |
98 | levels = (u32 *)__pa_nodebug(&final_levels); | |
99 | else | |
100 | levels = final_levels; | |
101 | ||
102 | for (i = 0; levels[i]; i++) { | |
103 | if (lvl == levels[i]) | |
104 | return true; | |
105 | } | |
106 | return false; | |
107 | } | |
108 | ||
fe055896 BP |
109 | static bool __init check_loader_disabled_bsp(void) |
110 | { | |
e8c8165e BP |
111 | static const char *__dis_opt_str = "dis_ucode_ldr"; |
112 | ||
fe055896 BP |
113 | #ifdef CONFIG_X86_32 |
114 | const char *cmdline = (const char *)__pa_nodebug(boot_command_line); | |
e8c8165e | 115 | const char *option = (const char *)__pa_nodebug(__dis_opt_str); |
fe055896 BP |
116 | bool *res = (bool *)__pa_nodebug(&dis_ucode_ldr); |
117 | ||
118 | #else /* CONFIG_X86_64 */ | |
119 | const char *cmdline = boot_command_line; | |
e8c8165e | 120 | const char *option = __dis_opt_str; |
fe055896 BP |
121 | bool *res = &dis_ucode_ldr; |
122 | #endif | |
123 | ||
a15a7535 BP |
124 | /* |
125 | * CPUID(1).ECX[31]: reserved for hypervisor use. This is still not | |
126 | * completely accurate as xen pv guests don't see that CPUID bit set but | |
127 | * that's good enough as they don't land on the BSP path anyway. | |
128 | */ | |
309aac77 | 129 | if (native_cpuid_ecx(1) & BIT(31)) |
a15a7535 BP |
130 | return *res; |
131 | ||
f3ad136d BP |
132 | if (x86_cpuid_vendor() == X86_VENDOR_AMD) { |
133 | if (amd_check_current_patch_level()) | |
134 | return *res; | |
135 | } | |
136 | ||
a15a7535 BP |
137 | if (cmdline_find_option_bool(cmdline, option) <= 0) |
138 | *res = false; | |
fe055896 BP |
139 | |
140 | return *res; | |
141 | } | |
142 | ||
143 | extern struct builtin_fw __start_builtin_fw[]; | |
144 | extern struct builtin_fw __end_builtin_fw[]; | |
145 | ||
146 | bool get_builtin_firmware(struct cpio_data *cd, const char *name) | |
147 | { | |
148 | #ifdef CONFIG_FW_LOADER | |
149 | struct builtin_fw *b_fw; | |
150 | ||
151 | for (b_fw = __start_builtin_fw; b_fw != __end_builtin_fw; b_fw++) { | |
152 | if (!strcmp(name, b_fw->name)) { | |
153 | cd->size = b_fw->size; | |
154 | cd->data = b_fw->data; | |
155 | return true; | |
156 | } | |
157 | } | |
158 | #endif | |
159 | return false; | |
160 | } | |
161 | ||
162 | void __init load_ucode_bsp(void) | |
163 | { | |
7a93a40b | 164 | unsigned int cpuid_1_eax; |
1f161f67 | 165 | bool intel = true; |
fe055896 | 166 | |
1f161f67 | 167 | if (!have_cpuid_p()) |
fe055896 BP |
168 | return; |
169 | ||
309aac77 | 170 | cpuid_1_eax = native_cpuid_eax(1); |
fe055896 | 171 | |
7a93a40b | 172 | switch (x86_cpuid_vendor()) { |
fe055896 | 173 | case X86_VENDOR_INTEL: |
1f161f67 BP |
174 | if (x86_family(cpuid_1_eax) < 6) |
175 | return; | |
fe055896 | 176 | break; |
1f161f67 | 177 | |
fe055896 | 178 | case X86_VENDOR_AMD: |
1f161f67 BP |
179 | if (x86_family(cpuid_1_eax) < 0x10) |
180 | return; | |
181 | intel = false; | |
fe055896 | 182 | break; |
1f161f67 | 183 | |
fe055896 | 184 | default: |
1f161f67 | 185 | return; |
fe055896 | 186 | } |
1f161f67 BP |
187 | |
188 | if (check_loader_disabled_bsp()) | |
189 | return; | |
190 | ||
191 | if (intel) | |
192 | load_ucode_intel_bsp(); | |
193 | else | |
194 | load_ucode_amd_bsp(cpuid_1_eax); | |
fe055896 BP |
195 | } |
196 | ||
197 | static bool check_loader_disabled_ap(void) | |
198 | { | |
199 | #ifdef CONFIG_X86_32 | |
200 | return *((bool *)__pa_nodebug(&dis_ucode_ldr)); | |
201 | #else | |
202 | return dis_ucode_ldr; | |
203 | #endif | |
204 | } | |
205 | ||
206 | void load_ucode_ap(void) | |
207 | { | |
7a93a40b | 208 | unsigned int cpuid_1_eax; |
fe055896 BP |
209 | |
210 | if (check_loader_disabled_ap()) | |
211 | return; | |
212 | ||
309aac77 | 213 | cpuid_1_eax = native_cpuid_eax(1); |
fe055896 | 214 | |
7a93a40b | 215 | switch (x86_cpuid_vendor()) { |
fe055896 | 216 | case X86_VENDOR_INTEL: |
309aac77 | 217 | if (x86_family(cpuid_1_eax) >= 6) |
fe055896 BP |
218 | load_ucode_intel_ap(); |
219 | break; | |
220 | case X86_VENDOR_AMD: | |
309aac77 BP |
221 | if (x86_family(cpuid_1_eax) >= 0x10) |
222 | load_ucode_amd_ap(cpuid_1_eax); | |
fe055896 BP |
223 | break; |
224 | default: | |
225 | break; | |
226 | } | |
227 | } | |
228 | ||
4b703305 | 229 | static int __init save_microcode_in_initrd(void) |
fe055896 BP |
230 | { |
231 | struct cpuinfo_x86 *c = &boot_cpu_data; | |
24c25032 | 232 | int ret = -EINVAL; |
fe055896 BP |
233 | |
234 | switch (c->x86_vendor) { | |
235 | case X86_VENDOR_INTEL: | |
236 | if (c->x86 >= 6) | |
24c25032 | 237 | ret = save_microcode_in_initrd_intel(); |
fe055896 BP |
238 | break; |
239 | case X86_VENDOR_AMD: | |
240 | if (c->x86 >= 0x10) | |
1d080f09 | 241 | ret = save_microcode_in_initrd_amd(cpuid_eax(1)); |
fe055896 BP |
242 | break; |
243 | default: | |
244 | break; | |
245 | } | |
246 | ||
24c25032 BP |
247 | initrd_gone = true; |
248 | ||
249 | return ret; | |
fe055896 BP |
250 | } |
251 | ||
06b8534c BP |
252 | struct cpio_data find_microcode_in_initrd(const char *path, bool use_pa) |
253 | { | |
254 | #ifdef CONFIG_BLK_DEV_INITRD | |
255 | unsigned long start = 0; | |
256 | size_t size; | |
257 | ||
258 | #ifdef CONFIG_X86_32 | |
259 | struct boot_params *params; | |
260 | ||
261 | if (use_pa) | |
262 | params = (struct boot_params *)__pa_nodebug(&boot_params); | |
263 | else | |
264 | params = &boot_params; | |
265 | ||
266 | size = params->hdr.ramdisk_size; | |
267 | ||
268 | /* | |
269 | * Set start only if we have an initrd image. We cannot use initrd_start | |
270 | * because it is not set that early yet. | |
271 | */ | |
272 | if (size) | |
273 | start = params->hdr.ramdisk_image; | |
274 | ||
275 | # else /* CONFIG_X86_64 */ | |
276 | size = (unsigned long)boot_params.ext_ramdisk_size << 32; | |
277 | size |= boot_params.hdr.ramdisk_size; | |
278 | ||
279 | if (size) { | |
280 | start = (unsigned long)boot_params.ext_ramdisk_image << 32; | |
281 | start |= boot_params.hdr.ramdisk_image; | |
282 | ||
283 | start += PAGE_OFFSET; | |
284 | } | |
285 | # endif | |
286 | ||
287 | /* | |
8877ebdd BP |
288 | * Fixup the start address: after reserve_initrd() runs, initrd_start |
289 | * has the virtual address of the beginning of the initrd. It also | |
290 | * possibly relocates the ramdisk. In either case, initrd_start contains | |
291 | * the updated address so use that instead. | |
24c25032 BP |
292 | * |
293 | * initrd_gone is for the hotplug case where we've thrown out initrd | |
294 | * already. | |
06b8534c | 295 | */ |
24c25032 BP |
296 | if (!use_pa) { |
297 | if (initrd_gone) | |
298 | return (struct cpio_data){ NULL, 0, "" }; | |
299 | if (initrd_start) | |
300 | start = initrd_start; | |
a3d98c93 BP |
301 | } else { |
302 | /* | |
303 | * The picture with physical addresses is a bit different: we | |
304 | * need to get the *physical* address to which the ramdisk was | |
305 | * relocated, i.e., relocated_ramdisk (not initrd_start) and | |
306 | * since we're running from physical addresses, we need to access | |
307 | * relocated_ramdisk through its *physical* address too. | |
308 | */ | |
309 | u64 *rr = (u64 *)__pa_nodebug(&relocated_ramdisk); | |
310 | if (*rr) | |
311 | start = *rr; | |
24c25032 | 312 | } |
06b8534c BP |
313 | |
314 | return find_cpio_data(path, (void *)start, size, NULL); | |
315 | #else /* !CONFIG_BLK_DEV_INITRD */ | |
316 | return (struct cpio_data){ NULL, 0, "" }; | |
317 | #endif | |
318 | } | |
319 | ||
fe055896 BP |
320 | void reload_early_microcode(void) |
321 | { | |
322 | int vendor, family; | |
323 | ||
99f925ce BP |
324 | vendor = x86_cpuid_vendor(); |
325 | family = x86_cpuid_family(); | |
fe055896 BP |
326 | |
327 | switch (vendor) { | |
328 | case X86_VENDOR_INTEL: | |
329 | if (family >= 6) | |
330 | reload_ucode_intel(); | |
331 | break; | |
332 | case X86_VENDOR_AMD: | |
333 | if (family >= 0x10) | |
334 | reload_ucode_amd(); | |
335 | break; | |
336 | default: | |
337 | break; | |
338 | } | |
339 | } | |
340 | ||
871b72dd DA |
341 | static void collect_cpu_info_local(void *arg) |
342 | { | |
343 | struct cpu_info_ctx *ctx = arg; | |
344 | ||
345 | ctx->err = microcode_ops->collect_cpu_info(smp_processor_id(), | |
346 | ctx->cpu_sig); | |
347 | } | |
348 | ||
349 | static int collect_cpu_info_on_target(int cpu, struct cpu_signature *cpu_sig) | |
350 | { | |
351 | struct cpu_info_ctx ctx = { .cpu_sig = cpu_sig, .err = 0 }; | |
352 | int ret; | |
353 | ||
354 | ret = smp_call_function_single(cpu, collect_cpu_info_local, &ctx, 1); | |
355 | if (!ret) | |
356 | ret = ctx.err; | |
357 | ||
358 | return ret; | |
359 | } | |
360 | ||
361 | static int collect_cpu_info(int cpu) | |
362 | { | |
363 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; | |
364 | int ret; | |
365 | ||
366 | memset(uci, 0, sizeof(*uci)); | |
367 | ||
368 | ret = collect_cpu_info_on_target(cpu, &uci->cpu_sig); | |
369 | if (!ret) | |
370 | uci->valid = 1; | |
371 | ||
372 | return ret; | |
373 | } | |
374 | ||
871b72dd DA |
375 | static void apply_microcode_local(void *arg) |
376 | { | |
854857f5 | 377 | enum ucode_state *err = arg; |
871b72dd | 378 | |
854857f5 | 379 | *err = microcode_ops->apply_microcode(smp_processor_id()); |
871b72dd DA |
380 | } |
381 | ||
382 | static int apply_microcode_on_target(int cpu) | |
383 | { | |
854857f5 | 384 | enum ucode_state err; |
871b72dd DA |
385 | int ret; |
386 | ||
854857f5 BP |
387 | ret = smp_call_function_single(cpu, apply_microcode_local, &err, 1); |
388 | if (!ret) { | |
389 | if (err == UCODE_ERROR) | |
390 | ret = 1; | |
391 | } | |
871b72dd DA |
392 | return ret; |
393 | } | |
394 | ||
3e135d88 | 395 | #ifdef CONFIG_MICROCODE_OLD_INTERFACE |
a0a29b62 | 396 | static int do_microcode_update(const void __user *buf, size_t size) |
3e135d88 | 397 | { |
3e135d88 | 398 | int error = 0; |
3e135d88 | 399 | int cpu; |
6f66cbc6 | 400 | |
a0a29b62 DA |
401 | for_each_online_cpu(cpu) { |
402 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; | |
871b72dd | 403 | enum ucode_state ustate; |
a0a29b62 DA |
404 | |
405 | if (!uci->valid) | |
406 | continue; | |
6f66cbc6 | 407 | |
871b72dd DA |
408 | ustate = microcode_ops->request_microcode_user(cpu, buf, size); |
409 | if (ustate == UCODE_ERROR) { | |
410 | error = -1; | |
411 | break; | |
24613a04 | 412 | } else if (ustate == UCODE_NEW) { |
871b72dd | 413 | apply_microcode_on_target(cpu); |
24613a04 | 414 | } |
3e135d88 | 415 | } |
871b72dd | 416 | |
3e135d88 PO |
417 | return error; |
418 | } | |
419 | ||
3f10940e | 420 | static int microcode_open(struct inode *inode, struct file *file) |
3e135d88 | 421 | { |
c5bf68fe | 422 | return capable(CAP_SYS_RAWIO) ? stream_open(inode, file) : -EPERM; |
3e135d88 PO |
423 | } |
424 | ||
d33dcb9e PO |
425 | static ssize_t microcode_write(struct file *file, const char __user *buf, |
426 | size_t len, loff_t *ppos) | |
3e135d88 | 427 | { |
871b72dd | 428 | ssize_t ret = -EINVAL; |
ca79b0c2 | 429 | unsigned long nr_pages = totalram_pages(); |
3e135d88 | 430 | |
3d6357de AK |
431 | if ((len >> PAGE_SHIFT) > nr_pages) { |
432 | pr_err("too much data (max %ld pages)\n", nr_pages); | |
871b72dd | 433 | return ret; |
3e135d88 PO |
434 | } |
435 | ||
436 | get_online_cpus(); | |
437 | mutex_lock(µcode_mutex); | |
438 | ||
871b72dd | 439 | if (do_microcode_update(buf, len) == 0) |
3e135d88 PO |
440 | ret = (ssize_t)len; |
441 | ||
e3e45c01 SE |
442 | if (ret > 0) |
443 | perf_check_microcode(); | |
444 | ||
3e135d88 PO |
445 | mutex_unlock(µcode_mutex); |
446 | put_online_cpus(); | |
447 | ||
448 | return ret; | |
449 | } | |
450 | ||
451 | static const struct file_operations microcode_fops = { | |
871b72dd DA |
452 | .owner = THIS_MODULE, |
453 | .write = microcode_write, | |
454 | .open = microcode_open, | |
6038f373 | 455 | .llseek = no_llseek, |
3e135d88 PO |
456 | }; |
457 | ||
458 | static struct miscdevice microcode_dev = { | |
871b72dd DA |
459 | .minor = MICROCODE_MINOR, |
460 | .name = "microcode", | |
e454cea2 | 461 | .nodename = "cpu/microcode", |
871b72dd | 462 | .fops = µcode_fops, |
3e135d88 PO |
463 | }; |
464 | ||
d33dcb9e | 465 | static int __init microcode_dev_init(void) |
3e135d88 PO |
466 | { |
467 | int error; | |
468 | ||
469 | error = misc_register(µcode_dev); | |
470 | if (error) { | |
f58e1f53 | 471 | pr_err("can't misc_register on minor=%d\n", MICROCODE_MINOR); |
3e135d88 PO |
472 | return error; |
473 | } | |
474 | ||
475 | return 0; | |
476 | } | |
477 | ||
bd399063 | 478 | static void __exit microcode_dev_exit(void) |
3e135d88 PO |
479 | { |
480 | misc_deregister(µcode_dev); | |
481 | } | |
3e135d88 | 482 | #else |
4bae1967 IM |
483 | #define microcode_dev_init() 0 |
484 | #define microcode_dev_exit() do { } while (0) | |
3e135d88 PO |
485 | #endif |
486 | ||
487 | /* fake device for request_firmware */ | |
4bae1967 | 488 | static struct platform_device *microcode_pdev; |
3e135d88 | 489 | |
a5321aec AR |
490 | /* |
491 | * Late loading dance. Why the heavy-handed stomp_machine effort? | |
492 | * | |
493 | * - HT siblings must be idle and not execute other code while the other sibling | |
494 | * is loading microcode in order to avoid any negative interactions caused by | |
495 | * the loading. | |
496 | * | |
497 | * - In addition, microcode update on the cores must be serialized until this | |
498 | * requirement can be relaxed in the future. Right now, this is conservative | |
499 | * and good. | |
500 | */ | |
501 | #define SPINUNIT 100 /* 100 nsec */ | |
502 | ||
30ec26da AR |
503 | static int check_online_cpus(void) |
504 | { | |
07d981ad | 505 | unsigned int cpu; |
30ec26da | 506 | |
07d981ad JP |
507 | /* |
508 | * Make sure all CPUs are online. It's fine for SMT to be disabled if | |
509 | * all the primary threads are still online. | |
510 | */ | |
511 | for_each_present_cpu(cpu) { | |
512 | if (topology_is_primary_thread(cpu) && !cpu_online(cpu)) { | |
513 | pr_err("Not all CPUs online, aborting microcode update.\n"); | |
514 | return -EINVAL; | |
515 | } | |
516 | } | |
30ec26da | 517 | |
07d981ad | 518 | return 0; |
30ec26da AR |
519 | } |
520 | ||
bb8c13d6 BP |
521 | static atomic_t late_cpus_in; |
522 | static atomic_t late_cpus_out; | |
523 | ||
524 | static int __wait_for_cpus(atomic_t *t, long long timeout) | |
525 | { | |
526 | int all_cpus = num_online_cpus(); | |
527 | ||
528 | atomic_inc(t); | |
529 | ||
530 | while (atomic_read(t) < all_cpus) { | |
531 | if (timeout < SPINUNIT) { | |
532 | pr_err("Timeout while waiting for CPUs rendezvous, remaining: %d\n", | |
533 | all_cpus - atomic_read(t)); | |
534 | return 1; | |
535 | } | |
536 | ||
537 | ndelay(SPINUNIT); | |
538 | timeout -= SPINUNIT; | |
539 | ||
540 | touch_nmi_watchdog(); | |
541 | } | |
542 | return 0; | |
543 | } | |
a5321aec AR |
544 | |
545 | /* | |
546 | * Returns: | |
547 | * < 0 - on error | |
9adbf3c6 | 548 | * 0 - success (no update done or microcode was updated) |
a5321aec AR |
549 | */ |
550 | static int __reload_late(void *info) | |
af5c820a | 551 | { |
a5321aec AR |
552 | int cpu = smp_processor_id(); |
553 | enum ucode_state err; | |
554 | int ret = 0; | |
555 | ||
a5321aec AR |
556 | /* |
557 | * Wait for all CPUs to arrive. A load will not be attempted unless all | |
558 | * CPUs show up. | |
559 | * */ | |
bb8c13d6 BP |
560 | if (__wait_for_cpus(&late_cpus_in, NSEC_PER_SEC)) |
561 | return -1; | |
a5321aec | 562 | |
93946a33 AR |
563 | /* |
564 | * On an SMT system, it suffices to load the microcode on one sibling of | |
565 | * the core because the microcode engine is shared between the threads. | |
566 | * Synchronization still needs to take place so that no concurrent | |
567 | * loading attempts happen on multiple threads of an SMT core. See | |
568 | * below. | |
569 | */ | |
570 | if (cpumask_first(topology_sibling_cpumask(cpu)) == cpu) | |
571 | apply_microcode_local(&err); | |
572 | else | |
573 | goto wait_for_siblings; | |
a5321aec | 574 | |
9adbf3c6 MC |
575 | if (err >= UCODE_NFOUND) { |
576 | if (err == UCODE_ERROR) | |
577 | pr_warn("Error reloading microcode on CPU %d\n", cpu); | |
578 | ||
09e182d1 | 579 | ret = -1; |
a5321aec | 580 | } |
af5c820a | 581 | |
93946a33 AR |
582 | wait_for_siblings: |
583 | if (__wait_for_cpus(&late_cpus_out, NSEC_PER_SEC)) | |
584 | panic("Timeout during microcode update!\n"); | |
585 | ||
bb8c13d6 | 586 | /* |
93946a33 AR |
587 | * At least one thread has completed update on each core. |
588 | * For others, simply call the update to make sure the | |
589 | * per-cpu cpuinfo can be updated with right microcode | |
590 | * revision. | |
bb8c13d6 | 591 | */ |
93946a33 AR |
592 | if (cpumask_first(topology_sibling_cpumask(cpu)) != cpu) |
593 | apply_microcode_local(&err); | |
a5321aec AR |
594 | |
595 | return ret; | |
596 | } | |
597 | ||
598 | /* | |
599 | * Reload microcode late on all CPUs. Wait for a sec until they | |
600 | * all gather together. | |
601 | */ | |
602 | static int microcode_reload_late(void) | |
603 | { | |
604 | int ret; | |
605 | ||
bb8c13d6 BP |
606 | atomic_set(&late_cpus_in, 0); |
607 | atomic_set(&late_cpus_out, 0); | |
a5321aec AR |
608 | |
609 | ret = stop_machine_cpuslocked(__reload_late, NULL, cpu_online_mask); | |
9adbf3c6 | 610 | if (ret == 0) |
a5321aec AR |
611 | microcode_check(); |
612 | ||
9bd68125 BP |
613 | pr_info("Reload completed, microcode revision: 0x%x\n", boot_cpu_data.microcode); |
614 | ||
a5321aec | 615 | return ret; |
af5c820a RR |
616 | } |
617 | ||
8a25a2fd KS |
618 | static ssize_t reload_store(struct device *dev, |
619 | struct device_attribute *attr, | |
871b72dd | 620 | const char *buf, size_t size) |
3e135d88 | 621 | { |
3f1f576a | 622 | enum ucode_state tmp_ret = UCODE_OK; |
a5321aec | 623 | int bsp = boot_cpu_data.cpu_index; |
871b72dd | 624 | unsigned long val; |
3f1f576a | 625 | ssize_t ret = 0; |
c9fc3f77 | 626 | |
e826abd5 SK |
627 | ret = kstrtoul(buf, 0, &val); |
628 | if (ret) | |
629 | return ret; | |
871b72dd | 630 | |
c9fc3f77 BP |
631 | if (val != 1) |
632 | return size; | |
633 | ||
cfb52a5a | 634 | tmp_ret = microcode_ops->request_microcode_fw(bsp, µcode_pdev->dev, true); |
2613f36e | 635 | if (tmp_ret != UCODE_NEW) |
cfb52a5a BP |
636 | return size; |
637 | ||
c9fc3f77 | 638 | get_online_cpus(); |
30ec26da AR |
639 | |
640 | ret = check_online_cpus(); | |
641 | if (ret) | |
642 | goto put; | |
643 | ||
c93dc84c | 644 | mutex_lock(µcode_mutex); |
a5321aec | 645 | ret = microcode_reload_late(); |
c93dc84c | 646 | mutex_unlock(µcode_mutex); |
30ec26da AR |
647 | |
648 | put: | |
c9fc3f77 | 649 | put_online_cpus(); |
871b72dd | 650 | |
9adbf3c6 | 651 | if (ret == 0) |
871b72dd DA |
652 | ret = size; |
653 | ||
654 | return ret; | |
3e135d88 PO |
655 | } |
656 | ||
8a25a2fd KS |
657 | static ssize_t version_show(struct device *dev, |
658 | struct device_attribute *attr, char *buf) | |
3e135d88 PO |
659 | { |
660 | struct ucode_cpu_info *uci = ucode_cpu_info + dev->id; | |
661 | ||
d45de409 | 662 | return sprintf(buf, "0x%x\n", uci->cpu_sig.rev); |
3e135d88 PO |
663 | } |
664 | ||
8a25a2fd KS |
665 | static ssize_t pf_show(struct device *dev, |
666 | struct device_attribute *attr, char *buf) | |
3e135d88 PO |
667 | { |
668 | struct ucode_cpu_info *uci = ucode_cpu_info + dev->id; | |
669 | ||
d45de409 | 670 | return sprintf(buf, "0x%x\n", uci->cpu_sig.pf); |
3e135d88 PO |
671 | } |
672 | ||
6cbaefb4 | 673 | static DEVICE_ATTR_WO(reload); |
f4661d29 JT |
674 | static DEVICE_ATTR(version, 0444, version_show, NULL); |
675 | static DEVICE_ATTR(processor_flags, 0444, pf_show, NULL); | |
3e135d88 PO |
676 | |
677 | static struct attribute *mc_default_attrs[] = { | |
8a25a2fd KS |
678 | &dev_attr_version.attr, |
679 | &dev_attr_processor_flags.attr, | |
3e135d88 PO |
680 | NULL |
681 | }; | |
682 | ||
45bd07ad | 683 | static const struct attribute_group mc_attr_group = { |
871b72dd DA |
684 | .attrs = mc_default_attrs, |
685 | .name = "microcode", | |
3e135d88 PO |
686 | }; |
687 | ||
871b72dd | 688 | static void microcode_fini_cpu(int cpu) |
d45de409 | 689 | { |
06b8534c BP |
690 | if (microcode_ops->microcode_fini_cpu) |
691 | microcode_ops->microcode_fini_cpu(cpu); | |
280a9ca5 DA |
692 | } |
693 | ||
871b72dd | 694 | static enum ucode_state microcode_resume_cpu(int cpu) |
d45de409 | 695 | { |
bb9d3e47 BP |
696 | if (apply_microcode_on_target(cpu)) |
697 | return UCODE_ERROR; | |
871b72dd | 698 | |
6b14b818 BP |
699 | pr_debug("CPU%d updated upon resume\n", cpu); |
700 | ||
871b72dd | 701 | return UCODE_OK; |
d45de409 DA |
702 | } |
703 | ||
48e30685 | 704 | static enum ucode_state microcode_init_cpu(int cpu, bool refresh_fw) |
d45de409 | 705 | { |
871b72dd | 706 | enum ucode_state ustate; |
9cd4d78e FY |
707 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; |
708 | ||
43858f57 | 709 | if (uci->valid) |
9cd4d78e | 710 | return UCODE_OK; |
d45de409 | 711 | |
871b72dd DA |
712 | if (collect_cpu_info(cpu)) |
713 | return UCODE_ERROR; | |
d45de409 | 714 | |
871b72dd DA |
715 | /* --dimm. Trigger a delayed update? */ |
716 | if (system_state != SYSTEM_RUNNING) | |
717 | return UCODE_NFOUND; | |
d45de409 | 718 | |
2613f36e BP |
719 | ustate = microcode_ops->request_microcode_fw(cpu, µcode_pdev->dev, refresh_fw); |
720 | if (ustate == UCODE_NEW) { | |
f58e1f53 | 721 | pr_debug("CPU%d updated upon init\n", cpu); |
871b72dd | 722 | apply_microcode_on_target(cpu); |
d45de409 DA |
723 | } |
724 | ||
871b72dd | 725 | return ustate; |
d45de409 DA |
726 | } |
727 | ||
871b72dd | 728 | static enum ucode_state microcode_update_cpu(int cpu) |
d45de409 | 729 | { |
871b72dd | 730 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; |
d45de409 | 731 | |
7f709d0c BP |
732 | /* Refresh CPU microcode revision after resume. */ |
733 | collect_cpu_info(cpu); | |
734 | ||
2f99f5c8 | 735 | if (uci->valid) |
bb9d3e47 | 736 | return microcode_resume_cpu(cpu); |
d45de409 | 737 | |
48e30685 | 738 | return microcode_init_cpu(cpu, false); |
d45de409 DA |
739 | } |
740 | ||
8a25a2fd | 741 | static int mc_device_add(struct device *dev, struct subsys_interface *sif) |
3e135d88 | 742 | { |
8a25a2fd | 743 | int err, cpu = dev->id; |
3e135d88 PO |
744 | |
745 | if (!cpu_online(cpu)) | |
746 | return 0; | |
747 | ||
f58e1f53 | 748 | pr_debug("CPU%d added\n", cpu); |
3e135d88 | 749 | |
8a25a2fd | 750 | err = sysfs_create_group(&dev->kobj, &mc_attr_group); |
3e135d88 PO |
751 | if (err) |
752 | return err; | |
753 | ||
48e30685 | 754 | if (microcode_init_cpu(cpu, true) == UCODE_ERROR) |
6c53cbfc | 755 | return -EINVAL; |
af5c820a RR |
756 | |
757 | return err; | |
3e135d88 PO |
758 | } |
759 | ||
71db87ba | 760 | static void mc_device_remove(struct device *dev, struct subsys_interface *sif) |
3e135d88 | 761 | { |
8a25a2fd | 762 | int cpu = dev->id; |
3e135d88 PO |
763 | |
764 | if (!cpu_online(cpu)) | |
71db87ba | 765 | return; |
3e135d88 | 766 | |
f58e1f53 | 767 | pr_debug("CPU%d removed\n", cpu); |
d45de409 | 768 | microcode_fini_cpu(cpu); |
8a25a2fd | 769 | sysfs_remove_group(&dev->kobj, &mc_attr_group); |
3e135d88 PO |
770 | } |
771 | ||
8a25a2fd KS |
772 | static struct subsys_interface mc_cpu_interface = { |
773 | .name = "microcode", | |
774 | .subsys = &cpu_subsys, | |
775 | .add_dev = mc_device_add, | |
776 | .remove_dev = mc_device_remove, | |
f3c6ea1b RW |
777 | }; |
778 | ||
779 | /** | |
780 | * mc_bp_resume - Update boot CPU microcode during resume. | |
781 | */ | |
782 | static void mc_bp_resume(void) | |
3e135d88 | 783 | { |
f3c6ea1b | 784 | int cpu = smp_processor_id(); |
871b72dd | 785 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; |
3e135d88 | 786 | |
871b72dd DA |
787 | if (uci->valid && uci->mc) |
788 | microcode_ops->apply_microcode(cpu); | |
fb86b973 | 789 | else if (!uci->mc) |
fbae4ba8 | 790 | reload_early_microcode(); |
3e135d88 PO |
791 | } |
792 | ||
f3c6ea1b RW |
793 | static struct syscore_ops mc_syscore_ops = { |
794 | .resume = mc_bp_resume, | |
3e135d88 PO |
795 | }; |
796 | ||
5423f5ce | 797 | static int mc_cpu_starting(unsigned int cpu) |
3e135d88 | 798 | { |
29bd7fbc SAS |
799 | microcode_update_cpu(cpu); |
800 | pr_debug("CPU%d added\n", cpu); | |
5423f5ce TG |
801 | return 0; |
802 | } | |
803 | ||
804 | static int mc_cpu_online(unsigned int cpu) | |
805 | { | |
806 | struct device *dev = get_cpu_device(cpu); | |
09c3f0d8 | 807 | |
29bd7fbc SAS |
808 | if (sysfs_create_group(&dev->kobj, &mc_attr_group)) |
809 | pr_err("Failed to create group for CPU%d\n", cpu); | |
810 | return 0; | |
811 | } | |
09c3f0d8 | 812 | |
29bd7fbc SAS |
813 | static int mc_cpu_down_prep(unsigned int cpu) |
814 | { | |
815 | struct device *dev; | |
70989449 | 816 | |
29bd7fbc SAS |
817 | dev = get_cpu_device(cpu); |
818 | /* Suspend is in progress, only remove the interface */ | |
819 | sysfs_remove_group(&dev->kobj, &mc_attr_group); | |
820 | pr_debug("CPU%d removed\n", cpu); | |
06b8534c | 821 | |
29bd7fbc | 822 | return 0; |
3e135d88 PO |
823 | } |
824 | ||
3d8986bc BP |
825 | static struct attribute *cpu_root_microcode_attrs[] = { |
826 | &dev_attr_reload.attr, | |
827 | NULL | |
828 | }; | |
829 | ||
45bd07ad | 830 | static const struct attribute_group cpu_root_microcode_group = { |
3d8986bc BP |
831 | .name = "microcode", |
832 | .attrs = cpu_root_microcode_attrs, | |
833 | }; | |
834 | ||
9a2bc335 | 835 | int __init microcode_init(void) |
3e135d88 | 836 | { |
9a2bc335 | 837 | struct cpuinfo_x86 *c = &boot_cpu_data; |
3e135d88 PO |
838 | int error; |
839 | ||
84aba677 | 840 | if (dis_ucode_ldr) |
da63865a | 841 | return -EINVAL; |
65cef131 | 842 | |
18dbc916 DA |
843 | if (c->x86_vendor == X86_VENDOR_INTEL) |
844 | microcode_ops = init_intel_microcode(); | |
82b07865 | 845 | else if (c->x86_vendor == X86_VENDOR_AMD) |
18dbc916 | 846 | microcode_ops = init_amd_microcode(); |
283c1f25 | 847 | else |
f58e1f53 | 848 | pr_err("no support for this CPU vendor\n"); |
283c1f25 AH |
849 | |
850 | if (!microcode_ops) | |
18dbc916 | 851 | return -ENODEV; |
3e135d88 | 852 | |
3e135d88 PO |
853 | microcode_pdev = platform_device_register_simple("microcode", -1, |
854 | NULL, 0); | |
bd399063 | 855 | if (IS_ERR(microcode_pdev)) |
3e135d88 | 856 | return PTR_ERR(microcode_pdev); |
3e135d88 PO |
857 | |
858 | get_online_cpus(); | |
871b72dd DA |
859 | mutex_lock(µcode_mutex); |
860 | ||
8a25a2fd | 861 | error = subsys_interface_register(&mc_cpu_interface); |
c93dc84c PZ |
862 | if (!error) |
863 | perf_check_microcode(); | |
871b72dd | 864 | mutex_unlock(µcode_mutex); |
3e135d88 | 865 | put_online_cpus(); |
871b72dd | 866 | |
bd399063 SB |
867 | if (error) |
868 | goto out_pdev; | |
3e135d88 | 869 | |
3d8986bc BP |
870 | error = sysfs_create_group(&cpu_subsys.dev_root->kobj, |
871 | &cpu_root_microcode_group); | |
872 | ||
873 | if (error) { | |
874 | pr_err("Error creating microcode group!\n"); | |
875 | goto out_driver; | |
876 | } | |
877 | ||
871b72dd DA |
878 | error = microcode_dev_init(); |
879 | if (error) | |
3d8986bc | 880 | goto out_ucode_group; |
871b72dd | 881 | |
f3c6ea1b | 882 | register_syscore_ops(&mc_syscore_ops); |
5423f5ce TG |
883 | cpuhp_setup_state_nocalls(CPUHP_AP_MICROCODE_LOADER, "x86/microcode:starting", |
884 | mc_cpu_starting, NULL); | |
885 | cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "x86/microcode:online", | |
29bd7fbc | 886 | mc_cpu_online, mc_cpu_down_prep); |
8d86f390 | 887 | |
14cfbe55 | 888 | pr_info("Microcode Update Driver: v%s.", DRIVER_VERSION); |
8d86f390 | 889 | |
3e135d88 | 890 | return 0; |
bd399063 | 891 | |
3d8986bc BP |
892 | out_ucode_group: |
893 | sysfs_remove_group(&cpu_subsys.dev_root->kobj, | |
894 | &cpu_root_microcode_group); | |
895 | ||
896 | out_driver: | |
bd399063 SB |
897 | get_online_cpus(); |
898 | mutex_lock(µcode_mutex); | |
899 | ||
ff4b8a57 | 900 | subsys_interface_unregister(&mc_cpu_interface); |
bd399063 SB |
901 | |
902 | mutex_unlock(µcode_mutex); | |
903 | put_online_cpus(); | |
904 | ||
3d8986bc | 905 | out_pdev: |
bd399063 SB |
906 | platform_device_unregister(microcode_pdev); |
907 | return error; | |
908 | ||
3e135d88 | 909 | } |
4b703305 | 910 | fs_initcall(save_microcode_in_initrd); |
2d5be37d | 911 | late_initcall(microcode_init); |