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Commit | Line | Data |
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3e135d88 | 1 | /* |
6b44e72a | 2 | * CPU Microcode Update Driver for Linux |
3e135d88 | 3 | * |
cea58224 | 4 | * Copyright (C) 2000-2006 Tigran Aivazian <aivazian.tigran@gmail.com> |
6b44e72a | 5 | * 2006 Shaohua Li <shaohua.li@intel.com> |
14cfbe55 | 6 | * 2013-2016 Borislav Petkov <bp@alien8.de> |
3e135d88 | 7 | * |
fe055896 BP |
8 | * X86 CPU microcode early update for Linux: |
9 | * | |
10 | * Copyright (C) 2012 Fenghua Yu <fenghua.yu@intel.com> | |
11 | * H Peter Anvin" <hpa@zytor.com> | |
12 | * (C) 2015 Borislav Petkov <bp@alien8.de> | |
13 | * | |
6b44e72a | 14 | * This driver allows to upgrade microcode on x86 processors. |
3e135d88 | 15 | * |
6b44e72a BP |
16 | * This program is free software; you can redistribute it and/or |
17 | * modify it under the terms of the GNU General Public License | |
18 | * as published by the Free Software Foundation; either version | |
19 | * 2 of the License, or (at your option) any later version. | |
3e135d88 | 20 | */ |
f58e1f53 | 21 | |
6b26e1bf | 22 | #define pr_fmt(fmt) "microcode: " fmt |
f58e1f53 | 23 | |
4bae1967 | 24 | #include <linux/platform_device.h> |
fe055896 | 25 | #include <linux/syscore_ops.h> |
4bae1967 | 26 | #include <linux/miscdevice.h> |
871b72dd | 27 | #include <linux/capability.h> |
fe055896 | 28 | #include <linux/firmware.h> |
4bae1967 | 29 | #include <linux/kernel.h> |
3e135d88 PO |
30 | #include <linux/mutex.h> |
31 | #include <linux/cpu.h> | |
4bae1967 IM |
32 | #include <linux/fs.h> |
33 | #include <linux/mm.h> | |
3e135d88 | 34 | |
fe055896 | 35 | #include <asm/microcode_intel.h> |
78ff123b | 36 | #include <asm/cpu_device_id.h> |
fe055896 | 37 | #include <asm/microcode_amd.h> |
c93dc84c | 38 | #include <asm/perf_event.h> |
fe055896 BP |
39 | #include <asm/microcode.h> |
40 | #include <asm/processor.h> | |
41 | #include <asm/cmdline.h> | |
06b8534c | 42 | #include <asm/setup.h> |
3e135d88 | 43 | |
14cfbe55 | 44 | #define DRIVER_VERSION "2.2" |
3e135d88 | 45 | |
4bae1967 | 46 | static struct microcode_ops *microcode_ops; |
a15a7535 | 47 | static bool dis_ucode_ldr = true; |
6b26e1bf | 48 | |
24c25032 BP |
49 | bool initrd_gone; |
50 | ||
058dc498 BP |
51 | LIST_HEAD(microcode_cache); |
52 | ||
871b72dd DA |
53 | /* |
54 | * Synchronization. | |
55 | * | |
56 | * All non cpu-hotplug-callback call sites use: | |
57 | * | |
58 | * - microcode_mutex to synchronize with each other; | |
59 | * - get/put_online_cpus() to synchronize with | |
60 | * the cpu-hotplug-callback call sites. | |
61 | * | |
62 | * We guarantee that only a single cpu is being | |
63 | * updated at any particular moment of time. | |
64 | */ | |
d45de409 | 65 | static DEFINE_MUTEX(microcode_mutex); |
3e135d88 | 66 | |
4bae1967 | 67 | struct ucode_cpu_info ucode_cpu_info[NR_CPUS]; |
3e135d88 | 68 | |
871b72dd DA |
69 | struct cpu_info_ctx { |
70 | struct cpu_signature *cpu_sig; | |
71 | int err; | |
72 | }; | |
73 | ||
f3ad136d BP |
74 | /* |
75 | * Those patch levels cannot be updated to newer ones and thus should be final. | |
76 | */ | |
77 | static u32 final_levels[] = { | |
78 | 0x01000098, | |
79 | 0x0100009f, | |
80 | 0x010000af, | |
81 | 0, /* T-101 terminator */ | |
82 | }; | |
83 | ||
84 | /* | |
85 | * Check the current patch level on this CPU. | |
86 | * | |
87 | * Returns: | |
88 | * - true: if update should stop | |
89 | * - false: otherwise | |
90 | */ | |
91 | static bool amd_check_current_patch_level(void) | |
92 | { | |
93 | u32 lvl, dummy, i; | |
94 | u32 *levels; | |
95 | ||
96 | native_rdmsr(MSR_AMD64_PATCH_LEVEL, lvl, dummy); | |
97 | ||
98 | if (IS_ENABLED(CONFIG_X86_32)) | |
99 | levels = (u32 *)__pa_nodebug(&final_levels); | |
100 | else | |
101 | levels = final_levels; | |
102 | ||
103 | for (i = 0; levels[i]; i++) { | |
104 | if (lvl == levels[i]) | |
105 | return true; | |
106 | } | |
107 | return false; | |
108 | } | |
109 | ||
fe055896 BP |
110 | static bool __init check_loader_disabled_bsp(void) |
111 | { | |
e8c8165e BP |
112 | static const char *__dis_opt_str = "dis_ucode_ldr"; |
113 | ||
fe055896 BP |
114 | #ifdef CONFIG_X86_32 |
115 | const char *cmdline = (const char *)__pa_nodebug(boot_command_line); | |
e8c8165e | 116 | const char *option = (const char *)__pa_nodebug(__dis_opt_str); |
fe055896 BP |
117 | bool *res = (bool *)__pa_nodebug(&dis_ucode_ldr); |
118 | ||
119 | #else /* CONFIG_X86_64 */ | |
120 | const char *cmdline = boot_command_line; | |
e8c8165e | 121 | const char *option = __dis_opt_str; |
fe055896 BP |
122 | bool *res = &dis_ucode_ldr; |
123 | #endif | |
124 | ||
a15a7535 BP |
125 | if (!have_cpuid_p()) |
126 | return *res; | |
127 | ||
a15a7535 BP |
128 | /* |
129 | * CPUID(1).ECX[31]: reserved for hypervisor use. This is still not | |
130 | * completely accurate as xen pv guests don't see that CPUID bit set but | |
131 | * that's good enough as they don't land on the BSP path anyway. | |
132 | */ | |
309aac77 | 133 | if (native_cpuid_ecx(1) & BIT(31)) |
a15a7535 BP |
134 | return *res; |
135 | ||
f3ad136d BP |
136 | if (x86_cpuid_vendor() == X86_VENDOR_AMD) { |
137 | if (amd_check_current_patch_level()) | |
138 | return *res; | |
139 | } | |
140 | ||
a15a7535 BP |
141 | if (cmdline_find_option_bool(cmdline, option) <= 0) |
142 | *res = false; | |
fe055896 BP |
143 | |
144 | return *res; | |
145 | } | |
146 | ||
147 | extern struct builtin_fw __start_builtin_fw[]; | |
148 | extern struct builtin_fw __end_builtin_fw[]; | |
149 | ||
150 | bool get_builtin_firmware(struct cpio_data *cd, const char *name) | |
151 | { | |
152 | #ifdef CONFIG_FW_LOADER | |
153 | struct builtin_fw *b_fw; | |
154 | ||
155 | for (b_fw = __start_builtin_fw; b_fw != __end_builtin_fw; b_fw++) { | |
156 | if (!strcmp(name, b_fw->name)) { | |
157 | cd->size = b_fw->size; | |
158 | cd->data = b_fw->data; | |
159 | return true; | |
160 | } | |
161 | } | |
162 | #endif | |
163 | return false; | |
164 | } | |
165 | ||
166 | void __init load_ucode_bsp(void) | |
167 | { | |
7a93a40b | 168 | unsigned int cpuid_1_eax; |
fe055896 BP |
169 | |
170 | if (check_loader_disabled_bsp()) | |
171 | return; | |
172 | ||
309aac77 | 173 | cpuid_1_eax = native_cpuid_eax(1); |
fe055896 | 174 | |
7a93a40b | 175 | switch (x86_cpuid_vendor()) { |
fe055896 | 176 | case X86_VENDOR_INTEL: |
309aac77 | 177 | if (x86_family(cpuid_1_eax) >= 6) |
fe055896 BP |
178 | load_ucode_intel_bsp(); |
179 | break; | |
180 | case X86_VENDOR_AMD: | |
309aac77 BP |
181 | if (x86_family(cpuid_1_eax) >= 0x10) |
182 | load_ucode_amd_bsp(cpuid_1_eax); | |
fe055896 BP |
183 | break; |
184 | default: | |
185 | break; | |
186 | } | |
187 | } | |
188 | ||
189 | static bool check_loader_disabled_ap(void) | |
190 | { | |
191 | #ifdef CONFIG_X86_32 | |
192 | return *((bool *)__pa_nodebug(&dis_ucode_ldr)); | |
193 | #else | |
194 | return dis_ucode_ldr; | |
195 | #endif | |
196 | } | |
197 | ||
198 | void load_ucode_ap(void) | |
199 | { | |
7a93a40b | 200 | unsigned int cpuid_1_eax; |
fe055896 BP |
201 | |
202 | if (check_loader_disabled_ap()) | |
203 | return; | |
204 | ||
309aac77 | 205 | cpuid_1_eax = native_cpuid_eax(1); |
fe055896 | 206 | |
7a93a40b | 207 | switch (x86_cpuid_vendor()) { |
fe055896 | 208 | case X86_VENDOR_INTEL: |
309aac77 | 209 | if (x86_family(cpuid_1_eax) >= 6) |
fe055896 BP |
210 | load_ucode_intel_ap(); |
211 | break; | |
212 | case X86_VENDOR_AMD: | |
309aac77 BP |
213 | if (x86_family(cpuid_1_eax) >= 0x10) |
214 | load_ucode_amd_ap(cpuid_1_eax); | |
fe055896 BP |
215 | break; |
216 | default: | |
217 | break; | |
218 | } | |
219 | } | |
220 | ||
4b703305 | 221 | static int __init save_microcode_in_initrd(void) |
fe055896 BP |
222 | { |
223 | struct cpuinfo_x86 *c = &boot_cpu_data; | |
24c25032 | 224 | int ret = -EINVAL; |
fe055896 BP |
225 | |
226 | switch (c->x86_vendor) { | |
227 | case X86_VENDOR_INTEL: | |
228 | if (c->x86 >= 6) | |
24c25032 | 229 | ret = save_microcode_in_initrd_intel(); |
fe055896 BP |
230 | break; |
231 | case X86_VENDOR_AMD: | |
232 | if (c->x86 >= 0x10) | |
309aac77 | 233 | return save_microcode_in_initrd_amd(cpuid_eax(1)); |
fe055896 BP |
234 | break; |
235 | default: | |
236 | break; | |
237 | } | |
238 | ||
24c25032 BP |
239 | initrd_gone = true; |
240 | ||
241 | return ret; | |
fe055896 BP |
242 | } |
243 | ||
06b8534c BP |
244 | struct cpio_data find_microcode_in_initrd(const char *path, bool use_pa) |
245 | { | |
246 | #ifdef CONFIG_BLK_DEV_INITRD | |
247 | unsigned long start = 0; | |
248 | size_t size; | |
249 | ||
250 | #ifdef CONFIG_X86_32 | |
251 | struct boot_params *params; | |
252 | ||
253 | if (use_pa) | |
254 | params = (struct boot_params *)__pa_nodebug(&boot_params); | |
255 | else | |
256 | params = &boot_params; | |
257 | ||
258 | size = params->hdr.ramdisk_size; | |
259 | ||
260 | /* | |
261 | * Set start only if we have an initrd image. We cannot use initrd_start | |
262 | * because it is not set that early yet. | |
263 | */ | |
264 | if (size) | |
265 | start = params->hdr.ramdisk_image; | |
266 | ||
267 | # else /* CONFIG_X86_64 */ | |
268 | size = (unsigned long)boot_params.ext_ramdisk_size << 32; | |
269 | size |= boot_params.hdr.ramdisk_size; | |
270 | ||
271 | if (size) { | |
272 | start = (unsigned long)boot_params.ext_ramdisk_image << 32; | |
273 | start |= boot_params.hdr.ramdisk_image; | |
274 | ||
275 | start += PAGE_OFFSET; | |
276 | } | |
277 | # endif | |
278 | ||
279 | /* | |
8877ebdd BP |
280 | * Fixup the start address: after reserve_initrd() runs, initrd_start |
281 | * has the virtual address of the beginning of the initrd. It also | |
282 | * possibly relocates the ramdisk. In either case, initrd_start contains | |
283 | * the updated address so use that instead. | |
24c25032 BP |
284 | * |
285 | * initrd_gone is for the hotplug case where we've thrown out initrd | |
286 | * already. | |
06b8534c | 287 | */ |
24c25032 BP |
288 | if (!use_pa) { |
289 | if (initrd_gone) | |
290 | return (struct cpio_data){ NULL, 0, "" }; | |
291 | if (initrd_start) | |
292 | start = initrd_start; | |
293 | } | |
06b8534c BP |
294 | |
295 | return find_cpio_data(path, (void *)start, size, NULL); | |
296 | #else /* !CONFIG_BLK_DEV_INITRD */ | |
297 | return (struct cpio_data){ NULL, 0, "" }; | |
298 | #endif | |
299 | } | |
300 | ||
fe055896 BP |
301 | void reload_early_microcode(void) |
302 | { | |
303 | int vendor, family; | |
304 | ||
99f925ce BP |
305 | vendor = x86_cpuid_vendor(); |
306 | family = x86_cpuid_family(); | |
fe055896 BP |
307 | |
308 | switch (vendor) { | |
309 | case X86_VENDOR_INTEL: | |
310 | if (family >= 6) | |
311 | reload_ucode_intel(); | |
312 | break; | |
313 | case X86_VENDOR_AMD: | |
314 | if (family >= 0x10) | |
315 | reload_ucode_amd(); | |
316 | break; | |
317 | default: | |
318 | break; | |
319 | } | |
320 | } | |
321 | ||
871b72dd DA |
322 | static void collect_cpu_info_local(void *arg) |
323 | { | |
324 | struct cpu_info_ctx *ctx = arg; | |
325 | ||
326 | ctx->err = microcode_ops->collect_cpu_info(smp_processor_id(), | |
327 | ctx->cpu_sig); | |
328 | } | |
329 | ||
330 | static int collect_cpu_info_on_target(int cpu, struct cpu_signature *cpu_sig) | |
331 | { | |
332 | struct cpu_info_ctx ctx = { .cpu_sig = cpu_sig, .err = 0 }; | |
333 | int ret; | |
334 | ||
335 | ret = smp_call_function_single(cpu, collect_cpu_info_local, &ctx, 1); | |
336 | if (!ret) | |
337 | ret = ctx.err; | |
338 | ||
339 | return ret; | |
340 | } | |
341 | ||
342 | static int collect_cpu_info(int cpu) | |
343 | { | |
344 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; | |
345 | int ret; | |
346 | ||
347 | memset(uci, 0, sizeof(*uci)); | |
348 | ||
349 | ret = collect_cpu_info_on_target(cpu, &uci->cpu_sig); | |
350 | if (!ret) | |
351 | uci->valid = 1; | |
352 | ||
353 | return ret; | |
354 | } | |
355 | ||
356 | struct apply_microcode_ctx { | |
357 | int err; | |
358 | }; | |
359 | ||
360 | static void apply_microcode_local(void *arg) | |
361 | { | |
362 | struct apply_microcode_ctx *ctx = arg; | |
363 | ||
364 | ctx->err = microcode_ops->apply_microcode(smp_processor_id()); | |
365 | } | |
366 | ||
367 | static int apply_microcode_on_target(int cpu) | |
368 | { | |
369 | struct apply_microcode_ctx ctx = { .err = 0 }; | |
370 | int ret; | |
371 | ||
372 | ret = smp_call_function_single(cpu, apply_microcode_local, &ctx, 1); | |
373 | if (!ret) | |
374 | ret = ctx.err; | |
375 | ||
376 | return ret; | |
377 | } | |
378 | ||
3e135d88 | 379 | #ifdef CONFIG_MICROCODE_OLD_INTERFACE |
a0a29b62 | 380 | static int do_microcode_update(const void __user *buf, size_t size) |
3e135d88 | 381 | { |
3e135d88 | 382 | int error = 0; |
3e135d88 | 383 | int cpu; |
6f66cbc6 | 384 | |
a0a29b62 DA |
385 | for_each_online_cpu(cpu) { |
386 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; | |
871b72dd | 387 | enum ucode_state ustate; |
a0a29b62 DA |
388 | |
389 | if (!uci->valid) | |
390 | continue; | |
6f66cbc6 | 391 | |
871b72dd DA |
392 | ustate = microcode_ops->request_microcode_user(cpu, buf, size); |
393 | if (ustate == UCODE_ERROR) { | |
394 | error = -1; | |
395 | break; | |
396 | } else if (ustate == UCODE_OK) | |
397 | apply_microcode_on_target(cpu); | |
3e135d88 | 398 | } |
871b72dd | 399 | |
3e135d88 PO |
400 | return error; |
401 | } | |
402 | ||
3f10940e | 403 | static int microcode_open(struct inode *inode, struct file *file) |
3e135d88 | 404 | { |
3f10940e | 405 | return capable(CAP_SYS_RAWIO) ? nonseekable_open(inode, file) : -EPERM; |
3e135d88 PO |
406 | } |
407 | ||
d33dcb9e PO |
408 | static ssize_t microcode_write(struct file *file, const char __user *buf, |
409 | size_t len, loff_t *ppos) | |
3e135d88 | 410 | { |
871b72dd | 411 | ssize_t ret = -EINVAL; |
3e135d88 | 412 | |
4481374c | 413 | if ((len >> PAGE_SHIFT) > totalram_pages) { |
f58e1f53 | 414 | pr_err("too much data (max %ld pages)\n", totalram_pages); |
871b72dd | 415 | return ret; |
3e135d88 PO |
416 | } |
417 | ||
418 | get_online_cpus(); | |
419 | mutex_lock(µcode_mutex); | |
420 | ||
871b72dd | 421 | if (do_microcode_update(buf, len) == 0) |
3e135d88 PO |
422 | ret = (ssize_t)len; |
423 | ||
e3e45c01 SE |
424 | if (ret > 0) |
425 | perf_check_microcode(); | |
426 | ||
3e135d88 PO |
427 | mutex_unlock(µcode_mutex); |
428 | put_online_cpus(); | |
429 | ||
430 | return ret; | |
431 | } | |
432 | ||
433 | static const struct file_operations microcode_fops = { | |
871b72dd DA |
434 | .owner = THIS_MODULE, |
435 | .write = microcode_write, | |
436 | .open = microcode_open, | |
6038f373 | 437 | .llseek = no_llseek, |
3e135d88 PO |
438 | }; |
439 | ||
440 | static struct miscdevice microcode_dev = { | |
871b72dd DA |
441 | .minor = MICROCODE_MINOR, |
442 | .name = "microcode", | |
e454cea2 | 443 | .nodename = "cpu/microcode", |
871b72dd | 444 | .fops = µcode_fops, |
3e135d88 PO |
445 | }; |
446 | ||
d33dcb9e | 447 | static int __init microcode_dev_init(void) |
3e135d88 PO |
448 | { |
449 | int error; | |
450 | ||
451 | error = misc_register(µcode_dev); | |
452 | if (error) { | |
f58e1f53 | 453 | pr_err("can't misc_register on minor=%d\n", MICROCODE_MINOR); |
3e135d88 PO |
454 | return error; |
455 | } | |
456 | ||
457 | return 0; | |
458 | } | |
459 | ||
bd399063 | 460 | static void __exit microcode_dev_exit(void) |
3e135d88 PO |
461 | { |
462 | misc_deregister(µcode_dev); | |
463 | } | |
3e135d88 | 464 | #else |
4bae1967 IM |
465 | #define microcode_dev_init() 0 |
466 | #define microcode_dev_exit() do { } while (0) | |
3e135d88 PO |
467 | #endif |
468 | ||
469 | /* fake device for request_firmware */ | |
4bae1967 | 470 | static struct platform_device *microcode_pdev; |
3e135d88 | 471 | |
871b72dd | 472 | static int reload_for_cpu(int cpu) |
af5c820a | 473 | { |
871b72dd | 474 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; |
4dbf32c3 | 475 | enum ucode_state ustate; |
af5c820a RR |
476 | int err = 0; |
477 | ||
4dbf32c3 BP |
478 | if (!uci->valid) |
479 | return err; | |
871b72dd | 480 | |
48e30685 | 481 | ustate = microcode_ops->request_microcode_fw(cpu, µcode_pdev->dev, true); |
4dbf32c3 BP |
482 | if (ustate == UCODE_OK) |
483 | apply_microcode_on_target(cpu); | |
484 | else | |
485 | if (ustate == UCODE_ERROR) | |
486 | err = -EINVAL; | |
af5c820a RR |
487 | return err; |
488 | } | |
489 | ||
8a25a2fd KS |
490 | static ssize_t reload_store(struct device *dev, |
491 | struct device_attribute *attr, | |
871b72dd | 492 | const char *buf, size_t size) |
3e135d88 | 493 | { |
871b72dd | 494 | unsigned long val; |
c9fc3f77 BP |
495 | int cpu; |
496 | ssize_t ret = 0, tmp_ret; | |
497 | ||
e826abd5 SK |
498 | ret = kstrtoul(buf, 0, &val); |
499 | if (ret) | |
500 | return ret; | |
871b72dd | 501 | |
c9fc3f77 BP |
502 | if (val != 1) |
503 | return size; | |
504 | ||
505 | get_online_cpus(); | |
c93dc84c | 506 | mutex_lock(µcode_mutex); |
c9fc3f77 BP |
507 | for_each_online_cpu(cpu) { |
508 | tmp_ret = reload_for_cpu(cpu); | |
509 | if (tmp_ret != 0) | |
510 | pr_warn("Error reloading microcode on CPU %d\n", cpu); | |
511 | ||
512 | /* save retval of the first encountered reload error */ | |
513 | if (!ret) | |
514 | ret = tmp_ret; | |
3e135d88 | 515 | } |
c93dc84c PZ |
516 | if (!ret) |
517 | perf_check_microcode(); | |
518 | mutex_unlock(µcode_mutex); | |
c9fc3f77 | 519 | put_online_cpus(); |
871b72dd DA |
520 | |
521 | if (!ret) | |
522 | ret = size; | |
523 | ||
524 | return ret; | |
3e135d88 PO |
525 | } |
526 | ||
8a25a2fd KS |
527 | static ssize_t version_show(struct device *dev, |
528 | struct device_attribute *attr, char *buf) | |
3e135d88 PO |
529 | { |
530 | struct ucode_cpu_info *uci = ucode_cpu_info + dev->id; | |
531 | ||
d45de409 | 532 | return sprintf(buf, "0x%x\n", uci->cpu_sig.rev); |
3e135d88 PO |
533 | } |
534 | ||
8a25a2fd KS |
535 | static ssize_t pf_show(struct device *dev, |
536 | struct device_attribute *attr, char *buf) | |
3e135d88 PO |
537 | { |
538 | struct ucode_cpu_info *uci = ucode_cpu_info + dev->id; | |
539 | ||
d45de409 | 540 | return sprintf(buf, "0x%x\n", uci->cpu_sig.pf); |
3e135d88 PO |
541 | } |
542 | ||
8a25a2fd KS |
543 | static DEVICE_ATTR(reload, 0200, NULL, reload_store); |
544 | static DEVICE_ATTR(version, 0400, version_show, NULL); | |
545 | static DEVICE_ATTR(processor_flags, 0400, pf_show, NULL); | |
3e135d88 PO |
546 | |
547 | static struct attribute *mc_default_attrs[] = { | |
8a25a2fd KS |
548 | &dev_attr_version.attr, |
549 | &dev_attr_processor_flags.attr, | |
3e135d88 PO |
550 | NULL |
551 | }; | |
552 | ||
553 | static struct attribute_group mc_attr_group = { | |
871b72dd DA |
554 | .attrs = mc_default_attrs, |
555 | .name = "microcode", | |
3e135d88 PO |
556 | }; |
557 | ||
871b72dd | 558 | static void microcode_fini_cpu(int cpu) |
d45de409 | 559 | { |
06b8534c BP |
560 | if (microcode_ops->microcode_fini_cpu) |
561 | microcode_ops->microcode_fini_cpu(cpu); | |
280a9ca5 DA |
562 | } |
563 | ||
871b72dd | 564 | static enum ucode_state microcode_resume_cpu(int cpu) |
d45de409 | 565 | { |
bb9d3e47 BP |
566 | if (apply_microcode_on_target(cpu)) |
567 | return UCODE_ERROR; | |
871b72dd | 568 | |
6b14b818 BP |
569 | pr_debug("CPU%d updated upon resume\n", cpu); |
570 | ||
871b72dd | 571 | return UCODE_OK; |
d45de409 DA |
572 | } |
573 | ||
48e30685 | 574 | static enum ucode_state microcode_init_cpu(int cpu, bool refresh_fw) |
d45de409 | 575 | { |
871b72dd | 576 | enum ucode_state ustate; |
9cd4d78e FY |
577 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; |
578 | ||
43858f57 | 579 | if (uci->valid) |
9cd4d78e | 580 | return UCODE_OK; |
d45de409 | 581 | |
871b72dd DA |
582 | if (collect_cpu_info(cpu)) |
583 | return UCODE_ERROR; | |
d45de409 | 584 | |
871b72dd DA |
585 | /* --dimm. Trigger a delayed update? */ |
586 | if (system_state != SYSTEM_RUNNING) | |
587 | return UCODE_NFOUND; | |
d45de409 | 588 | |
48e30685 BP |
589 | ustate = microcode_ops->request_microcode_fw(cpu, µcode_pdev->dev, |
590 | refresh_fw); | |
d45de409 | 591 | |
871b72dd | 592 | if (ustate == UCODE_OK) { |
f58e1f53 | 593 | pr_debug("CPU%d updated upon init\n", cpu); |
871b72dd | 594 | apply_microcode_on_target(cpu); |
d45de409 DA |
595 | } |
596 | ||
871b72dd | 597 | return ustate; |
d45de409 DA |
598 | } |
599 | ||
871b72dd | 600 | static enum ucode_state microcode_update_cpu(int cpu) |
d45de409 | 601 | { |
871b72dd | 602 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; |
d45de409 | 603 | |
7f709d0c BP |
604 | /* Refresh CPU microcode revision after resume. */ |
605 | collect_cpu_info(cpu); | |
606 | ||
2f99f5c8 | 607 | if (uci->valid) |
bb9d3e47 | 608 | return microcode_resume_cpu(cpu); |
d45de409 | 609 | |
48e30685 | 610 | return microcode_init_cpu(cpu, false); |
d45de409 DA |
611 | } |
612 | ||
8a25a2fd | 613 | static int mc_device_add(struct device *dev, struct subsys_interface *sif) |
3e135d88 | 614 | { |
8a25a2fd | 615 | int err, cpu = dev->id; |
3e135d88 PO |
616 | |
617 | if (!cpu_online(cpu)) | |
618 | return 0; | |
619 | ||
f58e1f53 | 620 | pr_debug("CPU%d added\n", cpu); |
3e135d88 | 621 | |
8a25a2fd | 622 | err = sysfs_create_group(&dev->kobj, &mc_attr_group); |
3e135d88 PO |
623 | if (err) |
624 | return err; | |
625 | ||
48e30685 | 626 | if (microcode_init_cpu(cpu, true) == UCODE_ERROR) |
6c53cbfc | 627 | return -EINVAL; |
af5c820a RR |
628 | |
629 | return err; | |
3e135d88 PO |
630 | } |
631 | ||
71db87ba | 632 | static void mc_device_remove(struct device *dev, struct subsys_interface *sif) |
3e135d88 | 633 | { |
8a25a2fd | 634 | int cpu = dev->id; |
3e135d88 PO |
635 | |
636 | if (!cpu_online(cpu)) | |
71db87ba | 637 | return; |
3e135d88 | 638 | |
f58e1f53 | 639 | pr_debug("CPU%d removed\n", cpu); |
d45de409 | 640 | microcode_fini_cpu(cpu); |
8a25a2fd | 641 | sysfs_remove_group(&dev->kobj, &mc_attr_group); |
3e135d88 PO |
642 | } |
643 | ||
8a25a2fd KS |
644 | static struct subsys_interface mc_cpu_interface = { |
645 | .name = "microcode", | |
646 | .subsys = &cpu_subsys, | |
647 | .add_dev = mc_device_add, | |
648 | .remove_dev = mc_device_remove, | |
f3c6ea1b RW |
649 | }; |
650 | ||
651 | /** | |
652 | * mc_bp_resume - Update boot CPU microcode during resume. | |
653 | */ | |
654 | static void mc_bp_resume(void) | |
3e135d88 | 655 | { |
f3c6ea1b | 656 | int cpu = smp_processor_id(); |
871b72dd | 657 | struct ucode_cpu_info *uci = ucode_cpu_info + cpu; |
3e135d88 | 658 | |
871b72dd DA |
659 | if (uci->valid && uci->mc) |
660 | microcode_ops->apply_microcode(cpu); | |
fb86b973 | 661 | else if (!uci->mc) |
fbae4ba8 | 662 | reload_early_microcode(); |
3e135d88 PO |
663 | } |
664 | ||
f3c6ea1b RW |
665 | static struct syscore_ops mc_syscore_ops = { |
666 | .resume = mc_bp_resume, | |
3e135d88 PO |
667 | }; |
668 | ||
29bd7fbc | 669 | static int mc_cpu_online(unsigned int cpu) |
3e135d88 | 670 | { |
8a25a2fd | 671 | struct device *dev; |
3e135d88 | 672 | |
8a25a2fd | 673 | dev = get_cpu_device(cpu); |
29bd7fbc SAS |
674 | microcode_update_cpu(cpu); |
675 | pr_debug("CPU%d added\n", cpu); | |
09c3f0d8 | 676 | |
29bd7fbc SAS |
677 | if (sysfs_create_group(&dev->kobj, &mc_attr_group)) |
678 | pr_err("Failed to create group for CPU%d\n", cpu); | |
679 | return 0; | |
680 | } | |
09c3f0d8 | 681 | |
29bd7fbc SAS |
682 | static int mc_cpu_down_prep(unsigned int cpu) |
683 | { | |
684 | struct device *dev; | |
70989449 | 685 | |
29bd7fbc SAS |
686 | dev = get_cpu_device(cpu); |
687 | /* Suspend is in progress, only remove the interface */ | |
688 | sysfs_remove_group(&dev->kobj, &mc_attr_group); | |
689 | pr_debug("CPU%d removed\n", cpu); | |
06b8534c | 690 | |
29bd7fbc | 691 | return 0; |
3e135d88 PO |
692 | } |
693 | ||
3d8986bc BP |
694 | static struct attribute *cpu_root_microcode_attrs[] = { |
695 | &dev_attr_reload.attr, | |
696 | NULL | |
697 | }; | |
698 | ||
699 | static struct attribute_group cpu_root_microcode_group = { | |
700 | .name = "microcode", | |
701 | .attrs = cpu_root_microcode_attrs, | |
702 | }; | |
703 | ||
9a2bc335 | 704 | int __init microcode_init(void) |
3e135d88 | 705 | { |
9a2bc335 | 706 | struct cpuinfo_x86 *c = &boot_cpu_data; |
3e135d88 PO |
707 | int error; |
708 | ||
84aba677 | 709 | if (dis_ucode_ldr) |
da63865a | 710 | return -EINVAL; |
65cef131 | 711 | |
18dbc916 DA |
712 | if (c->x86_vendor == X86_VENDOR_INTEL) |
713 | microcode_ops = init_intel_microcode(); | |
82b07865 | 714 | else if (c->x86_vendor == X86_VENDOR_AMD) |
18dbc916 | 715 | microcode_ops = init_amd_microcode(); |
283c1f25 | 716 | else |
f58e1f53 | 717 | pr_err("no support for this CPU vendor\n"); |
283c1f25 AH |
718 | |
719 | if (!microcode_ops) | |
18dbc916 | 720 | return -ENODEV; |
3e135d88 | 721 | |
3e135d88 PO |
722 | microcode_pdev = platform_device_register_simple("microcode", -1, |
723 | NULL, 0); | |
bd399063 | 724 | if (IS_ERR(microcode_pdev)) |
3e135d88 | 725 | return PTR_ERR(microcode_pdev); |
3e135d88 PO |
726 | |
727 | get_online_cpus(); | |
871b72dd DA |
728 | mutex_lock(µcode_mutex); |
729 | ||
8a25a2fd | 730 | error = subsys_interface_register(&mc_cpu_interface); |
c93dc84c PZ |
731 | if (!error) |
732 | perf_check_microcode(); | |
871b72dd | 733 | mutex_unlock(µcode_mutex); |
3e135d88 | 734 | put_online_cpus(); |
871b72dd | 735 | |
bd399063 SB |
736 | if (error) |
737 | goto out_pdev; | |
3e135d88 | 738 | |
3d8986bc BP |
739 | error = sysfs_create_group(&cpu_subsys.dev_root->kobj, |
740 | &cpu_root_microcode_group); | |
741 | ||
742 | if (error) { | |
743 | pr_err("Error creating microcode group!\n"); | |
744 | goto out_driver; | |
745 | } | |
746 | ||
871b72dd DA |
747 | error = microcode_dev_init(); |
748 | if (error) | |
3d8986bc | 749 | goto out_ucode_group; |
871b72dd | 750 | |
f3c6ea1b | 751 | register_syscore_ops(&mc_syscore_ops); |
29bd7fbc SAS |
752 | cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "x86/microcode:online", |
753 | mc_cpu_online, mc_cpu_down_prep); | |
8d86f390 | 754 | |
14cfbe55 | 755 | pr_info("Microcode Update Driver: v%s.", DRIVER_VERSION); |
8d86f390 | 756 | |
3e135d88 | 757 | return 0; |
bd399063 | 758 | |
3d8986bc BP |
759 | out_ucode_group: |
760 | sysfs_remove_group(&cpu_subsys.dev_root->kobj, | |
761 | &cpu_root_microcode_group); | |
762 | ||
763 | out_driver: | |
bd399063 SB |
764 | get_online_cpus(); |
765 | mutex_lock(µcode_mutex); | |
766 | ||
ff4b8a57 | 767 | subsys_interface_unregister(&mc_cpu_interface); |
bd399063 SB |
768 | |
769 | mutex_unlock(µcode_mutex); | |
770 | put_online_cpus(); | |
771 | ||
3d8986bc | 772 | out_pdev: |
bd399063 SB |
773 | platform_device_unregister(microcode_pdev); |
774 | return error; | |
775 | ||
3e135d88 | 776 | } |
4b703305 | 777 | fs_initcall(save_microcode_in_initrd); |
2d5be37d | 778 | late_initcall(microcode_init); |