[thirdparty/linux.git] / arch / x86 / kernel / cpu / perfctr-watchdog.c

// SPDX-License-Identifier: GPL-2.0
/*
 * local apic based NMI watchdog for various CPUs.
 *
 * This file also handles reservation of performance counters for coordination
 * with other users (like oprofile).
 *
 * Note that these events normally don't tick when the CPU idles. This means
 * the frequency varies with CPU load.
 *
 * Original code for K7/P6 written by Keith Owens
 *
 */

#include <linux/percpu.h>
#include <linux/export.h>
#include <linux/kernel.h>
#include <linux/bitops.h>
#include <linux/smp.h>
#include <asm/nmi.h>
#include <linux/kprobes.h>

#include <asm/apic.h>
#include <asm/perf_event.h>

/*
 * this number is calculated from Intel's MSR_P4_CRU_ESCR5 register and it's
 * offset from MSR_P4_BSU_ESCR0.
 *
 * It will be the max for all platforms (for now)
 */
#define NMI_MAX_COUNTER_BITS 66

/*
 * perfctr_nmi_owner tracks the ownership of the perfctr registers:
 * evtsel_nmi_owner tracks the ownership of the event selection
 * - different performance counters/ event selection may be reserved for
 *   different subsystems this reservation system just tries to coordinate
 *   things a little
 */
static DECLARE_BITMAP(perfctr_nmi_owner, NMI_MAX_COUNTER_BITS);
static DECLARE_BITMAP(evntsel_nmi_owner, NMI_MAX_COUNTER_BITS);

/* converts an msr to an appropriate reservation bit */
static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr)
{
	/* returns the bit offset of the performance counter register */
	switch (boot_cpu_data.x86_vendor) {
	case X86_VENDOR_HYGON:
	case X86_VENDOR_AMD:
		if (msr >= MSR_F15H_PERF_CTR)
			return (msr - MSR_F15H_PERF_CTR) >> 1;
		return msr - MSR_K7_PERFCTR0;
	case X86_VENDOR_INTEL:
		if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
			return msr - MSR_ARCH_PERFMON_PERFCTR0;

		switch (boot_cpu_data.x86) {
		case 6:
			return msr - MSR_P6_PERFCTR0;
		case 11:
			return msr - MSR_KNC_PERFCTR0;
		case 15:
			return msr - MSR_P4_BPU_PERFCTR0;
		}
		fallthrough;
	case X86_VENDOR_ZHAOXIN:
	case X86_VENDOR_CENTAUR:
		return msr - MSR_ARCH_PERFMON_PERFCTR0;
	}
	return 0;
}

/*
 * converts an msr to an appropriate reservation bit
 * returns the bit offset of the event selection register
 */
static inline unsigned int nmi_evntsel_msr_to_bit(unsigned int msr)
{
	/* returns the bit offset of the event selection register */
	switch (boot_cpu_data.x86_vendor) {
	case X86_VENDOR_HYGON:
	case X86_VENDOR_AMD:
		if (msr >= MSR_F15H_PERF_CTL)
			return (msr - MSR_F15H_PERF_CTL) >> 1;
		return msr - MSR_K7_EVNTSEL0;
	case X86_VENDOR_INTEL:
		if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
			return msr - MSR_ARCH_PERFMON_EVENTSEL0;

		switch (boot_cpu_data.x86) {
		case 6:
			return msr - MSR_P6_EVNTSEL0;
		case 11:
			return msr - MSR_KNC_EVNTSEL0;
		case 15:
			return msr - MSR_P4_BSU_ESCR0;
		}
		fallthrough;
	case X86_VENDOR_ZHAOXIN:
	case X86_VENDOR_CENTAUR:
		return msr - MSR_ARCH_PERFMON_EVENTSEL0;
	}
	return 0;

}

/* checks for a bit availability (hack for oprofile) */
int avail_to_resrv_perfctr_nmi_bit(unsigned int counter)
{
	BUG_ON(counter > NMI_MAX_COUNTER_BITS);

	return !test_bit(counter, perfctr_nmi_owner);
}
EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi_bit);

int reserve_perfctr_nmi(unsigned int msr)
{
	unsigned int counter;

	counter = nmi_perfctr_msr_to_bit(msr);
	/* register not managed by the allocator? */
	if (counter > NMI_MAX_COUNTER_BITS)
		return 1;

	if (!test_and_set_bit(counter, perfctr_nmi_owner))
		return 1;
	return 0;
}
EXPORT_SYMBOL(reserve_perfctr_nmi);

void release_perfctr_nmi(unsigned int msr)
{
	unsigned int counter;

	counter = nmi_perfctr_msr_to_bit(msr);
	/* register not managed by the allocator? */
	if (counter > NMI_MAX_COUNTER_BITS)
		return;

	clear_bit(counter, perfctr_nmi_owner);
}
EXPORT_SYMBOL(release_perfctr_nmi);

int reserve_evntsel_nmi(unsigned int msr)
{
	unsigned int counter;

	counter = nmi_evntsel_msr_to_bit(msr);
	/* register not managed by the allocator? */
	if (counter > NMI_MAX_COUNTER_BITS)
		return 1;

	if (!test_and_set_bit(counter, evntsel_nmi_owner))
		return 1;
	return 0;
}
EXPORT_SYMBOL(reserve_evntsel_nmi);

void release_evntsel_nmi(unsigned int msr)
{
	unsigned int counter;

	counter = nmi_evntsel_msr_to_bit(msr);
	/* register not managed by the allocator? */
	if (counter > NMI_MAX_COUNTER_BITS)
		return;

	clear_bit(counter, evntsel_nmi_owner);
}
EXPORT_SYMBOL(release_evntsel_nmi);
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
47a486cc CG	2	/*
	3	* local apic based NMI watchdog for various CPUs.
	4	*
	5	* This file also handles reservation of performance counters for coordination
	6	* with other users (like oprofile).
	7	*
	8	* Note that these events normally don't tick when the CPU idles. This means
	9	* the frequency varies with CPU load.
	10	*
	11	* Original code for K7/P6 written by Keith Owens
	12	*
	13	*/
09198e68 AK	14
09198e68 AK	15	#include <linux/percpu.h>
186f4360	16	#include <linux/export.h>
09198e68 AK	17	#include <linux/kernel.h>
	18	#include <linux/bitops.h>
	19	#include <linux/smp.h>
4a7863cc	20	#include <asm/nmi.h>
8b1fa1d7 IM	21	#include <linux/kprobes.h>
8b1fa1d7 IM	22
09198e68	23	#include <asm/apic.h>
cdd6c482	24	#include <asm/perf_event.h>
09198e68	25
47a486cc CG	26	/*
	27	* this number is calculated from Intel's MSR_P4_CRU_ESCR5 register and it's
	28	* offset from MSR_P4_BSU_ESCR0.
	29	*
	30	* It will be the max for all platforms (for now)
09198e68 AK	31	*/
	32	#define NMI_MAX_COUNTER_BITS 66
	33
47a486cc CG	34	/*
47a486cc CG	35	* perfctr_nmi_owner tracks the ownership of the perfctr registers:
09198e68 AK	36	* evtsel_nmi_owner tracks the ownership of the event selection
	37	* - different performance counters/ event selection may be reserved for
	38	* different subsystems this reservation system just tries to coordinate
	39	* things a little
	40	*/
	41	static DECLARE_BITMAP(perfctr_nmi_owner, NMI_MAX_COUNTER_BITS);
	42	static DECLARE_BITMAP(evntsel_nmi_owner, NMI_MAX_COUNTER_BITS);
	43
09198e68 AK	44	/* converts an msr to an appropriate reservation bit */
	45	static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr)
	46	{
5dcccd8d AK	47	/* returns the bit offset of the performance counter register */
5dcccd8d AK	48	switch (boot_cpu_data.x86_vendor) {
6d0ef316	49	case X86_VENDOR_HYGON:
5dcccd8d	50	case X86_VENDOR_AMD:
69d8e1e8 RR	51	if (msr >= MSR_F15H_PERF_CTR)
69d8e1e8 RR	52	return (msr - MSR_F15H_PERF_CTR) >> 1;
8bdbd962	53	return msr - MSR_K7_PERFCTR0;
5dcccd8d AK	54	case X86_VENDOR_INTEL:
5dcccd8d AK	55	if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
8bdbd962	56	return msr - MSR_ARCH_PERFMON_PERFCTR0;
5dcccd8d AK	57
	58	switch (boot_cpu_data.x86) {
	59	case 6:
8bdbd962	60	return msr - MSR_P6_PERFCTR0;
e717bf4e VW	61	case 11:
e717bf4e VW	62	return msr - MSR_KNC_PERFCTR0;
5dcccd8d	63	case 15:
8bdbd962	64	return msr - MSR_P4_BPU_PERFCTR0;
5dcccd8d	65	}
3a4ac121 C	66	fallthrough;
	67	case X86_VENDOR_ZHAOXIN:
	68	case X86_VENDOR_CENTAUR:
	69	return msr - MSR_ARCH_PERFMON_PERFCTR0;
5dcccd8d AK	70	}
5dcccd8d AK	71	return 0;
09198e68 AK	72	}
09198e68 AK	73
47a486cc CG	74	/*
	75	* converts an msr to an appropriate reservation bit
	76	* returns the bit offset of the event selection register
	77	*/
09198e68 AK	78	static inline unsigned int nmi_evntsel_msr_to_bit(unsigned int msr)
09198e68 AK	79	{
5dcccd8d AK	80	/* returns the bit offset of the event selection register */
5dcccd8d AK	81	switch (boot_cpu_data.x86_vendor) {
6d0ef316	82	case X86_VENDOR_HYGON:
5dcccd8d	83	case X86_VENDOR_AMD:
69d8e1e8 RR	84	if (msr >= MSR_F15H_PERF_CTL)
69d8e1e8 RR	85	return (msr - MSR_F15H_PERF_CTL) >> 1;
8bdbd962	86	return msr - MSR_K7_EVNTSEL0;
5dcccd8d AK	87	case X86_VENDOR_INTEL:
5dcccd8d AK	88	if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
8bdbd962	89	return msr - MSR_ARCH_PERFMON_EVENTSEL0;
5dcccd8d AK	90
	91	switch (boot_cpu_data.x86) {
	92	case 6:
8bdbd962	93	return msr - MSR_P6_EVNTSEL0;
e717bf4e VW	94	case 11:
e717bf4e VW	95	return msr - MSR_KNC_EVNTSEL0;
5dcccd8d	96	case 15:
8bdbd962	97	return msr - MSR_P4_BSU_ESCR0;
5dcccd8d	98	}
3a4ac121 C	99	fallthrough;
	100	case X86_VENDOR_ZHAOXIN:
	101	case X86_VENDOR_CENTAUR:
	102	return msr - MSR_ARCH_PERFMON_EVENTSEL0;
5dcccd8d AK	103	}
	104	return 0;
	105
09198e68 AK	106	}
	107
	108	/* checks for a bit availability (hack for oprofile) */
	109	int avail_to_resrv_perfctr_nmi_bit(unsigned int counter)
	110	{
	111	BUG_ON(counter > NMI_MAX_COUNTER_BITS);
	112
8bdbd962	113	return !test_bit(counter, perfctr_nmi_owner);
09198e68	114	}
47a486cc	115	EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi_bit);
09198e68 AK	116
	117	int reserve_perfctr_nmi(unsigned int msr)
	118	{
	119	unsigned int counter;
	120
	121	counter = nmi_perfctr_msr_to_bit(msr);
124d395f SE	122	/* register not managed by the allocator? */
	123	if (counter > NMI_MAX_COUNTER_BITS)
	124	return 1;
09198e68 AK	125
	126	if (!test_and_set_bit(counter, perfctr_nmi_owner))
	127	return 1;
	128	return 0;
	129	}
47a486cc	130	EXPORT_SYMBOL(reserve_perfctr_nmi);
09198e68 AK	131
	132	void release_perfctr_nmi(unsigned int msr)
	133	{
	134	unsigned int counter;
	135
	136	counter = nmi_perfctr_msr_to_bit(msr);
124d395f SE	137	/* register not managed by the allocator? */
	138	if (counter > NMI_MAX_COUNTER_BITS)
	139	return;
09198e68 AK	140
	141	clear_bit(counter, perfctr_nmi_owner);
	142	}
47a486cc	143	EXPORT_SYMBOL(release_perfctr_nmi);
09198e68 AK	144
	145	int reserve_evntsel_nmi(unsigned int msr)
	146	{
	147	unsigned int counter;
	148
	149	counter = nmi_evntsel_msr_to_bit(msr);
124d395f SE	150	/* register not managed by the allocator? */
	151	if (counter > NMI_MAX_COUNTER_BITS)
	152	return 1;
09198e68 AK	153
	154	if (!test_and_set_bit(counter, evntsel_nmi_owner))
	155	return 1;
	156	return 0;
	157	}
47a486cc	158	EXPORT_SYMBOL(reserve_evntsel_nmi);
09198e68 AK	159
	160	void release_evntsel_nmi(unsigned int msr)
	161	{
	162	unsigned int counter;
	163
	164	counter = nmi_evntsel_msr_to_bit(msr);
124d395f SE	165	/* register not managed by the allocator? */
	166	if (counter > NMI_MAX_COUNTER_BITS)
	167	return;
09198e68 AK	168
	169	clear_bit(counter, evntsel_nmi_owner);
	170	}
09198e68	171	EXPORT_SYMBOL(release_evntsel_nmi);