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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Copyright (C) 1994 Linus Torvalds |
3 | * | |
4 | * Pentium III FXSR, SSE support | |
5 | * General FPU state handling cleanups | |
6 | * Gareth Hughes <gareth@valinux.com>, May 2000 | |
7 | */ | |
78f7f1e5 | 8 | #include <asm/fpu/internal.h> |
91066588 | 9 | #include <linux/hardirq.h> |
1da177e4 | 10 | |
085cc281 IM |
11 | /* |
12 | * Track whether the kernel is using the FPU state | |
13 | * currently. | |
14 | * | |
15 | * This flag is used: | |
16 | * | |
17 | * - by IRQ context code to potentially use the FPU | |
18 | * if it's unused. | |
19 | * | |
20 | * - to debug kernel_fpu_begin()/end() correctness | |
21 | */ | |
14e153ef ON |
22 | static DEFINE_PER_CPU(bool, in_kernel_fpu); |
23 | ||
b0c050c5 | 24 | /* |
36b544dc | 25 | * Track which context is using the FPU on the CPU: |
b0c050c5 | 26 | */ |
36b544dc | 27 | DEFINE_PER_CPU(struct fpu *, fpu_fpregs_owner_ctx); |
b0c050c5 | 28 | |
416d49ac | 29 | static void kernel_fpu_disable(void) |
7575637a ON |
30 | { |
31 | WARN_ON(this_cpu_read(in_kernel_fpu)); | |
32 | this_cpu_write(in_kernel_fpu, true); | |
33 | } | |
34 | ||
416d49ac | 35 | static void kernel_fpu_enable(void) |
7575637a | 36 | { |
3103ae3a | 37 | WARN_ON_ONCE(!this_cpu_read(in_kernel_fpu)); |
7575637a ON |
38 | this_cpu_write(in_kernel_fpu, false); |
39 | } | |
40 | ||
085cc281 IM |
41 | static bool kernel_fpu_disabled(void) |
42 | { | |
43 | return this_cpu_read(in_kernel_fpu); | |
44 | } | |
45 | ||
8546c008 LT |
46 | /* |
47 | * Were we in an interrupt that interrupted kernel mode? | |
48 | * | |
304bceda | 49 | * On others, we can do a kernel_fpu_begin/end() pair *ONLY* if that |
8546c008 LT |
50 | * pair does nothing at all: the thread must not have fpu (so |
51 | * that we don't try to save the FPU state), and TS must | |
52 | * be set (so that the clts/stts pair does nothing that is | |
53 | * visible in the interrupted kernel thread). | |
5187b28f | 54 | * |
4b2e762e ON |
55 | * Except for the eagerfpu case when we return true; in the likely case |
56 | * the thread has FPU but we are not going to set/clear TS. | |
8546c008 | 57 | */ |
416d49ac | 58 | static bool interrupted_kernel_fpu_idle(void) |
8546c008 | 59 | { |
085cc281 | 60 | if (kernel_fpu_disabled()) |
14e153ef ON |
61 | return false; |
62 | ||
5d2bd700 | 63 | if (use_eager_fpu()) |
4b2e762e | 64 | return true; |
304bceda | 65 | |
d5cea9b0 | 66 | return !current->thread.fpu.fpregs_active && (read_cr0() & X86_CR0_TS); |
8546c008 LT |
67 | } |
68 | ||
69 | /* | |
70 | * Were we in user mode (or vm86 mode) when we were | |
71 | * interrupted? | |
72 | * | |
73 | * Doing kernel_fpu_begin/end() is ok if we are running | |
74 | * in an interrupt context from user mode - we'll just | |
75 | * save the FPU state as required. | |
76 | */ | |
416d49ac | 77 | static bool interrupted_user_mode(void) |
8546c008 LT |
78 | { |
79 | struct pt_regs *regs = get_irq_regs(); | |
f39b6f0e | 80 | return regs && user_mode(regs); |
8546c008 LT |
81 | } |
82 | ||
83 | /* | |
84 | * Can we use the FPU in kernel mode with the | |
85 | * whole "kernel_fpu_begin/end()" sequence? | |
86 | * | |
87 | * It's always ok in process context (ie "not interrupt") | |
88 | * but it is sometimes ok even from an irq. | |
89 | */ | |
90 | bool irq_fpu_usable(void) | |
91 | { | |
92 | return !in_interrupt() || | |
93 | interrupted_user_mode() || | |
94 | interrupted_kernel_fpu_idle(); | |
95 | } | |
96 | EXPORT_SYMBOL(irq_fpu_usable); | |
97 | ||
b1a74bf8 | 98 | void __kernel_fpu_begin(void) |
8546c008 | 99 | { |
36b544dc | 100 | struct fpu *fpu = ¤t->thread.fpu; |
8546c008 | 101 | |
3103ae3a | 102 | kernel_fpu_disable(); |
14e153ef | 103 | |
d5cea9b0 | 104 | if (fpu->fpregs_active) { |
276983f8 | 105 | fpu_save_init(fpu); |
7aeccb83 | 106 | } else { |
36b544dc | 107 | this_cpu_write(fpu_fpregs_owner_ctx, NULL); |
7aeccb83 ON |
108 | if (!use_eager_fpu()) |
109 | clts(); | |
8546c008 LT |
110 | } |
111 | } | |
b1a74bf8 | 112 | EXPORT_SYMBOL(__kernel_fpu_begin); |
8546c008 | 113 | |
b1a74bf8 | 114 | void __kernel_fpu_end(void) |
8546c008 | 115 | { |
af2d94fd | 116 | struct fpu *fpu = ¤t->thread.fpu; |
33a3ebdc | 117 | |
d5cea9b0 | 118 | if (fpu->fpregs_active) { |
11f2d50b | 119 | if (WARN_ON(restore_fpu_checking(fpu))) |
af2d94fd | 120 | fpu_reset_state(fpu); |
33a3ebdc | 121 | } else if (!use_eager_fpu()) { |
304bceda | 122 | stts(); |
731bd6a9 | 123 | } |
14e153ef | 124 | |
3103ae3a | 125 | kernel_fpu_enable(); |
8546c008 | 126 | } |
b1a74bf8 | 127 | EXPORT_SYMBOL(__kernel_fpu_end); |
8546c008 | 128 | |
d63e79b1 IM |
129 | void kernel_fpu_begin(void) |
130 | { | |
131 | preempt_disable(); | |
132 | WARN_ON_ONCE(!irq_fpu_usable()); | |
133 | __kernel_fpu_begin(); | |
134 | } | |
135 | EXPORT_SYMBOL_GPL(kernel_fpu_begin); | |
136 | ||
137 | void kernel_fpu_end(void) | |
138 | { | |
139 | __kernel_fpu_end(); | |
140 | preempt_enable(); | |
141 | } | |
142 | EXPORT_SYMBOL_GPL(kernel_fpu_end); | |
143 | ||
91066588 IM |
144 | /* |
145 | * CR0::TS save/restore functions: | |
146 | */ | |
147 | int irq_ts_save(void) | |
148 | { | |
149 | /* | |
150 | * If in process context and not atomic, we can take a spurious DNA fault. | |
151 | * Otherwise, doing clts() in process context requires disabling preemption | |
152 | * or some heavy lifting like kernel_fpu_begin() | |
153 | */ | |
154 | if (!in_atomic()) | |
155 | return 0; | |
156 | ||
157 | if (read_cr0() & X86_CR0_TS) { | |
158 | clts(); | |
159 | return 1; | |
160 | } | |
161 | ||
162 | return 0; | |
163 | } | |
164 | EXPORT_SYMBOL_GPL(irq_ts_save); | |
165 | ||
166 | void irq_ts_restore(int TS_state) | |
167 | { | |
168 | if (TS_state) | |
169 | stts(); | |
170 | } | |
171 | EXPORT_SYMBOL_GPL(irq_ts_restore); | |
172 | ||
a4d8fc2e | 173 | static void __save_fpu(struct fpu *fpu) |
2d75bcf3 IM |
174 | { |
175 | if (use_xsave()) { | |
176 | if (unlikely(system_state == SYSTEM_BOOTING)) | |
a4d8fc2e | 177 | xsave_state_booting(&fpu->state->xsave); |
2d75bcf3 | 178 | else |
a4d8fc2e | 179 | xsave_state(&fpu->state->xsave); |
2d75bcf3 | 180 | } else { |
a4d8fc2e | 181 | fpu_fxsave(fpu); |
2d75bcf3 IM |
182 | } |
183 | } | |
184 | ||
4af08f2f IM |
185 | /* |
186 | * Save the FPU state (initialize it if necessary): | |
87cdb98a IM |
187 | * |
188 | * This only ever gets called for the current task. | |
4af08f2f | 189 | */ |
0c070595 | 190 | void fpu__save(struct fpu *fpu) |
8546c008 | 191 | { |
0c070595 | 192 | WARN_ON(fpu != ¤t->thread.fpu); |
87cdb98a | 193 | |
8546c008 | 194 | preempt_disable(); |
d5cea9b0 | 195 | if (fpu->fpregs_active) { |
1a2a7f4e | 196 | if (use_eager_fpu()) { |
a4d8fc2e | 197 | __save_fpu(fpu); |
1a2a7f4e | 198 | } else { |
276983f8 | 199 | fpu_save_init(fpu); |
66af8e27 | 200 | fpregs_deactivate(fpu); |
1a2a7f4e | 201 | } |
a9241ea5 | 202 | } |
8546c008 LT |
203 | preempt_enable(); |
204 | } | |
4af08f2f | 205 | EXPORT_SYMBOL_GPL(fpu__save); |
8546c008 | 206 | |
c0ee2cf6 | 207 | void fpstate_init(struct fpu *fpu) |
1da177e4 | 208 | { |
60e019eb | 209 | if (!cpu_has_fpu) { |
86603283 AK |
210 | finit_soft_fpu(&fpu->state->soft); |
211 | return; | |
e8a496ac | 212 | } |
e8a496ac | 213 | |
1d23c451 ON |
214 | memset(fpu->state, 0, xstate_size); |
215 | ||
1da177e4 | 216 | if (cpu_has_fxsr) { |
5d2bd700 | 217 | fx_finit(&fpu->state->fxsave); |
1da177e4 | 218 | } else { |
86603283 | 219 | struct i387_fsave_struct *fp = &fpu->state->fsave; |
61c4628b SS |
220 | fp->cwd = 0xffff037fu; |
221 | fp->swd = 0xffff0000u; | |
222 | fp->twd = 0xffffffffu; | |
223 | fp->fos = 0xffff0000u; | |
1da177e4 | 224 | } |
86603283 | 225 | } |
c0ee2cf6 | 226 | EXPORT_SYMBOL_GPL(fpstate_init); |
86603283 | 227 | |
8ffb53ab IM |
228 | /* |
229 | * FPU state allocation: | |
230 | */ | |
f55f88e2 | 231 | static struct kmem_cache *task_xstate_cachep; |
8ffb53ab IM |
232 | |
233 | void fpstate_cache_init(void) | |
234 | { | |
235 | task_xstate_cachep = | |
236 | kmem_cache_create("task_xstate", xstate_size, | |
237 | __alignof__(union thread_xstate), | |
238 | SLAB_PANIC | SLAB_NOTRACK, NULL); | |
239 | setup_xstate_comp(); | |
240 | } | |
241 | ||
ed97b085 | 242 | int fpstate_alloc(struct fpu *fpu) |
6fbe6712 IM |
243 | { |
244 | if (fpu->state) | |
245 | return 0; | |
ed97b085 | 246 | |
6fbe6712 IM |
247 | fpu->state = kmem_cache_alloc(task_xstate_cachep, GFP_KERNEL); |
248 | if (!fpu->state) | |
249 | return -ENOMEM; | |
ed97b085 IM |
250 | |
251 | /* The CPU requires the FPU state to be aligned to 16 byte boundaries: */ | |
6fbe6712 | 252 | WARN_ON((unsigned long)fpu->state & 15); |
ed97b085 | 253 | |
6fbe6712 IM |
254 | return 0; |
255 | } | |
ed97b085 | 256 | EXPORT_SYMBOL_GPL(fpstate_alloc); |
6fbe6712 | 257 | |
5a12bf63 IM |
258 | void fpstate_free(struct fpu *fpu) |
259 | { | |
260 | if (fpu->state) { | |
261 | kmem_cache_free(task_xstate_cachep, fpu->state); | |
262 | fpu->state = NULL; | |
263 | } | |
264 | } | |
265 | EXPORT_SYMBOL_GPL(fpstate_free); | |
266 | ||
bfd6fc05 IM |
267 | /* |
268 | * Copy the current task's FPU state to a new task's FPU context. | |
269 | * | |
270 | * In the 'eager' case we just save to the destination context. | |
271 | * | |
272 | * In the 'lazy' case we save to the source context, mark the FPU lazy | |
273 | * via stts() and copy the source context into the destination context. | |
274 | */ | |
f9bc977f | 275 | static void fpu_copy(struct fpu *dst_fpu, struct fpu *src_fpu) |
e102f30f | 276 | { |
f9bc977f | 277 | WARN_ON(src_fpu != ¤t->thread.fpu); |
bfd6fc05 | 278 | |
e102f30f | 279 | if (use_eager_fpu()) { |
f9bc977f | 280 | memset(&dst_fpu->state->xsave, 0, xstate_size); |
a4d8fc2e | 281 | __save_fpu(dst_fpu); |
e102f30f | 282 | } else { |
0c070595 | 283 | fpu__save(src_fpu); |
a4d8fc2e | 284 | memcpy(dst_fpu->state, src_fpu->state, xstate_size); |
e102f30f IM |
285 | } |
286 | } | |
287 | ||
c69e098b | 288 | int fpu__copy(struct fpu *dst_fpu, struct fpu *src_fpu) |
a752b53d | 289 | { |
c69e098b | 290 | dst_fpu->counter = 0; |
d5cea9b0 | 291 | dst_fpu->fpregs_active = 0; |
c69e098b IM |
292 | dst_fpu->state = NULL; |
293 | dst_fpu->last_cpu = -1; | |
a752b53d | 294 | |
c5bedc68 IM |
295 | if (src_fpu->fpstate_active) { |
296 | int err = fpstate_alloc(dst_fpu); | |
a752b53d IM |
297 | |
298 | if (err) | |
299 | return err; | |
f9bc977f | 300 | fpu_copy(dst_fpu, src_fpu); |
a752b53d IM |
301 | } |
302 | return 0; | |
303 | } | |
304 | ||
97185c95 IM |
305 | /* |
306 | * Allocate the backing store for the current task's FPU registers | |
307 | * and initialize the registers themselves as well. | |
308 | * | |
309 | * Can fail. | |
310 | */ | |
db2b1d3a | 311 | int fpstate_alloc_init(struct fpu *fpu) |
97185c95 IM |
312 | { |
313 | int ret; | |
314 | ||
db2b1d3a | 315 | if (WARN_ON_ONCE(fpu != ¤t->thread.fpu)) |
97185c95 | 316 | return -EINVAL; |
c5bedc68 | 317 | if (WARN_ON_ONCE(fpu->fpstate_active)) |
97185c95 IM |
318 | return -EINVAL; |
319 | ||
320 | /* | |
321 | * Memory allocation at the first usage of the FPU and other state. | |
322 | */ | |
db2b1d3a | 323 | ret = fpstate_alloc(fpu); |
97185c95 IM |
324 | if (ret) |
325 | return ret; | |
326 | ||
db2b1d3a | 327 | fpstate_init(fpu); |
97185c95 IM |
328 | |
329 | /* Safe to do for the current task: */ | |
c5bedc68 | 330 | fpu->fpstate_active = 1; |
97185c95 IM |
331 | |
332 | return 0; | |
333 | } | |
334 | EXPORT_SYMBOL_GPL(fpstate_alloc_init); | |
335 | ||
86603283 | 336 | /* |
af7f8721 IM |
337 | * This function is called before we modify a stopped child's |
338 | * FPU state context. | |
339 | * | |
340 | * If the child has not used the FPU before then initialize its | |
341 | * FPU context. | |
342 | * | |
343 | * If the child has used the FPU before then unlazy it. | |
344 | * | |
345 | * [ After this function call, after the context is modified and | |
346 | * the child task is woken up, the child task will restore | |
347 | * the modified FPU state from the modified context. If we | |
348 | * didn't clear its lazy status here then the lazy in-registers | |
349 | * state pending on its former CPU could be restored, losing | |
350 | * the modifications. ] | |
351 | * | |
352 | * This function is also called before we read a stopped child's | |
353 | * FPU state - to make sure it's modified. | |
354 | * | |
355 | * TODO: A future optimization would be to skip the unlazying in | |
356 | * the read-only case, it's not strictly necessary for | |
357 | * read-only access to the context. | |
86603283 | 358 | */ |
cc08d545 | 359 | static int fpu__unlazy_stopped(struct fpu *child_fpu) |
86603283 AK |
360 | { |
361 | int ret; | |
362 | ||
cc08d545 | 363 | if (WARN_ON_ONCE(child_fpu == ¤t->thread.fpu)) |
67e97fc2 IM |
364 | return -EINVAL; |
365 | ||
c5bedc68 | 366 | if (child_fpu->fpstate_active) { |
cc08d545 | 367 | child_fpu->last_cpu = -1; |
86603283 AK |
368 | return 0; |
369 | } | |
370 | ||
44210111 | 371 | /* |
86603283 | 372 | * Memory allocation at the first usage of the FPU and other state. |
44210111 | 373 | */ |
cc08d545 | 374 | ret = fpstate_alloc(child_fpu); |
86603283 AK |
375 | if (ret) |
376 | return ret; | |
377 | ||
cc08d545 | 378 | fpstate_init(child_fpu); |
86603283 | 379 | |
071ae621 | 380 | /* Safe to do for stopped child tasks: */ |
c5bedc68 | 381 | child_fpu->fpstate_active = 1; |
071ae621 | 382 | |
aa283f49 | 383 | return 0; |
1da177e4 LT |
384 | } |
385 | ||
93b90712 | 386 | /* |
3a0aee48 | 387 | * 'fpu__restore()' saves the current math information in the |
93b90712 IM |
388 | * old math state array, and gets the new ones from the current task |
389 | * | |
390 | * Careful.. There are problems with IBM-designed IRQ13 behaviour. | |
391 | * Don't touch unless you *really* know how it works. | |
392 | * | |
393 | * Must be called with kernel preemption disabled (eg with local | |
394 | * local interrupts as in the case of do_device_not_available). | |
395 | */ | |
3a0aee48 | 396 | void fpu__restore(void) |
93b90712 IM |
397 | { |
398 | struct task_struct *tsk = current; | |
4540d3fa | 399 | struct fpu *fpu = &tsk->thread.fpu; |
93b90712 | 400 | |
c5bedc68 | 401 | if (!fpu->fpstate_active) { |
93b90712 IM |
402 | local_irq_enable(); |
403 | /* | |
404 | * does a slab alloc which can sleep | |
405 | */ | |
db2b1d3a | 406 | if (fpstate_alloc_init(fpu)) { |
93b90712 IM |
407 | /* |
408 | * ran out of memory! | |
409 | */ | |
410 | do_group_exit(SIGKILL); | |
411 | return; | |
412 | } | |
413 | local_irq_disable(); | |
414 | } | |
415 | ||
232f62cd | 416 | /* Avoid __kernel_fpu_begin() right after fpregs_activate() */ |
93b90712 | 417 | kernel_fpu_disable(); |
232f62cd | 418 | fpregs_activate(fpu); |
11f2d50b | 419 | if (unlikely(restore_fpu_checking(fpu))) { |
af2d94fd | 420 | fpu_reset_state(fpu); |
93b90712 IM |
421 | force_sig_info(SIGSEGV, SEND_SIG_PRIV, tsk); |
422 | } else { | |
423 | tsk->thread.fpu.counter++; | |
424 | } | |
425 | kernel_fpu_enable(); | |
426 | } | |
3a0aee48 | 427 | EXPORT_SYMBOL_GPL(fpu__restore); |
93b90712 | 428 | |
2e8a3102 | 429 | void fpu__clear(struct task_struct *tsk) |
81683cc8 | 430 | { |
c5bedc68 IM |
431 | struct fpu *fpu = &tsk->thread.fpu; |
432 | ||
2e8a3102 | 433 | WARN_ON_ONCE(tsk != current); /* Almost certainly an anomaly */ |
4c138410 | 434 | |
81683cc8 IM |
435 | if (!use_eager_fpu()) { |
436 | /* FPU state will be reallocated lazily at the first use. */ | |
ca6787ba | 437 | drop_fpu(fpu); |
e11267c1 | 438 | fpstate_free(fpu); |
81683cc8 | 439 | } else { |
c5bedc68 | 440 | if (!fpu->fpstate_active) { |
81683cc8 | 441 | /* kthread execs. TODO: cleanup this horror. */ |
e11267c1 | 442 | if (WARN_ON(fpstate_alloc_init(fpu))) |
81683cc8 IM |
443 | force_sig(SIGKILL, tsk); |
444 | user_fpu_begin(); | |
445 | } | |
446 | restore_init_xstate(); | |
447 | } | |
448 | } | |
449 | ||
5b3efd50 | 450 | /* |
678eaf60 | 451 | * The xstateregs_active() routine is the same as the regset_fpregs_active() routine, |
5b3efd50 SS |
452 | * as the "regset->n" for the xstate regset will be updated based on the feature |
453 | * capabilites supported by the xsave. | |
454 | */ | |
678eaf60 | 455 | int regset_fpregs_active(struct task_struct *target, const struct user_regset *regset) |
44210111 | 456 | { |
c5bedc68 IM |
457 | struct fpu *target_fpu = &target->thread.fpu; |
458 | ||
459 | return target_fpu->fpstate_active ? regset->n : 0; | |
44210111 | 460 | } |
1da177e4 | 461 | |
678eaf60 | 462 | int regset_xregset_fpregs_active(struct task_struct *target, const struct user_regset *regset) |
1da177e4 | 463 | { |
c5bedc68 IM |
464 | struct fpu *target_fpu = &target->thread.fpu; |
465 | ||
466 | return (cpu_has_fxsr && target_fpu->fpstate_active) ? regset->n : 0; | |
44210111 | 467 | } |
1da177e4 | 468 | |
44210111 RM |
469 | int xfpregs_get(struct task_struct *target, const struct user_regset *regset, |
470 | unsigned int pos, unsigned int count, | |
471 | void *kbuf, void __user *ubuf) | |
472 | { | |
cc08d545 | 473 | struct fpu *fpu = &target->thread.fpu; |
aa283f49 SS |
474 | int ret; |
475 | ||
44210111 RM |
476 | if (!cpu_has_fxsr) |
477 | return -ENODEV; | |
478 | ||
cc08d545 | 479 | ret = fpu__unlazy_stopped(fpu); |
aa283f49 SS |
480 | if (ret) |
481 | return ret; | |
44210111 | 482 | |
29104e10 SS |
483 | sanitize_i387_state(target); |
484 | ||
44210111 | 485 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, |
8dcea8db | 486 | &fpu->state->fxsave, 0, -1); |
1da177e4 | 487 | } |
44210111 RM |
488 | |
489 | int xfpregs_set(struct task_struct *target, const struct user_regset *regset, | |
490 | unsigned int pos, unsigned int count, | |
491 | const void *kbuf, const void __user *ubuf) | |
492 | { | |
cc08d545 | 493 | struct fpu *fpu = &target->thread.fpu; |
44210111 RM |
494 | int ret; |
495 | ||
496 | if (!cpu_has_fxsr) | |
497 | return -ENODEV; | |
498 | ||
cc08d545 | 499 | ret = fpu__unlazy_stopped(fpu); |
aa283f49 SS |
500 | if (ret) |
501 | return ret; | |
502 | ||
29104e10 SS |
503 | sanitize_i387_state(target); |
504 | ||
44210111 | 505 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, |
8dcea8db | 506 | &fpu->state->fxsave, 0, -1); |
44210111 RM |
507 | |
508 | /* | |
509 | * mxcsr reserved bits must be masked to zero for security reasons. | |
510 | */ | |
8dcea8db | 511 | fpu->state->fxsave.mxcsr &= mxcsr_feature_mask; |
44210111 | 512 | |
42deec6f SS |
513 | /* |
514 | * update the header bits in the xsave header, indicating the | |
515 | * presence of FP and SSE state. | |
516 | */ | |
517 | if (cpu_has_xsave) | |
400e4b20 | 518 | fpu->state->xsave.header.xfeatures |= XSTATE_FPSSE; |
42deec6f | 519 | |
44210111 RM |
520 | return ret; |
521 | } | |
522 | ||
5b3efd50 SS |
523 | int xstateregs_get(struct task_struct *target, const struct user_regset *regset, |
524 | unsigned int pos, unsigned int count, | |
525 | void *kbuf, void __user *ubuf) | |
526 | { | |
cc08d545 | 527 | struct fpu *fpu = &target->thread.fpu; |
18ecb3bf | 528 | struct xsave_struct *xsave; |
5b3efd50 SS |
529 | int ret; |
530 | ||
531 | if (!cpu_has_xsave) | |
532 | return -ENODEV; | |
533 | ||
cc08d545 | 534 | ret = fpu__unlazy_stopped(fpu); |
5b3efd50 SS |
535 | if (ret) |
536 | return ret; | |
537 | ||
8dcea8db | 538 | xsave = &fpu->state->xsave; |
18ecb3bf | 539 | |
5b3efd50 | 540 | /* |
ff7fbc72 SS |
541 | * Copy the 48bytes defined by the software first into the xstate |
542 | * memory layout in the thread struct, so that we can copy the entire | |
543 | * xstateregs to the user using one user_regset_copyout(). | |
5b3efd50 | 544 | */ |
e7f180dc ON |
545 | memcpy(&xsave->i387.sw_reserved, |
546 | xstate_fx_sw_bytes, sizeof(xstate_fx_sw_bytes)); | |
5b3efd50 | 547 | /* |
ff7fbc72 | 548 | * Copy the xstate memory layout. |
5b3efd50 | 549 | */ |
e7f180dc | 550 | ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, xsave, 0, -1); |
5b3efd50 SS |
551 | return ret; |
552 | } | |
553 | ||
554 | int xstateregs_set(struct task_struct *target, const struct user_regset *regset, | |
555 | unsigned int pos, unsigned int count, | |
556 | const void *kbuf, const void __user *ubuf) | |
557 | { | |
cc08d545 | 558 | struct fpu *fpu = &target->thread.fpu; |
18ecb3bf | 559 | struct xsave_struct *xsave; |
5b3efd50 | 560 | int ret; |
5b3efd50 SS |
561 | |
562 | if (!cpu_has_xsave) | |
563 | return -ENODEV; | |
564 | ||
cc08d545 | 565 | ret = fpu__unlazy_stopped(fpu); |
5b3efd50 SS |
566 | if (ret) |
567 | return ret; | |
568 | ||
8dcea8db | 569 | xsave = &fpu->state->xsave; |
18ecb3bf | 570 | |
e7f180dc | 571 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, xsave, 0, -1); |
5b3efd50 SS |
572 | /* |
573 | * mxcsr reserved bits must be masked to zero for security reasons. | |
574 | */ | |
e7f180dc | 575 | xsave->i387.mxcsr &= mxcsr_feature_mask; |
400e4b20 | 576 | xsave->header.xfeatures &= xfeatures_mask; |
5b3efd50 SS |
577 | /* |
578 | * These bits must be zero. | |
579 | */ | |
3a54450b | 580 | memset(&xsave->header.reserved, 0, 48); |
8dcea8db | 581 | |
5b3efd50 SS |
582 | return ret; |
583 | } | |
584 | ||
44210111 | 585 | #if defined CONFIG_X86_32 || defined CONFIG_IA32_EMULATION |
1da177e4 | 586 | |
1da177e4 LT |
587 | /* |
588 | * FPU tag word conversions. | |
589 | */ | |
590 | ||
3b095a04 | 591 | static inline unsigned short twd_i387_to_fxsr(unsigned short twd) |
1da177e4 LT |
592 | { |
593 | unsigned int tmp; /* to avoid 16 bit prefixes in the code */ | |
3b095a04 | 594 | |
1da177e4 | 595 | /* Transform each pair of bits into 01 (valid) or 00 (empty) */ |
3b095a04 | 596 | tmp = ~twd; |
44210111 | 597 | tmp = (tmp | (tmp>>1)) & 0x5555; /* 0V0V0V0V0V0V0V0V */ |
3b095a04 CG |
598 | /* and move the valid bits to the lower byte. */ |
599 | tmp = (tmp | (tmp >> 1)) & 0x3333; /* 00VV00VV00VV00VV */ | |
600 | tmp = (tmp | (tmp >> 2)) & 0x0f0f; /* 0000VVVV0000VVVV */ | |
601 | tmp = (tmp | (tmp >> 4)) & 0x00ff; /* 00000000VVVVVVVV */ | |
f668964e | 602 | |
3b095a04 | 603 | return tmp; |
1da177e4 LT |
604 | } |
605 | ||
497888cf | 606 | #define FPREG_ADDR(f, n) ((void *)&(f)->st_space + (n) * 16) |
44210111 RM |
607 | #define FP_EXP_TAG_VALID 0 |
608 | #define FP_EXP_TAG_ZERO 1 | |
609 | #define FP_EXP_TAG_SPECIAL 2 | |
610 | #define FP_EXP_TAG_EMPTY 3 | |
611 | ||
612 | static inline u32 twd_fxsr_to_i387(struct i387_fxsave_struct *fxsave) | |
613 | { | |
614 | struct _fpxreg *st; | |
615 | u32 tos = (fxsave->swd >> 11) & 7; | |
616 | u32 twd = (unsigned long) fxsave->twd; | |
617 | u32 tag; | |
618 | u32 ret = 0xffff0000u; | |
619 | int i; | |
1da177e4 | 620 | |
44210111 | 621 | for (i = 0; i < 8; i++, twd >>= 1) { |
3b095a04 CG |
622 | if (twd & 0x1) { |
623 | st = FPREG_ADDR(fxsave, (i - tos) & 7); | |
1da177e4 | 624 | |
3b095a04 | 625 | switch (st->exponent & 0x7fff) { |
1da177e4 | 626 | case 0x7fff: |
44210111 | 627 | tag = FP_EXP_TAG_SPECIAL; |
1da177e4 LT |
628 | break; |
629 | case 0x0000: | |
3b095a04 CG |
630 | if (!st->significand[0] && |
631 | !st->significand[1] && | |
632 | !st->significand[2] && | |
44210111 RM |
633 | !st->significand[3]) |
634 | tag = FP_EXP_TAG_ZERO; | |
635 | else | |
636 | tag = FP_EXP_TAG_SPECIAL; | |
1da177e4 LT |
637 | break; |
638 | default: | |
44210111 RM |
639 | if (st->significand[3] & 0x8000) |
640 | tag = FP_EXP_TAG_VALID; | |
641 | else | |
642 | tag = FP_EXP_TAG_SPECIAL; | |
1da177e4 LT |
643 | break; |
644 | } | |
645 | } else { | |
44210111 | 646 | tag = FP_EXP_TAG_EMPTY; |
1da177e4 | 647 | } |
44210111 | 648 | ret |= tag << (2 * i); |
1da177e4 LT |
649 | } |
650 | return ret; | |
651 | } | |
652 | ||
653 | /* | |
44210111 | 654 | * FXSR floating point environment conversions. |
1da177e4 LT |
655 | */ |
656 | ||
72a671ce | 657 | void |
f668964e | 658 | convert_from_fxsr(struct user_i387_ia32_struct *env, struct task_struct *tsk) |
1da177e4 | 659 | { |
86603283 | 660 | struct i387_fxsave_struct *fxsave = &tsk->thread.fpu.state->fxsave; |
44210111 RM |
661 | struct _fpreg *to = (struct _fpreg *) &env->st_space[0]; |
662 | struct _fpxreg *from = (struct _fpxreg *) &fxsave->st_space[0]; | |
663 | int i; | |
1da177e4 | 664 | |
44210111 RM |
665 | env->cwd = fxsave->cwd | 0xffff0000u; |
666 | env->swd = fxsave->swd | 0xffff0000u; | |
667 | env->twd = twd_fxsr_to_i387(fxsave); | |
668 | ||
669 | #ifdef CONFIG_X86_64 | |
670 | env->fip = fxsave->rip; | |
671 | env->foo = fxsave->rdp; | |
10c11f30 BG |
672 | /* |
673 | * should be actually ds/cs at fpu exception time, but | |
674 | * that information is not available in 64bit mode. | |
675 | */ | |
676 | env->fcs = task_pt_regs(tsk)->cs; | |
44210111 | 677 | if (tsk == current) { |
10c11f30 | 678 | savesegment(ds, env->fos); |
1da177e4 | 679 | } else { |
10c11f30 | 680 | env->fos = tsk->thread.ds; |
1da177e4 | 681 | } |
10c11f30 | 682 | env->fos |= 0xffff0000; |
44210111 RM |
683 | #else |
684 | env->fip = fxsave->fip; | |
609b5297 | 685 | env->fcs = (u16) fxsave->fcs | ((u32) fxsave->fop << 16); |
44210111 RM |
686 | env->foo = fxsave->foo; |
687 | env->fos = fxsave->fos; | |
688 | #endif | |
1da177e4 | 689 | |
44210111 RM |
690 | for (i = 0; i < 8; ++i) |
691 | memcpy(&to[i], &from[i], sizeof(to[0])); | |
1da177e4 LT |
692 | } |
693 | ||
72a671ce SS |
694 | void convert_to_fxsr(struct task_struct *tsk, |
695 | const struct user_i387_ia32_struct *env) | |
1da177e4 | 696 | |
1da177e4 | 697 | { |
86603283 | 698 | struct i387_fxsave_struct *fxsave = &tsk->thread.fpu.state->fxsave; |
44210111 RM |
699 | struct _fpreg *from = (struct _fpreg *) &env->st_space[0]; |
700 | struct _fpxreg *to = (struct _fpxreg *) &fxsave->st_space[0]; | |
701 | int i; | |
1da177e4 | 702 | |
44210111 RM |
703 | fxsave->cwd = env->cwd; |
704 | fxsave->swd = env->swd; | |
705 | fxsave->twd = twd_i387_to_fxsr(env->twd); | |
706 | fxsave->fop = (u16) ((u32) env->fcs >> 16); | |
707 | #ifdef CONFIG_X86_64 | |
708 | fxsave->rip = env->fip; | |
709 | fxsave->rdp = env->foo; | |
710 | /* cs and ds ignored */ | |
711 | #else | |
712 | fxsave->fip = env->fip; | |
713 | fxsave->fcs = (env->fcs & 0xffff); | |
714 | fxsave->foo = env->foo; | |
715 | fxsave->fos = env->fos; | |
716 | #endif | |
1da177e4 | 717 | |
44210111 RM |
718 | for (i = 0; i < 8; ++i) |
719 | memcpy(&to[i], &from[i], sizeof(from[0])); | |
1da177e4 LT |
720 | } |
721 | ||
44210111 RM |
722 | int fpregs_get(struct task_struct *target, const struct user_regset *regset, |
723 | unsigned int pos, unsigned int count, | |
724 | void *kbuf, void __user *ubuf) | |
1da177e4 | 725 | { |
cc08d545 | 726 | struct fpu *fpu = &target->thread.fpu; |
44210111 | 727 | struct user_i387_ia32_struct env; |
aa283f49 | 728 | int ret; |
1da177e4 | 729 | |
cc08d545 | 730 | ret = fpu__unlazy_stopped(fpu); |
aa283f49 SS |
731 | if (ret) |
732 | return ret; | |
1da177e4 | 733 | |
60e019eb | 734 | if (!static_cpu_has(X86_FEATURE_FPU)) |
e8a496ac SS |
735 | return fpregs_soft_get(target, regset, pos, count, kbuf, ubuf); |
736 | ||
60e019eb | 737 | if (!cpu_has_fxsr) |
44210111 | 738 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, |
8dcea8db | 739 | &fpu->state->fsave, 0, |
61c4628b | 740 | -1); |
1da177e4 | 741 | |
29104e10 SS |
742 | sanitize_i387_state(target); |
743 | ||
44210111 RM |
744 | if (kbuf && pos == 0 && count == sizeof(env)) { |
745 | convert_from_fxsr(kbuf, target); | |
746 | return 0; | |
1da177e4 | 747 | } |
44210111 RM |
748 | |
749 | convert_from_fxsr(&env, target); | |
f668964e | 750 | |
44210111 | 751 | return user_regset_copyout(&pos, &count, &kbuf, &ubuf, &env, 0, -1); |
1da177e4 LT |
752 | } |
753 | ||
44210111 RM |
754 | int fpregs_set(struct task_struct *target, const struct user_regset *regset, |
755 | unsigned int pos, unsigned int count, | |
756 | const void *kbuf, const void __user *ubuf) | |
1da177e4 | 757 | { |
cc08d545 | 758 | struct fpu *fpu = &target->thread.fpu; |
44210111 RM |
759 | struct user_i387_ia32_struct env; |
760 | int ret; | |
1da177e4 | 761 | |
cc08d545 | 762 | ret = fpu__unlazy_stopped(fpu); |
aa283f49 SS |
763 | if (ret) |
764 | return ret; | |
765 | ||
29104e10 SS |
766 | sanitize_i387_state(target); |
767 | ||
60e019eb | 768 | if (!static_cpu_has(X86_FEATURE_FPU)) |
e8a496ac SS |
769 | return fpregs_soft_set(target, regset, pos, count, kbuf, ubuf); |
770 | ||
60e019eb | 771 | if (!cpu_has_fxsr) |
44210111 | 772 | return user_regset_copyin(&pos, &count, &kbuf, &ubuf, |
8dcea8db | 773 | &fpu->state->fsave, 0, |
60e019eb | 774 | -1); |
44210111 RM |
775 | |
776 | if (pos > 0 || count < sizeof(env)) | |
777 | convert_from_fxsr(&env, target); | |
778 | ||
779 | ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &env, 0, -1); | |
780 | if (!ret) | |
781 | convert_to_fxsr(target, &env); | |
782 | ||
42deec6f SS |
783 | /* |
784 | * update the header bit in the xsave header, indicating the | |
785 | * presence of FP. | |
786 | */ | |
787 | if (cpu_has_xsave) | |
400e4b20 | 788 | fpu->state->xsave.header.xfeatures |= XSTATE_FP; |
44210111 | 789 | return ret; |
1da177e4 LT |
790 | } |
791 | ||
1da177e4 LT |
792 | /* |
793 | * FPU state for core dumps. | |
60b3b9af RM |
794 | * This is only used for a.out dumps now. |
795 | * It is declared generically using elf_fpregset_t (which is | |
796 | * struct user_i387_struct) but is in fact only used for 32-bit | |
797 | * dumps, so on 64-bit it is really struct user_i387_ia32_struct. | |
1da177e4 | 798 | */ |
c5bedc68 | 799 | int dump_fpu(struct pt_regs *regs, struct user_i387_struct *ufpu) |
1da177e4 | 800 | { |
1da177e4 | 801 | struct task_struct *tsk = current; |
c5bedc68 | 802 | struct fpu *fpu = &tsk->thread.fpu; |
f668964e | 803 | int fpvalid; |
1da177e4 | 804 | |
c5bedc68 | 805 | fpvalid = fpu->fpstate_active; |
60b3b9af RM |
806 | if (fpvalid) |
807 | fpvalid = !fpregs_get(tsk, NULL, | |
808 | 0, sizeof(struct user_i387_ia32_struct), | |
c5bedc68 | 809 | ufpu, NULL); |
1da177e4 LT |
810 | |
811 | return fpvalid; | |
812 | } | |
129f6946 | 813 | EXPORT_SYMBOL(dump_fpu); |
1da177e4 | 814 | |
60b3b9af | 815 | #endif /* CONFIG_X86_32 || CONFIG_IA32_EMULATION */ |