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x86/fpu: Move 'PER_CPU(fpu_owner_task)' to fpu/core.c
[people/arne_f/kernel.git] / arch / x86 / kernel / fpu / core.c
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1da177e4 1/*
1da177e4
LT
2 * Copyright (C) 1994 Linus Torvalds
3 *
4 * Pentium III FXSR, SSE support
5 * General FPU state handling cleanups
6 * Gareth Hughes <gareth@valinux.com>, May 2000
7 */
1361b83a 8#include <asm/fpu-internal.h>
1da177e4 9
085cc281
IM
10/*
11 * Track whether the kernel is using the FPU state
12 * currently.
13 *
14 * This flag is used:
15 *
16 * - by IRQ context code to potentially use the FPU
17 * if it's unused.
18 *
19 * - to debug kernel_fpu_begin()/end() correctness
20 */
14e153ef
ON
21static DEFINE_PER_CPU(bool, in_kernel_fpu);
22
b0c050c5
IM
23/*
24 * Track which task is using the FPU on the CPU:
25 */
26DEFINE_PER_CPU(struct task_struct *, fpu_owner_task);
27
416d49ac 28static void kernel_fpu_disable(void)
7575637a
ON
29{
30 WARN_ON(this_cpu_read(in_kernel_fpu));
31 this_cpu_write(in_kernel_fpu, true);
32}
33
416d49ac 34static void kernel_fpu_enable(void)
7575637a 35{
3103ae3a 36 WARN_ON_ONCE(!this_cpu_read(in_kernel_fpu));
7575637a
ON
37 this_cpu_write(in_kernel_fpu, false);
38}
39
085cc281
IM
40static bool kernel_fpu_disabled(void)
41{
42 return this_cpu_read(in_kernel_fpu);
43}
44
8546c008
LT
45/*
46 * Were we in an interrupt that interrupted kernel mode?
47 *
304bceda 48 * On others, we can do a kernel_fpu_begin/end() pair *ONLY* if that
8546c008
LT
49 * pair does nothing at all: the thread must not have fpu (so
50 * that we don't try to save the FPU state), and TS must
51 * be set (so that the clts/stts pair does nothing that is
52 * visible in the interrupted kernel thread).
5187b28f 53 *
4b2e762e
ON
54 * Except for the eagerfpu case when we return true; in the likely case
55 * the thread has FPU but we are not going to set/clear TS.
8546c008 56 */
416d49ac 57static bool interrupted_kernel_fpu_idle(void)
8546c008 58{
085cc281 59 if (kernel_fpu_disabled())
14e153ef
ON
60 return false;
61
5d2bd700 62 if (use_eager_fpu())
4b2e762e 63 return true;
304bceda 64
276983f8 65 return !current->thread.fpu.has_fpu && (read_cr0() & X86_CR0_TS);
8546c008
LT
66}
67
68/*
69 * Were we in user mode (or vm86 mode) when we were
70 * interrupted?
71 *
72 * Doing kernel_fpu_begin/end() is ok if we are running
73 * in an interrupt context from user mode - we'll just
74 * save the FPU state as required.
75 */
416d49ac 76static bool interrupted_user_mode(void)
8546c008
LT
77{
78 struct pt_regs *regs = get_irq_regs();
f39b6f0e 79 return regs && user_mode(regs);
8546c008
LT
80}
81
82/*
83 * Can we use the FPU in kernel mode with the
84 * whole "kernel_fpu_begin/end()" sequence?
85 *
86 * It's always ok in process context (ie "not interrupt")
87 * but it is sometimes ok even from an irq.
88 */
89bool irq_fpu_usable(void)
90{
91 return !in_interrupt() ||
92 interrupted_user_mode() ||
93 interrupted_kernel_fpu_idle();
94}
95EXPORT_SYMBOL(irq_fpu_usable);
96
b1a74bf8 97void __kernel_fpu_begin(void)
8546c008
LT
98{
99 struct task_struct *me = current;
276983f8 100 struct fpu *fpu = &me->thread.fpu;
8546c008 101
3103ae3a 102 kernel_fpu_disable();
14e153ef 103
276983f8
IM
104 if (fpu->has_fpu) {
105 fpu_save_init(fpu);
7aeccb83 106 } else {
c6ae41e7 107 this_cpu_write(fpu_owner_task, NULL);
7aeccb83
ON
108 if (!use_eager_fpu())
109 clts();
8546c008
LT
110 }
111}
b1a74bf8 112EXPORT_SYMBOL(__kernel_fpu_begin);
8546c008 113
b1a74bf8 114void __kernel_fpu_end(void)
8546c008 115{
33a3ebdc 116 struct task_struct *me = current;
276983f8 117 struct fpu *fpu = &me->thread.fpu;
33a3ebdc 118
276983f8 119 if (fpu->has_fpu) {
33a3ebdc 120 if (WARN_ON(restore_fpu_checking(me)))
b85e67d1 121 fpu_reset_state(me);
33a3ebdc 122 } else if (!use_eager_fpu()) {
304bceda 123 stts();
731bd6a9 124 }
14e153ef 125
3103ae3a 126 kernel_fpu_enable();
8546c008 127}
b1a74bf8 128EXPORT_SYMBOL(__kernel_fpu_end);
8546c008 129
4af08f2f
IM
130/*
131 * Save the FPU state (initialize it if necessary):
87cdb98a
IM
132 *
133 * This only ever gets called for the current task.
4af08f2f 134 */
0a781551 135void fpu__save(struct task_struct *tsk)
8546c008 136{
276983f8
IM
137 struct fpu *fpu = &tsk->thread.fpu;
138
87cdb98a
IM
139 WARN_ON(tsk != current);
140
8546c008 141 preempt_disable();
276983f8 142 if (fpu->has_fpu) {
1a2a7f4e
ON
143 if (use_eager_fpu()) {
144 __save_fpu(tsk);
145 } else {
276983f8 146 fpu_save_init(fpu);
1a2a7f4e
ON
147 __thread_fpu_end(tsk);
148 }
a9241ea5 149 }
8546c008
LT
150 preempt_enable();
151}
4af08f2f 152EXPORT_SYMBOL_GPL(fpu__save);
8546c008 153
c0ee2cf6 154void fpstate_init(struct fpu *fpu)
1da177e4 155{
60e019eb 156 if (!cpu_has_fpu) {
86603283
AK
157 finit_soft_fpu(&fpu->state->soft);
158 return;
e8a496ac 159 }
e8a496ac 160
1d23c451
ON
161 memset(fpu->state, 0, xstate_size);
162
1da177e4 163 if (cpu_has_fxsr) {
5d2bd700 164 fx_finit(&fpu->state->fxsave);
1da177e4 165 } else {
86603283 166 struct i387_fsave_struct *fp = &fpu->state->fsave;
61c4628b
SS
167 fp->cwd = 0xffff037fu;
168 fp->swd = 0xffff0000u;
169 fp->twd = 0xffffffffu;
170 fp->fos = 0xffff0000u;
1da177e4 171 }
86603283 172}
c0ee2cf6 173EXPORT_SYMBOL_GPL(fpstate_init);
86603283 174
8ffb53ab
IM
175/*
176 * FPU state allocation:
177 */
f55f88e2 178static struct kmem_cache *task_xstate_cachep;
8ffb53ab
IM
179
180void fpstate_cache_init(void)
181{
182 task_xstate_cachep =
183 kmem_cache_create("task_xstate", xstate_size,
184 __alignof__(union thread_xstate),
185 SLAB_PANIC | SLAB_NOTRACK, NULL);
186 setup_xstate_comp();
187}
188
ed97b085 189int fpstate_alloc(struct fpu *fpu)
6fbe6712
IM
190{
191 if (fpu->state)
192 return 0;
ed97b085 193
6fbe6712
IM
194 fpu->state = kmem_cache_alloc(task_xstate_cachep, GFP_KERNEL);
195 if (!fpu->state)
196 return -ENOMEM;
ed97b085
IM
197
198 /* The CPU requires the FPU state to be aligned to 16 byte boundaries: */
6fbe6712 199 WARN_ON((unsigned long)fpu->state & 15);
ed97b085 200
6fbe6712
IM
201 return 0;
202}
ed97b085 203EXPORT_SYMBOL_GPL(fpstate_alloc);
6fbe6712 204
5a12bf63
IM
205void fpstate_free(struct fpu *fpu)
206{
207 if (fpu->state) {
208 kmem_cache_free(task_xstate_cachep, fpu->state);
209 fpu->state = NULL;
210 }
211}
212EXPORT_SYMBOL_GPL(fpstate_free);
213
bfd6fc05
IM
214/*
215 * Copy the current task's FPU state to a new task's FPU context.
216 *
217 * In the 'eager' case we just save to the destination context.
218 *
219 * In the 'lazy' case we save to the source context, mark the FPU lazy
220 * via stts() and copy the source context into the destination context.
221 */
e102f30f
IM
222static void fpu_copy(struct task_struct *dst, struct task_struct *src)
223{
bfd6fc05
IM
224 WARN_ON(src != current);
225
e102f30f
IM
226 if (use_eager_fpu()) {
227 memset(&dst->thread.fpu.state->xsave, 0, xstate_size);
228 __save_fpu(dst);
229 } else {
230 struct fpu *dfpu = &dst->thread.fpu;
231 struct fpu *sfpu = &src->thread.fpu;
232
233 fpu__save(src);
234 memcpy(dfpu->state, sfpu->state, xstate_size);
235 }
236}
237
a752b53d
IM
238int fpu__copy(struct task_struct *dst, struct task_struct *src)
239{
240 dst->thread.fpu.counter = 0;
241 dst->thread.fpu.has_fpu = 0;
242 dst->thread.fpu.state = NULL;
243
244 task_disable_lazy_fpu_restore(dst);
245
246 if (tsk_used_math(src)) {
247 int err = fpstate_alloc(&dst->thread.fpu);
248
249 if (err)
250 return err;
251 fpu_copy(dst, src);
252 }
253 return 0;
254}
255
97185c95
IM
256/*
257 * Allocate the backing store for the current task's FPU registers
258 * and initialize the registers themselves as well.
259 *
260 * Can fail.
261 */
262int fpstate_alloc_init(struct task_struct *curr)
263{
264 int ret;
265
266 if (WARN_ON_ONCE(curr != current))
267 return -EINVAL;
268 if (WARN_ON_ONCE(curr->flags & PF_USED_MATH))
269 return -EINVAL;
270
271 /*
272 * Memory allocation at the first usage of the FPU and other state.
273 */
ed97b085 274 ret = fpstate_alloc(&curr->thread.fpu);
97185c95
IM
275 if (ret)
276 return ret;
277
c0ee2cf6 278 fpstate_init(&curr->thread.fpu);
97185c95
IM
279
280 /* Safe to do for the current task: */
281 curr->flags |= PF_USED_MATH;
282
283 return 0;
284}
285EXPORT_SYMBOL_GPL(fpstate_alloc_init);
286
86603283
AK
287/*
288 * The _current_ task is using the FPU for the first time
289 * so initialize it and set the mxcsr to its default
290 * value at reset if we support XMM instructions and then
0d2eb44f 291 * remember the current task has used the FPU.
86603283 292 */
67e97fc2 293static int fpu__unlazy_stopped(struct task_struct *child)
86603283
AK
294{
295 int ret;
296
67e97fc2
IM
297 if (WARN_ON_ONCE(child == current))
298 return -EINVAL;
299
071ae621 300 if (child->flags & PF_USED_MATH) {
67e97fc2 301 task_disable_lazy_fpu_restore(child);
86603283
AK
302 return 0;
303 }
304
44210111 305 /*
86603283 306 * Memory allocation at the first usage of the FPU and other state.
44210111 307 */
ed97b085 308 ret = fpstate_alloc(&child->thread.fpu);
86603283
AK
309 if (ret)
310 return ret;
311
c0ee2cf6 312 fpstate_init(&child->thread.fpu);
86603283 313
071ae621
IM
314 /* Safe to do for stopped child tasks: */
315 child->flags |= PF_USED_MATH;
316
aa283f49 317 return 0;
1da177e4
LT
318}
319
93b90712 320/*
3a0aee48 321 * 'fpu__restore()' saves the current math information in the
93b90712
IM
322 * old math state array, and gets the new ones from the current task
323 *
324 * Careful.. There are problems with IBM-designed IRQ13 behaviour.
325 * Don't touch unless you *really* know how it works.
326 *
327 * Must be called with kernel preemption disabled (eg with local
328 * local interrupts as in the case of do_device_not_available).
329 */
3a0aee48 330void fpu__restore(void)
93b90712
IM
331{
332 struct task_struct *tsk = current;
333
334 if (!tsk_used_math(tsk)) {
335 local_irq_enable();
336 /*
337 * does a slab alloc which can sleep
338 */
339 if (fpstate_alloc_init(tsk)) {
340 /*
341 * ran out of memory!
342 */
343 do_group_exit(SIGKILL);
344 return;
345 }
346 local_irq_disable();
347 }
348
349 /* Avoid __kernel_fpu_begin() right after __thread_fpu_begin() */
350 kernel_fpu_disable();
351 __thread_fpu_begin(tsk);
352 if (unlikely(restore_fpu_checking(tsk))) {
353 fpu_reset_state(tsk);
354 force_sig_info(SIGSEGV, SEND_SIG_PRIV, tsk);
355 } else {
356 tsk->thread.fpu.counter++;
357 }
358 kernel_fpu_enable();
359}
3a0aee48 360EXPORT_SYMBOL_GPL(fpu__restore);
93b90712 361
81683cc8
IM
362void fpu__flush_thread(struct task_struct *tsk)
363{
364 if (!use_eager_fpu()) {
365 /* FPU state will be reallocated lazily at the first use. */
366 drop_fpu(tsk);
367 fpstate_free(&tsk->thread.fpu);
368 } else {
369 if (!tsk_used_math(tsk)) {
370 /* kthread execs. TODO: cleanup this horror. */
371 if (WARN_ON(fpstate_alloc_init(tsk)))
372 force_sig(SIGKILL, tsk);
373 user_fpu_begin();
374 }
375 restore_init_xstate();
376 }
377}
378
5b3efd50
SS
379/*
380 * The xstateregs_active() routine is the same as the fpregs_active() routine,
381 * as the "regset->n" for the xstate regset will be updated based on the feature
382 * capabilites supported by the xsave.
383 */
44210111
RM
384int fpregs_active(struct task_struct *target, const struct user_regset *regset)
385{
386 return tsk_used_math(target) ? regset->n : 0;
387}
1da177e4 388
44210111 389int xfpregs_active(struct task_struct *target, const struct user_regset *regset)
1da177e4 390{
44210111
RM
391 return (cpu_has_fxsr && tsk_used_math(target)) ? regset->n : 0;
392}
1da177e4 393
44210111
RM
394int xfpregs_get(struct task_struct *target, const struct user_regset *regset,
395 unsigned int pos, unsigned int count,
396 void *kbuf, void __user *ubuf)
397{
aa283f49
SS
398 int ret;
399
44210111
RM
400 if (!cpu_has_fxsr)
401 return -ENODEV;
402
67e97fc2 403 ret = fpu__unlazy_stopped(target);
aa283f49
SS
404 if (ret)
405 return ret;
44210111 406
29104e10
SS
407 sanitize_i387_state(target);
408
44210111 409 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
86603283 410 &target->thread.fpu.state->fxsave, 0, -1);
1da177e4 411}
44210111
RM
412
413int xfpregs_set(struct task_struct *target, const struct user_regset *regset,
414 unsigned int pos, unsigned int count,
415 const void *kbuf, const void __user *ubuf)
416{
417 int ret;
418
419 if (!cpu_has_fxsr)
420 return -ENODEV;
421
67e97fc2 422 ret = fpu__unlazy_stopped(target);
aa283f49
SS
423 if (ret)
424 return ret;
425
29104e10
SS
426 sanitize_i387_state(target);
427
44210111 428 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
86603283 429 &target->thread.fpu.state->fxsave, 0, -1);
44210111
RM
430
431 /*
432 * mxcsr reserved bits must be masked to zero for security reasons.
433 */
86603283 434 target->thread.fpu.state->fxsave.mxcsr &= mxcsr_feature_mask;
44210111 435
42deec6f
SS
436 /*
437 * update the header bits in the xsave header, indicating the
438 * presence of FP and SSE state.
439 */
440 if (cpu_has_xsave)
86603283 441 target->thread.fpu.state->xsave.xsave_hdr.xstate_bv |= XSTATE_FPSSE;
42deec6f 442
44210111
RM
443 return ret;
444}
445
5b3efd50
SS
446int xstateregs_get(struct task_struct *target, const struct user_regset *regset,
447 unsigned int pos, unsigned int count,
448 void *kbuf, void __user *ubuf)
449{
18ecb3bf 450 struct xsave_struct *xsave;
5b3efd50
SS
451 int ret;
452
453 if (!cpu_has_xsave)
454 return -ENODEV;
455
67e97fc2 456 ret = fpu__unlazy_stopped(target);
5b3efd50
SS
457 if (ret)
458 return ret;
459
18ecb3bf
BP
460 xsave = &target->thread.fpu.state->xsave;
461
5b3efd50 462 /*
ff7fbc72
SS
463 * Copy the 48bytes defined by the software first into the xstate
464 * memory layout in the thread struct, so that we can copy the entire
465 * xstateregs to the user using one user_regset_copyout().
5b3efd50 466 */
e7f180dc
ON
467 memcpy(&xsave->i387.sw_reserved,
468 xstate_fx_sw_bytes, sizeof(xstate_fx_sw_bytes));
5b3efd50 469 /*
ff7fbc72 470 * Copy the xstate memory layout.
5b3efd50 471 */
e7f180dc 472 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, xsave, 0, -1);
5b3efd50
SS
473 return ret;
474}
475
476int xstateregs_set(struct task_struct *target, const struct user_regset *regset,
477 unsigned int pos, unsigned int count,
478 const void *kbuf, const void __user *ubuf)
479{
18ecb3bf 480 struct xsave_struct *xsave;
5b3efd50 481 int ret;
5b3efd50
SS
482
483 if (!cpu_has_xsave)
484 return -ENODEV;
485
67e97fc2 486 ret = fpu__unlazy_stopped(target);
5b3efd50
SS
487 if (ret)
488 return ret;
489
18ecb3bf
BP
490 xsave = &target->thread.fpu.state->xsave;
491
e7f180dc 492 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, xsave, 0, -1);
5b3efd50
SS
493 /*
494 * mxcsr reserved bits must be masked to zero for security reasons.
495 */
e7f180dc
ON
496 xsave->i387.mxcsr &= mxcsr_feature_mask;
497 xsave->xsave_hdr.xstate_bv &= pcntxt_mask;
5b3efd50
SS
498 /*
499 * These bits must be zero.
500 */
e7f180dc 501 memset(&xsave->xsave_hdr.reserved, 0, 48);
5b3efd50
SS
502 return ret;
503}
504
44210111 505#if defined CONFIG_X86_32 || defined CONFIG_IA32_EMULATION
1da177e4 506
1da177e4
LT
507/*
508 * FPU tag word conversions.
509 */
510
3b095a04 511static inline unsigned short twd_i387_to_fxsr(unsigned short twd)
1da177e4
LT
512{
513 unsigned int tmp; /* to avoid 16 bit prefixes in the code */
3b095a04 514
1da177e4 515 /* Transform each pair of bits into 01 (valid) or 00 (empty) */
3b095a04 516 tmp = ~twd;
44210111 517 tmp = (tmp | (tmp>>1)) & 0x5555; /* 0V0V0V0V0V0V0V0V */
3b095a04
CG
518 /* and move the valid bits to the lower byte. */
519 tmp = (tmp | (tmp >> 1)) & 0x3333; /* 00VV00VV00VV00VV */
520 tmp = (tmp | (tmp >> 2)) & 0x0f0f; /* 0000VVVV0000VVVV */
521 tmp = (tmp | (tmp >> 4)) & 0x00ff; /* 00000000VVVVVVVV */
f668964e 522
3b095a04 523 return tmp;
1da177e4
LT
524}
525
497888cf 526#define FPREG_ADDR(f, n) ((void *)&(f)->st_space + (n) * 16)
44210111
RM
527#define FP_EXP_TAG_VALID 0
528#define FP_EXP_TAG_ZERO 1
529#define FP_EXP_TAG_SPECIAL 2
530#define FP_EXP_TAG_EMPTY 3
531
532static inline u32 twd_fxsr_to_i387(struct i387_fxsave_struct *fxsave)
533{
534 struct _fpxreg *st;
535 u32 tos = (fxsave->swd >> 11) & 7;
536 u32 twd = (unsigned long) fxsave->twd;
537 u32 tag;
538 u32 ret = 0xffff0000u;
539 int i;
1da177e4 540
44210111 541 for (i = 0; i < 8; i++, twd >>= 1) {
3b095a04
CG
542 if (twd & 0x1) {
543 st = FPREG_ADDR(fxsave, (i - tos) & 7);
1da177e4 544
3b095a04 545 switch (st->exponent & 0x7fff) {
1da177e4 546 case 0x7fff:
44210111 547 tag = FP_EXP_TAG_SPECIAL;
1da177e4
LT
548 break;
549 case 0x0000:
3b095a04
CG
550 if (!st->significand[0] &&
551 !st->significand[1] &&
552 !st->significand[2] &&
44210111
RM
553 !st->significand[3])
554 tag = FP_EXP_TAG_ZERO;
555 else
556 tag = FP_EXP_TAG_SPECIAL;
1da177e4
LT
557 break;
558 default:
44210111
RM
559 if (st->significand[3] & 0x8000)
560 tag = FP_EXP_TAG_VALID;
561 else
562 tag = FP_EXP_TAG_SPECIAL;
1da177e4
LT
563 break;
564 }
565 } else {
44210111 566 tag = FP_EXP_TAG_EMPTY;
1da177e4 567 }
44210111 568 ret |= tag << (2 * i);
1da177e4
LT
569 }
570 return ret;
571}
572
573/*
44210111 574 * FXSR floating point environment conversions.
1da177e4
LT
575 */
576
72a671ce 577void
f668964e 578convert_from_fxsr(struct user_i387_ia32_struct *env, struct task_struct *tsk)
1da177e4 579{
86603283 580 struct i387_fxsave_struct *fxsave = &tsk->thread.fpu.state->fxsave;
44210111
RM
581 struct _fpreg *to = (struct _fpreg *) &env->st_space[0];
582 struct _fpxreg *from = (struct _fpxreg *) &fxsave->st_space[0];
583 int i;
1da177e4 584
44210111
RM
585 env->cwd = fxsave->cwd | 0xffff0000u;
586 env->swd = fxsave->swd | 0xffff0000u;
587 env->twd = twd_fxsr_to_i387(fxsave);
588
589#ifdef CONFIG_X86_64
590 env->fip = fxsave->rip;
591 env->foo = fxsave->rdp;
10c11f30
BG
592 /*
593 * should be actually ds/cs at fpu exception time, but
594 * that information is not available in 64bit mode.
595 */
596 env->fcs = task_pt_regs(tsk)->cs;
44210111 597 if (tsk == current) {
10c11f30 598 savesegment(ds, env->fos);
1da177e4 599 } else {
10c11f30 600 env->fos = tsk->thread.ds;
1da177e4 601 }
10c11f30 602 env->fos |= 0xffff0000;
44210111
RM
603#else
604 env->fip = fxsave->fip;
609b5297 605 env->fcs = (u16) fxsave->fcs | ((u32) fxsave->fop << 16);
44210111
RM
606 env->foo = fxsave->foo;
607 env->fos = fxsave->fos;
608#endif
1da177e4 609
44210111
RM
610 for (i = 0; i < 8; ++i)
611 memcpy(&to[i], &from[i], sizeof(to[0]));
1da177e4
LT
612}
613
72a671ce
SS
614void convert_to_fxsr(struct task_struct *tsk,
615 const struct user_i387_ia32_struct *env)
1da177e4 616
1da177e4 617{
86603283 618 struct i387_fxsave_struct *fxsave = &tsk->thread.fpu.state->fxsave;
44210111
RM
619 struct _fpreg *from = (struct _fpreg *) &env->st_space[0];
620 struct _fpxreg *to = (struct _fpxreg *) &fxsave->st_space[0];
621 int i;
1da177e4 622
44210111
RM
623 fxsave->cwd = env->cwd;
624 fxsave->swd = env->swd;
625 fxsave->twd = twd_i387_to_fxsr(env->twd);
626 fxsave->fop = (u16) ((u32) env->fcs >> 16);
627#ifdef CONFIG_X86_64
628 fxsave->rip = env->fip;
629 fxsave->rdp = env->foo;
630 /* cs and ds ignored */
631#else
632 fxsave->fip = env->fip;
633 fxsave->fcs = (env->fcs & 0xffff);
634 fxsave->foo = env->foo;
635 fxsave->fos = env->fos;
636#endif
1da177e4 637
44210111
RM
638 for (i = 0; i < 8; ++i)
639 memcpy(&to[i], &from[i], sizeof(from[0]));
1da177e4
LT
640}
641
44210111
RM
642int fpregs_get(struct task_struct *target, const struct user_regset *regset,
643 unsigned int pos, unsigned int count,
644 void *kbuf, void __user *ubuf)
1da177e4 645{
44210111 646 struct user_i387_ia32_struct env;
aa283f49 647 int ret;
1da177e4 648
67e97fc2 649 ret = fpu__unlazy_stopped(target);
aa283f49
SS
650 if (ret)
651 return ret;
1da177e4 652
60e019eb 653 if (!static_cpu_has(X86_FEATURE_FPU))
e8a496ac
SS
654 return fpregs_soft_get(target, regset, pos, count, kbuf, ubuf);
655
60e019eb 656 if (!cpu_has_fxsr)
44210111 657 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
86603283 658 &target->thread.fpu.state->fsave, 0,
61c4628b 659 -1);
1da177e4 660
29104e10
SS
661 sanitize_i387_state(target);
662
44210111
RM
663 if (kbuf && pos == 0 && count == sizeof(env)) {
664 convert_from_fxsr(kbuf, target);
665 return 0;
1da177e4 666 }
44210111
RM
667
668 convert_from_fxsr(&env, target);
f668964e 669
44210111 670 return user_regset_copyout(&pos, &count, &kbuf, &ubuf, &env, 0, -1);
1da177e4
LT
671}
672
44210111
RM
673int fpregs_set(struct task_struct *target, const struct user_regset *regset,
674 unsigned int pos, unsigned int count,
675 const void *kbuf, const void __user *ubuf)
1da177e4 676{
44210111
RM
677 struct user_i387_ia32_struct env;
678 int ret;
1da177e4 679
67e97fc2 680 ret = fpu__unlazy_stopped(target);
aa283f49
SS
681 if (ret)
682 return ret;
683
29104e10
SS
684 sanitize_i387_state(target);
685
60e019eb 686 if (!static_cpu_has(X86_FEATURE_FPU))
e8a496ac
SS
687 return fpregs_soft_set(target, regset, pos, count, kbuf, ubuf);
688
60e019eb 689 if (!cpu_has_fxsr)
44210111 690 return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
60e019eb
PA
691 &target->thread.fpu.state->fsave, 0,
692 -1);
44210111
RM
693
694 if (pos > 0 || count < sizeof(env))
695 convert_from_fxsr(&env, target);
696
697 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &env, 0, -1);
698 if (!ret)
699 convert_to_fxsr(target, &env);
700
42deec6f
SS
701 /*
702 * update the header bit in the xsave header, indicating the
703 * presence of FP.
704 */
705 if (cpu_has_xsave)
86603283 706 target->thread.fpu.state->xsave.xsave_hdr.xstate_bv |= XSTATE_FP;
44210111 707 return ret;
1da177e4
LT
708}
709
1da177e4
LT
710/*
711 * FPU state for core dumps.
60b3b9af
RM
712 * This is only used for a.out dumps now.
713 * It is declared generically using elf_fpregset_t (which is
714 * struct user_i387_struct) but is in fact only used for 32-bit
715 * dumps, so on 64-bit it is really struct user_i387_ia32_struct.
1da177e4 716 */
3b095a04 717int dump_fpu(struct pt_regs *regs, struct user_i387_struct *fpu)
1da177e4 718{
1da177e4 719 struct task_struct *tsk = current;
f668964e 720 int fpvalid;
1da177e4
LT
721
722 fpvalid = !!used_math();
60b3b9af
RM
723 if (fpvalid)
724 fpvalid = !fpregs_get(tsk, NULL,
725 0, sizeof(struct user_i387_ia32_struct),
726 fpu, NULL);
1da177e4
LT
727
728 return fpvalid;
729}
129f6946 730EXPORT_SYMBOL(dump_fpu);
1da177e4 731
60b3b9af 732#endif /* CONFIG_X86_32 || CONFIG_IA32_EMULATION */